Abstract: The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.

Abstract: An amount is divided into equal portions (n) in a manner which eliminates rounding errors or remainders and has repeatable results.

Abstract: A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.

Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.

Abstract: Methods and a system are disclosed for one or more appliances including a controller for managing power consumption within a household. The controller is configured to receive and process a signal indicative of one or more energy parameters of an associated energy utility, including at least a peak demand period or an off-peak demand period. A generated serial number is obtained from an original serial number of the appliance or controller, which is configured for a signal to communicate to the appliance within a population and command the appliance to operate in an energy savings mode and a normal mode at various time periods. The generated serial number (GSN) is used to segregate a total population into segments to provide granularity in assigning DR activations and deactivations based upon the GSN.

Abstract: The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: A method of adjusting a network data sending speed according to a data processing speed at a client is described. Through calculating and feeding back a data processing speed of a client computer to a server; and then, controlling and adjusting a data sending speed at the server in real time according to the data processing speed, the server adjusts the data sending speed thereof in real time according to the requirement on speed control, and sends data to the client computer at an adjusted data sending speed. This method controls and adjusts the data sending speed at the server through a feedback mechanism of the data processing speed of the client computer, thereby avoiding problems in the conventional art, such as low network data transmission efficiency and data loss, caused by mismatching between the data processing speed at the client and the data sending speed at the server.

Abstract: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2? to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.

Abstract: A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.

Abstract: A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder.

Abstract: A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

Abstract: A method of decimal division in a superscalar processor comprising: obtaining a first operand and a second operand; establishing a dividend and a divisor from the first operand and the second operand; determining a quotient digit and a resulting partial remainder; based on multiple parallel/simultaneous subtractions of at least one of the divisor and a multiple of the divisor from the dividend, utilizing dataflow elements of multiple execution pipes of the superscalar processor.

Abstract: A divider circuit provides a divide operation with a multiplier, counter and comparator. The divide operation of two values, x and y, to produce the value of x divided by y, x/y, is provided by sequentially multiplying y in the multiplier with values from the counter until the product of y and a current counter value is determined to cross a unity level, or "1," as determined by a comparator. Therefore, the current value in the counter is approximately equal to 1/y. Then, the determined value of 1/y is multiplied by x to provide x/y. A preferred embodiment of the divider circuit employs a single multiplier, and the divide circuit includes a mux, a multiplier, a counter, a comparator, and an optional buffer. The mux receives two values x and y and a selection signal provided by the comparator. The counter is loaded with an initial value, which may be a zero dataword.