Abstract: A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.

Abstract: Barrel-shifters may be implemented in field programmable gate array (FPGA) using digital signal processor (DSP) multipliers, rather than consuming lookup table (LUT) resources. This advantageously uses otherwise under-utilized assets, leaving previously heavily-burdened LUT resources available for other uses. Building blocks of 8-bit and 4-bit DSP-based shifters are implemented in parallel sets for wide data and in tandem stages for larger shifts. For example, a 32-bit barrel-shifter may be implemented using a set of seven (7) parallel 8-bit shifters to handle the width of the data in a first stage and another set of eight (8) parallel 4-bit shifters in a second stage that operates in tandem with the first stage, to complete the shift. In an example, the first stage provides fine shifting and the second stage provides coarse shifting. To achieve even wider barrel-shifters, for example a 256-bit shifter, 32-bit barrel-shifter may be used recursively.

Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.

Abstract: Computerized systems, and method and computer readable media. The method may include receiving, by a neural network, input face visual information; wherein the neural network comprises multiple convolutional layers, an embedding layer and one or more conversion layers; generating, by the embedding layer, a face recognition (FR) feature vector that comprises multiple FR feature elements; applying a soft function on the multiple FR feature elements, by the one or more conversion layers, to provide a converted FR feature vector that comprises multiple converted FR feature elements that are non-binary; and generating a binary representation of the face recognition features based on the converted FR feature vector.

Abstract: Computerized systems, and method and computer readable media. The method may include receiving, by a neural network, input face visual information; wherein the neural network comprises multiple convolutional layers, an embedding layer and one or more conversion layers; generating, by the embedding layer, a face recognition (FR) feature vector that comprises multiple FR feature elements; and generating a binary representation of the face recognition features based on the FR feature vector.

Abstract: A reverse time migration imaging method for cased-hole based on ultrasonic pitch-catch measurement, including: calculating a theoretical dispersion curve; expanding original Lamb data of two receivers into array waveform data based on phase-shift interpolation; establishing a two-dimensional migration velocity model including density, P-wave velocity and S-wave velocity of a target area; generating and storing a forward propagating ultrasonic wavefield for each time step; reversing a time axis; generating and storing a reversely propagating ultrasonic Lamb wavefield for the two receivers after phase-shift interpolation; calculating envelopes of the forward propagating ultrasonic Lamb wavefield and the reversely propagating ultrasonic Lamb wavefield; applying a zero-lag cross-correlation imaging condition to obtain reverse time migration imaging results; and applying Laplace filtering to suppress low-frequency imaging noises in the imaging results.

Abstract: A controller is configured to control the adaptive notch filter and to execute a search technique (e.g., artificial intelligence (AI) search technique) to converge on filter coefficients and to recursively adjust the filter coefficients of the adaptive notch filter in real time to adaptively adjust one or more filter characteristics (e.g., maximum notch depth or attenuation, bandwidth of notch, or general magnitude versus frequency response of notch).

Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.

Abstract: Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

Abstract: A controller is configured to control the adaptive notch filter and to execute a search technique (e.g., artificial intelligence (AI) search technique) to converge on filter coefficients and to recursively adjust the filter coefficients of the adaptive notch filter in real time to adaptively adjust one or more filter characteristics (e.g., maximum notch depth or attenuation, bandwidth of notch, or general magnitude versus frequency response of notch).

Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Abstract: The present disclosure advantageously provides a mixed precision computation (MPC) unit for executing one or more mixed-precision layers of an artificial neural network (ANN). The MPC unit includes a multiplier circuit configured to input a pair of operands and output a product, a first adder circuit coupled to the multiplier circuit, a second adder circuit, coupled to the first adder circuit, configured to input a pair of operands, an accumulator circuit, coupled to the multiplier circuit and the first adder circuit, configured to output an accumulated value, and a controller, coupled to the multiplier circuit, the first adder circuit, the second adder circuit and the accumulator circuit, configured to input a mode control signal. The controller has a plurality of operating modes including a high precision mode, a low precision add mode and a low precision multiply mode.

Abstract: A computer-implemented method for Eigenpair computation is provided. The method includes computing, her a hardware processor, an Eigenvector and respective Eigenvalues of the Eigenvector of a matrix by using a modified Stochastic Optimization process including performing a matrix vector product on a Resistive Processing Unit (RPU) crossbar array operatively coupled to the hardware processor and performing a scalar vector product on a digital device operatively coupled to the hardware processor and representing, for each of an Eigenpair, an initial guess for the Eigenvector and the respective Eigenvalues. The computing step includes storing the matrix in the RPU crossbar array.

Abstract: A method of predicting an electronic structure of a material by an electronic apparatus includes receiving user's input data about elements constituting the material; applying the received user's input data to a trained model for estimating a state density of the material; and outputting a first graph representing energy level-by-level state densities of the material output from the trained model, wherein the trained model is trained to generate the first graph based on a plurality of second graphs representing pre-calculated energy level-by-level state densities respectively corresponding to a plurality of pre-input data about elements of various materials and the plurality of pre-input data.

Abstract: A method for outsourcing exponentiation in a private group includes executing a query instruction to retrieve a query element stored on an untrusted server by selecting a prime factorization of two or more prime numbers of a modulus associated with the query element stored on the server, obtaining a group element configured to generate a respective one of the prime numbers, generating a series of base values using the prime factorization and the group element, and transmitting the series of base values from the client device to the server. The server is configured to determine an exponentiation of the group element with an exponent stored on the server using the series of base values. The method also includes receiving a result from the server based on the exponentiation of the group element with the exponent.

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

Abstract: An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Abstract: A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Abstract: The disclosure generally relates to principal component analysis (PCA) computation and, more particularly, to concurrent PCA computation. In one embodiment, a plurality of concurrent PCA requests are received by a server. An input matrix for each of the concurrent PCA requests is computed using a general purpose-graphical processing unit (GP-GPU) by the server. Further, tridiagnolization on the input matrix is performed on each of the concurrent PCA requests by a general purpose-graphical processing unit (GP-GPU) in the server to generate a tridiagonal matrix for each of the concurrent PCA requests. Furthermore, a plurality of eigen values and corresponding eigen vectors are computed for the tridiagonal matrix of each of the concurrent PCA requests by the server and subsequently back transformation of the eigen values and the eigen vectors is performed by the server for each of the concurrent PCA requests to obtain associated principal components.

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

Abstract: An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.

Abstract: A division operation apparatus is provided. The division operation apparatus includes a memory, a non-zero bit detection circuit, a mapping calculation circuit, a look-up circuit, a compensation circuit and a multiplication circuit. The memory stores a divisor look-up table including a plurality of entries. The non-zero bit detection circuit detects a number of a highest non-zero bit of the divisor. The mapping calculation circuit generates a mapped value of the divisor within a range of the divisor look-up table according to a mapping function. The look-up circuit retrieves a corresponding entry having a stored reciprocal according to the mapped value. The compensation circuit generates a compensation value according to the mapping function. The multiplication circuit multiplies a dividend, the stored reciprocal and the compensation value to generate a divided result of the dividend and the divisor.

Abstract: A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation.

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

Abstract: In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

Abstract: A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result.

Abstract: A system and method for reducing central processing unit transistor count when dividing multiple floating point numbers is disclosed. An example system may receive a plurality of floating point numbers to be inverted as denominator values. The denominator values may be grouped into pairs and multiplied. Products of pairs may be multiplied to produce combinations of products of denominator values until all denominator values have been multiplied together. The product of all denominator values may be inverted using a single division. The combinations of products of denominator values from the multiplications achieved before the division may be multiplied with the inverted product from the division to compute inversions of all denominator values. In some embodiments, an example system may receive a plurality of floating point numbers as numerator values that each correspond to a denominator value. Numerator values may be multiplied with corresponding inversion denominator values to produce division results.

Abstract: A normalized n-bit value is converted into a normalized m-bit value in accordance with a predetermined rounding mode. An initial m-bit value is determined, where the bits of the initial m-bit value are equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the normalized n-bit value. An output state is selected based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode. The output state indicates how the normalized m-bit value is to be determined from the initial m-bit value. In accordance with the selected output state, the normalized m-bit value is determined to be equal to one of a plurality of candidate m-bit values, wherein the plurality of candidate m-bit values consists of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one.

Abstract: A system and method for reducing central processing unit usage when inverting or dividing multiple floating point numbers is disclosed. An example system may receive a plurality of floating point numbers to be inverted as denominator values. The denominator values may be grouped into pairs and multiplied. Products of pairs may be multiplied to produce combinations of products of denominator values until all denominator values have been multiplied together. The product of all denominator values may be inverted using a single division. The combinations of products of denominator values from the multiplications achieved before the division may be multiplied with the inverted product from the division to compute inversions of all denominator values. In some embodiments, an example system may receive a plurality of floating point numbers as numerator values that each correspond to a denominator value. Numerator values may be multiplied with corresponding inversion denominator values to produce division results.

Abstract: One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a four-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for overall performance that is comparable to the best available high-performance alternatives.

Abstract: A complex divider utilized for dividing a first complex number by a second complex number to generate a computing result includes a computing unit and a dividing unit. The computing unit is utilized for receiving the first complex value and the second complex value, generating a third complex value according to the first complex value and the second complex value, and generating a real number according to the second complex value. The dividing unit is coupled to the computing unit, and is utilized for receiving the third complex value and the real number and dividing the third complex value by the real number to obtain the computing result.

Abstract: A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.

Abstract: A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.

Abstract: A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Abstract: The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2n<N?2n+1; performing an initialization operation by initializing a constant a to the smallest integer greater than or equal to half of N; performing a first operation by subtracting, when C is greater than or equal to N·a (product of N and a), the value of C by the value of N·a; and performing a second operation by assigning the smallest integer greater than or equal to half of a to the value of a, wherein the value of C is output as the result of modulo operation after the first operation and the second operation are repeated n times. In the first operation, when C is less than N·a, the value of C is unchanged.

Abstract: A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N1?N, and the exponent is i?1; wherein the right shift registers shift the first constant value to the right for h*i-digit for outputting a second constant value; wherein the multiplier multiplies a third constant value by the constant value M?N*S1 for outputting a fourth constant value, wherein the first adder adds up the estimate S1 and the fourth constant value for outputting the quotient S. The present invention also provides an implement method therefor.

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract: Systems, apparatus and methods are described related to optimizing fixed point divide.

Abstract: The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.

Abstract: A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.

Abstract: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

Abstract: An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.

Abstract: A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.

Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: A divider logic circuit for obtaining a quotient S of a dividend M divided by a divisor N, includes a first constant value input terminal, a first adder, a second constant value input terminal, a base number input terminal, at least one integer power device, at least one right shift register, a second adder, and a multiplier; wherein the integer power device determines a first constant value that the base number is N1?N, and the exponent is i?1; wherein the right shift registers shift the first constant value to the right for h*i-digit for outputting a second constant value; wherein the multiplier multiplies a third constant value by the constant value M?N*S1 for outputting a fourth constant value, wherein the first adder adds up the estimate S1 and the fourth constant value for outputting the quotient S. The present invention also provides an implement method therefor.

Abstract: The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is optimized for a second range of divisor values; the first range is distinct from the second range. During operation, the circuit receives a divisor for the division operation. The circuit: determines whether the divisor is in the first range or the second range to determine whether the first divider or the second divider should perform the division operation; performs the division operation in the selected host divider; and then outputs the result that was generated by the selected host divider.

Abstract: An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.

Abstract: One or more embodiments of the invention set forth techniques to perform integer division using a floating point hardware unit supporting floating point variables of a certain bit size. The numerator and denominator are integers having a bit size that is greater than the bit size of the floating point variables supported by the floating point hardware unit. Error correcting techniques are utilized to account for any loss of precision caused by the floating point operations.

Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.