Comparison Patents (Class 708/671)
  • Patent number: 11036503
    Abstract: Processing circuitry selectively applies vector processing operations to one or more data items of one or more data vectors. Each data vector comprises a plurality of data items at respective vector positions in the data vector according to the state of respective predicate indicators associated with the vector positions. Predicate generation circuitry apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in a predicate store.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 15, 2021
    Assignee: ARM LIMITED
    Inventors: Gary Alan Gorman, Lee Evan Eisen, Neil Burgess, Daniel Arulraj
  • Patent number: 10901692
    Abstract: An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: January 26, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Indu Prathapan, Puneet Sabbarwal, Pankaj Gupta
  • Patent number: 10705843
    Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
  • Patent number: 10445092
    Abstract: A processor for performing a vector permute comprises: a source vector register to store a plurality of source data elements; a destination vector register to store a plurality of destination data elements; a control vector register to store a plurality of control data elements, each control data element corresponding to one of the destination data elements and including an N bit value indicating whether a source data element is to be copied to the corresponding destination data element; vector permute logic to compare the N bit value of each control data element to an N bit portion of an immediate to determine whether to copy a source data element to the corresponding destination data element, wherein if the N bit values match, then the vector permute logic is to identify a source data element using an index value included in the control data element.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Jesus Corbal San Adrian, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney, Milind B. Girkar, Bret L. Toll, Roger Espasa, Guillem Sole, Jairo Balart, Brian Hickman
  • Patent number: 9720646
    Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 1, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz, Christopher Neal Hinds
  • Patent number: 9043379
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 9037626
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark J. Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 9037627
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 19, 2015
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 8751557
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: June 10, 2014
    Assignee: Robert T. and Virginia T. Jenkins
    Inventors: Richard Crandall, Karl Schiffmann
  • Publication number: 20140040342
    Abstract: In described embodiments, a trellis decoder includes a memory including a set of registers; and an add-compare-select (ACS) module including at least two ACS layer modules coupled in series and configured to form a feedback loop with carry components in a single clock cycle, wherein the ACS layer module includes at least two branch metrics represented by a plurality of bits and adders configured to generate a plurality of state metrics using carry-save arithmetic, and a plurality of multiplexers configured to perform a selection of a maximum state metric in carry-save arithmetic stored in memory as the carry components. A method of performing high speed ACS operation is disclosed.
    Type: Application
    Filed: April 24, 2013
    Publication date: February 6, 2014
    Applicant: LSI Corporation
    Inventors: Andrey P. Sokolov, Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Yurii S. Shutkin
  • Patent number: 8606841
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark J. Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 8554823
    Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Shriram D. Moharil
  • Patent number: 8489664
    Abstract: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: July 16, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Linh Do, Wei Fu, Arash Farhoodfar
  • Patent number: 8489665
    Abstract: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2? to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Limited
    Inventors: Fuyuta Sato, Hideo Okawa
  • Patent number: 8484236
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions. In particular embodiments, a character expression may be represented as a concatenation of binary representations of individual characters in the character expression to provide a binary string. The binary string may then be processed by applying a binary arithmetic operator to provide a comparison.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: July 9, 2013
    Assignee: Robert T. Jenkins and Virginia T. Jenkins
    Inventors: Mark Andrews, Richard Crandall, Karl Schiffmann
  • Patent number: 8407276
    Abstract: Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: March 26, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chun Gi Lyuh, Ik Jae Chun, Jung Hee Suk, Tae Moon Roh, Jong Kee Kwon, Jong Dae Kim
  • Patent number: 8407275
    Abstract: A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Michael Kroener, Silvia M. Mueller, Jochen Preiss
  • Patent number: 8402078
    Abstract: A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Weinberg, Martin S. Schmookler
  • Patent number: 8380779
    Abstract: A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: February 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Klas M. Bruce, Michael D. Snyder, Ravindraraj Ramaraju, David R. Bearden
  • Patent number: 8380780
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Publication number: 20120054257
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Applicant: Robert T. and Virginia Jenkins as Trustees for the Jenkins Family Trust Dated February 8, 2002
    Inventors: Richard Crandall, Karl Schiffmann
  • Patent number: 8117422
    Abstract: The core of this invention is the application of a fast comparison circuit to the problem of address translation. Traditional implementations generate the virtual address and the physical address in series. This invention generates the physical address and virtual address simultaneously. A bitwise operation on the base address, the offset address and each stored virtual address determines whether the base address and offset address sum equals the virtual address without requiring a carry propagate. Circular addressing is implemented in the match determination by masking bits corresponding to the circular address limit.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: February 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Kai Chirca
  • Patent number: 8073893
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 6, 2011
    Inventors: Richard Crandall, Karl Schiffmann
  • Patent number: 8037120
    Abstract: An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N?1:0] and a second N-bit vector B[N?1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N?1:0] & ˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N?1:0]^˜B[N?1:0]) operation using A[N?1:0] and ˜B[N?1:0]. The difference between the first N-bit vector A[N?1:0] and the second N-bit vector B[N?1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 11, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Abhijit Giri
  • Patent number: 7991820
    Abstract: The ONE STEP BINARY SUMMARIZER is a digital logic circuit. It is used for summarizing two binary numbers. It contains one Function Generator Module and one or more SUMMARIZER Units. For subtraction it is subtracting Register “A” from Register “B” and Register “B” from Register “A”. The two subtraction and one addition operations are executed simultaneously. The Function Generator Module determines the actual correct operation, (addition or subtraction) and selects the correct results for the resultant operand. The circuit utilizes the subtraction-by-carry method; therefore the subtraction operation does not require any presorting, complementary operations, iterative additions, temporary storage, and multiple instruction sets, etc. The logic-flow is similar, the operational speed is identical for the addition and subtraction operations; and therefore, it is a true Time Symmetrical circuit. It is independent from the initial operation selection, the signs and magnitudes of the input operands.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: August 2, 2011
    Inventor: Leslie Imre Sohay
  • Patent number: 7973566
    Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 5, 2011
    Assignees: University of Florida Research Foundation, Inc., Control Dynamics, Inc.
    Inventors: William L. Ditto, Krishnamurthy Murali, Sudeshna Sinha, Abraham Miliotis
  • Patent number: 7958181
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 7836111
    Abstract: To detect a change in data produced by a system, predicted data values for plural time points are computed. Actual data values for the plural time points are received, and residual values are derived from differences between the predicted data values and actual data values. Based on the computed residual values, a time point at which the change in data occurred is determined.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 16, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jerry Z. Shan
  • Publication number: 20100235673
    Abstract: An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs.
    Type: Application
    Filed: September 30, 2008
    Publication date: September 16, 2010
    Applicant: RAMBUS INC.
    Inventor: Aliazam Abbasfar
  • Publication number: 20090292757
    Abstract: A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor 115 in use is connected by a controller 110 to an arithmetic unit 120. Different embodiments of the invention for use in addition include inverters 205 connected via incrementers 220 to comparators 235 for subtraction and comparators 235 for decrementation. The method includes determination 915 of which arithmetic operation to be performed, activation 925, 950 and 975 of a suitable zero prediction method for the operation along with the operation subtraction 930, addition 955 and decrementation 980. If a zero is detected, operations 930, 955 and 980 are deactivated.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 26, 2009
    Inventor: Steven Leeland
  • Patent number: 7620676
    Abstract: Input data is divided into a plurality of blocks, and the blocks are corresponded to each address of the lookup table, and a block is divided into a plurality of sections according to the change of the output data, and at this time position information to indicates the boundary of the section, and output data in each section are stored in an address corresponding to each block, so that the memory capacity required for the lookup table can be decreased.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: November 17, 2009
    Assignee: Fujitsu Limited
    Inventors: Shigeaki Okutani, Toshiro Nakazuru, Noboru Morita
  • Publication number: 20090172070
    Abstract: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.
    Type: Application
    Filed: March 6, 2009
    Publication date: July 2, 2009
    Inventors: Viet Linh Do, Wei Fu, Arash Farhoodfar
  • Publication number: 20080288565
    Abstract: A binary data comparison method is performed as follows. First, bits of a plurality of binary data are provided, and bit x of the plurality of binary data are summed, where x=n, n?1, . . . , 1 or 0, and bit x is the most significant bit (MSB). If the sum is equal to 1, the binary data having bit x=1 is determined as the maximum. If the sum is larger than or equal to 2, the binary data having bit x=0 is masked by setting all bits of the binary data to zero. The above processes are repeated in which bit x is iterated by bit x?1 if the sum is not equal to 1 until the maximum is found.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Hung Shih Lin
  • Publication number: 20080263123
    Abstract: There is provided a system for determining a minimum number and a penultimate minimum number in a set of numbers. According to one embodiment, the system includes a first comparator module configured to receive a first subset of the set of numbers and to compare the first subset to determine a first minimum number and a first penultimate minimum number. The system also includes a second comparator module configured to receive a second subset of the set of numbers and to compare the second subset to determine a second minimum number and a second penultimate minimum number. The system further includes a third comparator module configured to receive and compare the first and second minimum numbers and the first and second penultimate minimum numbers to determine the minimum number and the penultimate minimum number in the set of numbers.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Inventor: Paul Penzes
  • Publication number: 20080255710
    Abstract: Embodiments of the present invention provide a system that dynamically controls a temperature profile within a computer system by generating computer system activity. The system starts by receiving a desired temperature profile. The system then generates a load profile based on the desired temperature profile, wherein the load profile specifies operations to be performed by the computer system. The system next executes the load profile on the computer system to generate computer system activity, wherein the computer system activity causes the desired temperature profile in the computer system.
    Type: Application
    Filed: April 12, 2007
    Publication date: October 16, 2008
    Inventors: Kalyanaraman Vaidyanathan, Kenny C. Gross
  • Patent number: 7437402
    Abstract: Apparatus and method for performing a high-speed, low-power bit-wise comparison of two digital words. For each bit, a bit comparator is shown, employing a compare node and a discharge node. After both nodes are charged, the discharge node is discharged and the condition of the compare node signals the result of the comparison. For each bit, a bit comparator is provided including a single transistor switch across the compare node and the discharge node. An exclusive-OR circuit connected to receive the corresponding bits of the words drives and selectively actuates the switch when the values of the corresponding bits are mismatched. Words may be segmented such that comparisons may be done segment-wise and the detection of a mismatch in any segment obviates the discharging of the compare node in segments containing more significant bits, to save power.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: October 14, 2008
    Assignee: Analog Devices, Inc.
    Inventor: Richard P. Schubert
  • Patent number: 7434034
    Abstract: The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30, 2004 and entitled SIMD PROCESSOR AND ADDRESSING METHOD.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: October 7, 2008
    Assignee: ATI Technologies Inc.
    Inventors: Richard J. Selvaggi, Larry A. Pearlstein
  • Patent number: 7395303
    Abstract: A system and method for comparing binary data words are provided, which method includes splitting a first and a second data word (A, B) to be compared to one another into at least two subwords, one having high-order bits (hA, hB) and the other having low-order bits (nA, nB), and separately comparing each pair of the corresponding two subwords (hA, hB; nA, nB) in a separate comparing device. The intermediate comparison results of the comparing devices are gated in a logic device, e.g., an AND gate, to yield an overall result as a function of a control signal which is applied to a correction device, which is connected between at least one of the comparing devices and the logic device.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: July 1, 2008
    Assignee: Robert Bosch GmbH
    Inventors: Reinhard Weiberle, Thomas Kottke
  • Patent number: 7395304
    Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit. This adjustment causes the arithmetic circuit to generate a valid outcome in redundant form as a result of a subtraction operation if the arithmetic operation is subtraction.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: July 1, 2008
    Assignee: Intel Corporation
    Inventors: Bharat Bhushan, Vinod Sharma, Edward Grochowski, John Crawford
  • Publication number: 20080140754
    Abstract: A device for checking numbers consists of a multiplexer (101) with a controller module (106) linked to it. An output of the multiplexer is connected to a first input of a register (102), which is an element of memory, while a first output of the controller module (106) is connected to an input of a memory (103) and a second input of the register (102). An output of the register (102) and an output of the memory (103) are connected to inputs of the adder (104), which adds on its output a number, stored in the register (102) and a number written in the memory (103) at an address indicated by the controller module (106). The adder (104) generates on its output a carry-out signal, informing about overflow, which is passed to a first controlling input of the controller module (106), which manages operation of the device checking numbers.
    Type: Application
    Filed: February 4, 2008
    Publication date: June 12, 2008
    Applicant: ADVANCED DIGITAL BROADCAST S.A.
    Inventor: Sebastian ZYLOWSKI
  • Publication number: 20080133625
    Abstract: A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an old discarded sample, is calculated for each component filter. A desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition. Using circuits running at a multiple of the sampling clock, multiple running sums may be implemented on the same hardware. A whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic. The invention saves significant chip resources and manufacturing costs.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 5, 2008
    Inventor: Radu Alexandru
  • Publication number: 20080052339
    Abstract: A circuit and a method of examining in a microprocessor a section of a first range of values and a second range of values each comprising a lower boundary value and an upper boundary value is disclosed. The method includes examining whether a value of the first range of values is equal to or greater than the lower boundary value of the second range of values, and examining whether the lower boundary value of the first range of values is smaller than or equal to the upper boundary value of the second range of values.
    Type: Application
    Filed: August 25, 2006
    Publication date: February 28, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mohr, Harry Siebert
  • Patent number: 7322032
    Abstract: A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specific queue scheduling requirements for the computerized device. The computerized device extracts a first time stamp value and a second time stamp value associated with a first queue and a second queue, respectively. The computerized device receives instructions to configure a table of the GSP with scheduling entries. The computerized device compares the first time stamp value with the second time stamp value to form a comparison result. The computerized device then selects a decision instruction from the table, based upon the comparison result, and identifies a preferred queue of the first queue and the second queue, based upon the decision instruction.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: January 22, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Gregory S. Goss, Albert A. Slane, Christopher J. Kappler
  • Patent number: 7284028
    Abstract: An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Wei Hwang, Kun Wu
  • Patent number: 7233964
    Abstract: A method and system for compositing a plurality of three-dimensional Sub-Images by examining the Depth values of the Pixels corresponding to same spatial location in each Sub-Image and compositing the content of the Pixel having the greatest Depth value. The Depth values are divided into two or more binary Segments, where the bit length of the Segments is determined according to their level of significance. In a first step, the numerical values of the Segments having the same level of Significance are simultaneously compared, and accordingly a group designating the Depth values which the numerical value of their Most Significant Segment is the greatest is determined, and a Grade is evaluated for the Least Significant Segments indicating their numerical size in comparison with the numerical value of the other Segments of the same level of significance.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Lucid Information Technology Ltd.
    Inventors: Reuven Bakalash, Ofir Remez
  • Patent number: 7191359
    Abstract: A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operations; a plurality of data storage elements for storing respective results of the arithmetic and logical operations of the plurality of the processors; a comparator for comparing the results of the arithmetic and logical operations of the plurality of the processors stored in the plurality of the data storage elements; and a comparison record storage element for storing a record of the comparison results of the comparator.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: March 13, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Kotaro Shimamura, Naohiro Ikeda, Takeshi Takehara
  • Patent number: 7103624
    Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An?1An?2 . . . A1A0 and a second binary data Bn?1Bn?2 . . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation: F(A?B)=A(n?1)?·B(n?1)+(A(n?1)?+B(n?1))·{A(n?2)?·B(n?2)+(A(n?2)?+B(n?2)) . . . {A1?·B1+(A1?+B1)·(A0?+B0)}} where subscripts denote a position of a bit of the N-bit binary data and a prime (?) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Ltd., Co.
    Inventors: Ji-Sun Shin, Jae-Jin Lee, You-Pyo Hong
  • Patent number: 7020830
    Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b?c?d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.
    Type: Grant
    Filed: December 24, 2001
    Date of Patent: March 28, 2006
    Assignee: Agere Systems Inc.
    Inventors: Paul Gerard D'Arcy, Rajan V. K. Pillai
  • Patent number: 7016931
    Abstract: A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of transistors, arranged in 4 columns (201, 202, 203, 204) of N rows of transistors arranged in order, so as to control the gates of the transistors; the matrix, which receives, at the sources of the transistors of two (203, 204) of the columns, the signals representative of the bits of one of the numbers compared and their negated signals, is interconnected in a manner such as to identify the most significant difference by a simultaneous logic process, and to decide, on the basis of the bit signals received, which of the binary numbers is greater than, or greater than or equal to the other, presenting the outcome of the decision at an output (U2) within a very short time and with the use of much fewer active components than are required by conventional combin
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: March 21, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventor: Luigi Pascucci
  • Patent number: 6938172
    Abstract: A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums the number of logic transitions. The transformation algorithm is applied to the new data vector only if it would reduce the resulting number of transitions, otherwise the data vector is propagated unmodified. Bit inversion is a data transformation algorithm according to the present invention that provides up to a 50% reduction in the number of logic transitions.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: August 30, 2005
    Assignee: Tektronix, Inc.
    Inventor: Michael S. Hagen