Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An?1An?2 . . . A1A0 and a second binary data Bn?1Bn?2 . . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation: F(A?B)=A(n?1)?·B(n?1)+(A(n?1)?+B(n?1))·{A(n?2)?·B(n?2)+(A(n?2)?+B(n?2)) . . . {A1?·B1+(A1?+B1)·(A0?+B0)}} where subscripts denote a position of a bit of the N-bit binary data and a prime (?) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.

Abstract: Techniques are provided for the addition and comparison operations associated with a Viterbi decoding algorithm at substantially the same time. To this end, an operation of the type a±b>c±d (where a and b are to be added, c and d are to be added, and then the sums compared to determine the larger of the two sums) can be formulated, in accordance with the invention, into a±b?c?d>0 (where the addition of a and b and of c and d, and their comparison, are substantially concurrently performed). More specifically, in order to facilitate substantially concurrent addition and comparison operations in a Viterbi decoder, in one embodiment, the present invention performs multi-operand addition in a carry save form. With the results of addition represented in carry save form, the evaluation of comparator conditions is relatively straightforward.

Abstract: A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of transistors, arranged in 4 columns (201, 202, 203, 204) of N rows of transistors arranged in order, so as to control the gates of the transistors; the matrix, which receives, at the sources of the transistors of two (203, 204) of the columns, the signals representative of the bits of one of the numbers compared and their negated signals, is interconnected in a manner such as to identify the most significant difference by a simultaneous logic process, and to decide, on the basis of the bit signals received, which of the binary numbers is greater than, or greater than or equal to the other, presenting the outcome of the decision at an output (U2) within a very short time and with the use of much fewer active components than are required by conventional combin

Abstract: A data transformation algorithm is selectively applied to each data vector as it enters the pipelined structure. In a selection step, the algorithm compares the bit value of the new data vector with the corresponding bit values of the preceding data vector, and sums the number of logic transitions. The transformation algorithm is applied to the new data vector only if it would reduce the resulting number of transitions, otherwise the data vector is propagated unmodified. Bit inversion is a data transformation algorithm according to the present invention that provides up to a 50% reduction in the number of logic transitions.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.

Abstract: The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.

Abstract: The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

Abstract: To provide a variety of methods for extracting digital watermark information from an image as correctly as possible. For example, a first pattern arrangement and a second pattern arrangement which is different from the first pattern arrangement for use in a calculation for extracting the digital watermark information are provided. A state of an original image without the digital watermark information embedded is inferred, using a second pattern arrangement, and a reliability of the digital watermark information to be extracted in accordance with the state is determined. Or to decide the embedding position of the digital watermark information from the image data, the extracting start position is discriminated by detecting the positional information by multiple times at the different extracting start positions. Or to detect a geometrical distortion, a registration signal is embedded on the image.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

Abstract: One embodiment of the present invention provides a circuit that performs a prefix computation. This circuit includes an N-bit prefix network comprised of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ∘, such that, Y1=X1, Y2=X2∘X1, Y3=X3∘X2∘X1, . . . , and YN=XN∘XN−1 ∘X2∘X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2t horizontal wiring tracks between each logic level. Additionally, l+f+t=L−1, and unlike existing prefix circuits, l>0, f>0, and t>0.

Abstract: A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

Abstract: Methods and apparatus for comparing two binary numbers with a power-of-two threshold are provided in accordance with the present invention. In one embodiment, a method for comparing two binary numbers with a power-of-two threshold includes the steps of generating new relations, namely, much_greater_than (ggi) and equal_to (nqi), based at least in part on generate (gt) and propagate (eq) signals created for each bit of the binary numbers to be compared, and applying recursion in order to reduce the set of input signals at successive recursive nodes by a predetermined number. By omitting a pre-addition operation, the present invention eliminates the use of exclusive-OR logic gates, thus significantly reducing system cost and delay.

Abstract: A method and apparatus for adding numbers represented in redundant form or for subtracting numbers received in redundant form and for comparing results in redundant form for equality to an expected value. A redundant arithmetic circuit performs an arithmetic operation on operands received in redundant form to generate a result represented in redundant form. A comparator circuit is coupled with the arithmetic circuit to receive the result in redundant form and to perform an equality comparison of the result to the expected value, and to indicate the truth of said equality comparison independent of carry signal propagation from the least significant digit to the most significant digit.

Abstract: In a compiler or program proving or verification software code, it is often useful to analyse a computer program and one way in which this might be partially achieved is by comparing algebraic expressions to see if they are equivalent, i.e. to see if they are derivable from a common template or function definition. Herein a string matching and replacement algorithm is used to compare two functions. Initially, each expression is converted to a “reduced” form by reference to a set of standard rules so as, for example, to ensure that terms comprising the same variables are combined. The variables names in each term are then replaced with symbols to produce, for each expression, a corresponding character string which, arranged in a predetermined order, are compared to determine equivalence of the expressions. To achieve this, a matrix M is formed with entries corresponding to the symbols and the matrix elements are incremented according to pre-set rules.

Abstract: A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weighted sum of input signals to the floating gates of the first comparator stage. Additionally, the double differential comparator can be integrated into fully differential programmable analog integrated circuits. Such fully differential programmable analog integrated circuits can also include a differential output digital-to-analog converter to be used with or without the double differential comparator.

Abstract: A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An−1An−2 . . . A1A0 and a second binary data Bn−1Bn−2 . . .

Abstract: A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: One embodiment of the present invention provides a system for representing intervals within a computer system to facilitate efficient and sharp arithmetic interval operations. The system operates by receiving a representation of two intervals. These representations include a first floating-point number representing a first endpoint of the interval and a second floating-point number representing a second endpoint of the interval. Next, the system performs an interval arithmetic operation using the interval operands to produce an interval result. In performing this arithmetic operation, if the first endpoint is negative infinity and the second endpoint is finite, the system treats the first endpoint as a negative overflow toward negative infinity. On the other hand, if the second endpoint is positive infinity and the first endpoint is finite, the system treats the first endpoint as a positive overflow toward positive infinity.

Abstract: A zero result detector for detecting a zero result in the sum of a first operand A, a second operand B and a carry bit Cin operates by calculating {overscore (A)} and {overscore (A)}+1 and then comparing one of these with B (Cin=O, {overscore (A)}; Cin=1, {overscore (A)}+1) in dependence upon Cin. If the comparison shows equality, then the zero detect result Z is true.

Abstract: In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their fraction parts compared, and a result of each comparison and a sign of each data are used to code a relationship in magnitude between data corresponding to a clipping coordinate and the other data fed. A clip code generated depending on the previously obtained comparison results from exponent part and fraction part compare units, rather than depending on a zero flag according to a result of an addition or a subtraction and a sign of the result of the addition or the subtraction, can rapidly be generated without the circuit increased in scale.

Abstract: The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Abstract: Source data can be preconditioned to perform a packed min/max operation. A first selector can be coupled to a first invertor and a first input. A second selector can be coupled to a second invertor and a second input. An adder can be coupled to said first selector and said second selector. A third selector can be coupled to said adder, the first input, and the second input.

Abstract: A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

Abstract: The invention relates to a process for securely comparing two main storage registers, comprising defining an auxiliary storage register (A), calculating a first sum of the words composing the auxiliary storage register, comparing the words of the two main storage registers, randomly selecting one of the words of the auxiliary storage register, and modifying the value of the selected word by a first predetermined value if said words of the main storage registers are identical, and modifying the value of said selected word by a second predetermined value if said words of the main storage registers are different, calculating a second sum (SA2) of the words of the auxiliary storage register, and modifying the second sum by a value equal to said first value multiplied by the number of words (n) of the main storage registers, and comparing said first and second sums (SA1, SA2). The invention also relates to the associated security module.

Abstract: Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.

Abstract: A comparator for comparing binary numbers with N bits, where N>1, in which a plurality (200) of bit-to-bit comparators supplies a plurality of equality-difference signals, arranged in order of decreasing significance of the bits compared, to a matrix of transistors, arranged in 4 columns (201, 202, 203, 204) of N rows of transistors arranged in order, so as to control the gates of the transistors; the matrix, which receives, at the sources of the transistors of two (203, 204) of the columns, the signals representative of the bits of one of the numbers compared and their negated signals, is interconnected in a manner such as to identify the most significant difference by a simultaneous logic process, and to decide, on the basis of the bit signals received, which of the binary numbers is greater than, or greater than or equal to the other, presenting the outcome of the decision at an output (U2) within a very short time and with the use of much fewer active components than are required by conventional combin

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. Results of the subtraction operation are compared to zero in redundant form and without requiring carry propagation.

Abstract: The sum interval detector has two n-bit inputs, a 1-bit carry input, and a 1-bit output, which is activated when the sum of the input values lies within the interval −2p . . . 2p−1 or the like. The circuit utilizes a known method to detect whether a sum is equal to a constant to detect whether the upper n−p bits of the sum are binary 000 . . . 0, i.e. 0, or binary 111 . . . 1, i.e. −1, while the lower p bits of the sum are ignored corresponding to XXX . . . X. The method requires that the carry at position p be known which occurs with a well known, fast carry look-ahead circuit. By adding inverters and two levels of full adders the sum interval detector is capable of deciding whether two effective addresses, which each is a sum of base address plus offset, are so close, that the associated data areas overlap.

Abstract: A method and apparatus are provided for performing a fast sum-and-compare operation. The apparatus of the present invention utilizes a single carry save adder in conjunction with a zero detect circuit for performing logic operations to determine whether or not the sum of a plurality of operands is equal to one or more constants. The Carry Save Adder generates a sum, M, and carry, L, that are output from the carry save adder to the zero detect circuit. The zero detect circuit produces internal carry signals that are passed between adjacent bit-cells of the zero detect circuit. The zero detect circuit generates outputs Zk1 through Zkn which are true if the condition A+B+C={k1, k2, k3 . . . kn} for all constants k1 through kn. The carry signals propagate through only one bit of the zero detect circuit, thereby providing the sum-and-compare circuit of the present invention with extremely high speed.

Abstract: A method and apparatus are provided for forming a measure of difference between two data vectors, in particular for use in a trainable data classifier system. An association coefficient determined for the two vectors is used to form the measure of difference. A geometric difference between the two vectors may advantageously be combined with the association coefficient in forming the measure of difference. A particular application is the determination of conflicts between items of training data proposed for use in training a neural network to detect telecommunications account fraud or network intrusion.

Abstract: The present invention provides an efficient method for bypassing outputs while in redundant form to an arithmetic circuit that is capable of adding or subtracting numbers in redundant from and comparing the magnitudes of numbers received in redundant form for equality and inequality relationships. For one embodiment of the invention, an arithmetic circuit subtracts numbers received in redundant form and compares the result to zero represented in redundant form without carry propagation. In parallel with the subtraction and comparison, the most significant bits of each number received in redundant form are generated and compared for equality, and a carry-out is generated for the subtraction. These results are combined by magnitude comparison logic to produce a magnitude comparison for the numbers received in redundant form.

Abstract: An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module generates second detection bits from the first and second operands, where the second detection bits indicate a difference of one. A combiner combines the first and second detection bits to determine whether the difference of two numbers is less than two. The apparatus and method is used in determining to bypass normalization in floating point calculation.

Abstract: Methods and apparatus for comparing two binary numbers with a power-of-two threshold are provided in accordance with the present invention. In one embodiment, a method for comparing two binary numbers with a power-of-two threshold includes the steps of generating new relations, namely, much_greater_than (ggi) and equal_to (nqi), based at least in part on generate (gt) and propagate (eq) signals created for each bit of the binary numbers to be compared, and applying recursion in order to reduce the set of input signals at successive recursive nodes by a predetermined number. By omitting a pre-addition operation, the present invention eliminates the use of exclusive-OR logic gates, thus significantly reducing system cost and delay.

Abstract: Floating-point compare apparatus and methods are implemented. An adder generates a difference in moduli of first and second input operands. A sign bit of the second input operand provides a carry-in bit to an adder. In a first embodiment, the first and second input operands correspond to first and second source operands of the executing floating-point compare instruction. Comparison logic generates the compare result in response to a sign bit of the difference, sign bits of the first and second input operands, and a signal that is asserted if the operands are equal, and if the floating-point compare instruction being executed is A≧B, and negated otherwise. In a second embodiment, the first and second input operands are derived from the first and second source operands via switching logic that interchanges the operands in response to predecoded instruction information.

Abstract: The present invention relates to a digital comparator including a first block receiving on first inputs the bits of a first operand A of n bits and on second inputs the logic complements of the bits of a second operand B of n bits, generating a propagation signal p n = π i = 1 n ⁢ P i ⁢   ⁢ where ⁢   ⁢ P i = A i + B _ i , and a generation signal g

Abstract: For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.

Abstract: In accordance with the present invention, a logic circuit identifies the maximum or minimum boundary values from a group of values and also designates the input value(s) which match the boundary values. The logic circuit includes a number of slice logic blocks and a common logic block. Each slice logic block processes one of the input values to determine if it is a maximum value. The common logic block, shared by all the slice logic blocks generates the boundary value.

Abstract: A sum-and-compare circuit is provided which minimizes propagation delay and which minimizes the amount of die area required to implement the sum-and-compare circuit. The sum-and-compare circuit comprises a propagate/generate logic block followed by a carry-lookahead tree structure. The propagate/generate logic block receives a first operand, A, a second operand, B, and a third operand, J. The first operand A corresponds to an addend, the second operand B corresponds to an augend, and the third operand J corresponds to the twos compliment of the constant K. The propagate/generate logic block comprises logic configured to add the operand A to the operand B to obtain a first sum and logic configured to add the first sum to the operand J to obtain a plurality of propagate signals and a plurality of generate signals, which are then output from the propagate/generate logic block to a carry-lookahead tree structure.

Abstract: The present invention is a magnitude comparator that receives as inputs two 32-bit 1-of-4 operands. The magnitude comparator generates a carry indicator if the value of the first operand is less than or equal to the value of the second operand. The magnitude comparator generates a no carry indicator if the value of the first operand is greater than the value of the second operand.

Abstract: Burst-mode data transfers between a SCSI host bus adapter and at least one SCSI bus device interface adapter are implemented by hardware. For a first embodiment of the invention, the device interface adapter is equipped with a first, second and third data registers, a comparator, a subtractor, and control logic in the form of an application specific integrated circuit. When a burst-mode transfer is requested, the first register is programmed with a value corresponding to the length of the transfer in bytes, and the second register is programmed with the maximum possible number of bytes in a burst. The comparator then compares the value in stored in the first register with the value stored in the second register and determines which is the smaller. The smaller of the two values is written to the third register. The subtractor then subtracts said third value from said first value to obtain a remainder value. The first value is then replaced with a new first value equal to said remainder value.

Abstract: An apparatus and method for filtering and stabilizing a signal by using a window value is provided. The signal is sampled and each sample of the signal is input to the method or apparatus and compared to the previous output. If the difference between the input sample and the previous output is less than the window value, then the previous output is provided as the next output. However, if the difference between the reference sample and the input sample is greater than the window value, then the input sample is provided as the next output. Thus, the method and apparatus provide a constant output until the difference between the input sample and that output is greater than the window value, at which time the input sample is provided as the new output. In a preferred application, the invention can be used as a digital filter and can be embodied in the form of software, such as, for example, a C program.

Abstract: The present invention provides a digital data comparator having a first selective data inverting circuit inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive, a first adding circuit coupled to an output of the first selective data inverting circuit, adding one to the least significant bit when the sign of the first input data is negative, or outputting the first input data when the sign is positive, a second selective data inverting circuit inverting a second input data when the sign of the second input data is positive, or outputting the second input data when the sign is negative, and a second adding circuit adding an output of the first adding circuit and an output of the second selective data inverting circuit.

Abstract: The sum of a plurality of logarithmic numbers is determined by expressing the logarithmic numbers as one of a predetermined values. For example, the numbers may be analog values which may be sampled by an 8-bit AtoD converter to be expressed as one of a possible 256 values. The number of occurrences for each of the values is accumulated in bins (counters) and the sum is determined by a summation of the logarithmic numbers based on processing of the counts rather than the logarithmic numbers themselves. Bin counts are reduced iteratively by replacing counts greater than 1 by incrementing the count of a proportionately higher value bin until only counts of 1 or zero remain. These counts are then combined to provide only a single counter with a non-zero count value which indicates the accumulated signal strength of the signal strength measurements. The invention may further be provided using single bit memory elements and byte processing with look-up tables.

Abstract: In an arithmetic operation circuit, a coincidence detector receives the sign bits of binary data so as to output a truth coincidence detection signal when the two sign bits coincide with each other, and to output a false coincidence detection signal when they do not coincide with each other. A data inverter outputs a logic-inverted signal of each bit of the data when the coincidence detection result is truth, and outputs a signal equal to the data when the coincidence detection result is false. An adder receives the coincidence detection signal as a carry signal, and outputs the sum of the data and the output from the data inverter. A flag generator receives the sign bit of the data and the sign bit of the sum from the adder, and selectively outputs the sign bit or its inverted bit.