Abstract: A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.
Type:
Grant
Filed:
July 6, 2005
Date of Patent:
July 21, 2009
Assignee:
BAE Systems Information and Electronic Systems Integration Inc.
Abstract: A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the carry by comparing the input current and the threshold current in response to an input current and a sum signal generation unit for outputting a differential sum signal for the input current and the threshold current according to a comparison result of the carry generation unit.
Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.
Type:
Application
Filed:
March 26, 2002
Publication date:
October 2, 2003
Applicant:
Intel Corporation
Inventors:
David J. Comer, Aaron K. Martin, James E. Jaussi