Binary Patents (Class 708/700)

Patent number: 11301213Abstract: An integrated circuit with a large multiplier is provided. The multiplier may be configured to receive large input operands with thousands of bits. The multiplier may be implemented using a multiplier decomposition scheme that is recursively flattened into multiple decomposition levels to expose a tree of adders. The adders may be collapsed into a merged pipelined structure, where partial sums are forwarded from one level to the next while bypassing intervening prefix networks. The final correct sum is not calculated until later. In accordance with the decomposition technique, the partial sums are successively halved, which allows the prefix networks to be smaller from one level to the next. This allows all sums to be calculated at approximately the same pipeline depth, which significantly reduces latency with no or limited pipeline balancing.Type: GrantFiled: June 24, 2019Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Martin Langhammer, Bogdan Pasca

Patent number: 10824692Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a highpower mode of the adder circuit or a lowpower mode of the adder circuit using the determined relationship between the first and second inputs. The highpower mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.Type: GrantFiled: October 12, 2018Date of Patent: November 3, 2020Assignee: Google LLCInventors: Anand Suresh Kane, Ravi Narayanaswami

Patent number: 10620915Abstract: A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pullup network and a first pulldown network. There are at most two stacked transistors in at one or both of the first pullup network and the first pulldown network.Type: GrantFiled: August 24, 2018Date of Patent: April 14, 2020Assignee: MEDIATEK INC.Inventors: YingChun Wei, MinHang Hsieh, JenHang Yang

Patent number: 10503503Abstract: A method in a computeraided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a nonupdating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a nonupdating instruction.Type: GrantFiled: September 25, 2015Date of Patent: December 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi

Patent number: 10394524Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.Type: GrantFiled: February 14, 2018Date of Patent: August 27, 2019Assignee: ARM LimitedInventors: Christopher Neal Hinds, David Raymond Lutz

Patent number: 10340920Abstract: The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision may be restructured so that a set of subadders may perform the arithmetic on a respective segment of the operands. More specifically, the adder may be restructured so that a subadder of the set of subadders may concurrently output a generate signal and a propagate signal, which may both be routed to a prefix network. The prefix network may determine respective carry bit(s), which may carry into and/or select a sum at a subsequent subadder of the restructured adder. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., area and/or power) involved with implementing addition, which may improve operations such as encryption or machine learning on the integrated circuit.Type: GrantFiled: September 28, 2018Date of Patent: July 2, 2019Assignee: INTEL CORPORATIONInventors: Martin Langhammer, Tim Michael Vanderhoek, Jeffery Christopher Chromczak, Trevis Chandler

Patent number: 10001994Abstract: A vector scan operation is performed to generate M data elements of a result vector, where each result data element corresponds to a combination of an additional data element S with at least some of the data elements of a source vector operand V. The vector scan operation is performed using a plurality of steps, each step comprising one or more combination operations for combining data elements. At least one of the steps includes two or more combination operations performed in parallel. At least two of the steps comprise a combination operation for combining a data element with the additional data element S. This approach enables the vector scan operation to be performed in fewer steps in the case where fewer than M data elements are active, so that the vector scan operation can be performed more quickly.Type: GrantFiled: January 21, 2015Date of Patent: June 19, 2018Assignee: ARM LimitedInventors: Matthias Boettcher, Giacomo Gabrielli, Mbou EyoleMonono

Patent number: 9760375Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.Type: GrantFiled: September 9, 2014Date of Patent: September 12, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Markus Kaltenbach, David Lang, Jentje Leenstra

Patent number: 9740486Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.Type: GrantFiled: December 18, 2014Date of Patent: August 22, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Markus Kaltenbach, David Lang, Jentje Leenstra

Patent number: 9735761Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4LUT) configured to provide a 4LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.Type: GrantFiled: January 30, 2015Date of Patent: August 15, 2017Assignee: LATTICE SEMICONDUCTOR CORPORATIONInventors: Brad SharpeGeisler, Senani Gunaratna, Ting Yew

Patent number: 9658830Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises lookup table (LUT) logic having K inputs (a “KLUT”). The KLUT is configured to input the binary input signals at respective inputs of the KLUT logic cell and to provide, at a plurality of outputs of the KLUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the KLUT.Type: GrantFiled: June 30, 2014Date of Patent: May 23, 2017Assignee: Altera CorporationInventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim

Patent number: 9552328Abstract: A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an interprocessing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.Type: GrantFiled: April 27, 2012Date of Patent: January 24, 2017Assignee: SOCIONEXT INC.Inventors: Hayato Higuchi, Takashi Hanai

Patent number: 9448767Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a onebit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the onebit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.Type: GrantFiled: February 27, 2014Date of Patent: September 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca

Patent number: 9047081Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.Type: GrantFiled: March 15, 2013Date of Patent: June 2, 2015Assignee: Intel CorporationInventor: Gopalan Ramanujam

Patent number: 8959134Abstract: Disclosed is a method of modular multiplication of two Lbit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being kbit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first subloop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into pbit digits. Starting each subloop iteration, the p bits of the current digit of mi are simultaneously produced. A second subloop calculates and sums the remaining partial results of XYi+miM+R using mi from the first subloop.Type: GrantFiled: April 11, 2012Date of Patent: February 17, 2015Assignee: Inside SecureInventor: Michael Niel

Publication number: 20140214913Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: HyeongSeok YU, SukJin KIM

Patent number: 8788563Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.Type: GrantFiled: April 2, 2009Date of Patent: July 22, 2014Assignee: SARL Daniel TornoInventor: Daniel Torno

Patent number: 8713086Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a onebit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the onebit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.Type: GrantFiled: July 8, 2011Date of Patent: April 29, 2014Assignee: Texas Instruments IncorporatedInventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca

Patent number: 8706795Abstract: Methods, apparatuses, and articles associated with SIMD adding two integers are disclosed. In embodiments, a method may include elementwise SIMD adding corresponding elements of a first SIMDsized integer (A) and a second SIMDsized integer (B) to generate a SIMDsized integer result (R) and a carry bit. A may have an integer size (SizeA), while B may have an integer size (SizeB). The addition, in response to SizeA greater than SizeB, may further include updating R and the carry bit in view of one or more elements of A that do not have corresponding element or elements of B. Further, elementwise SIMD adding may include performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks.Type: GrantFiled: March 30, 2011Date of Patent: April 22, 2014Assignee: Intel CorporationInventor: Sergey Lyalin

Patent number: 8667046Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multioperand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).Type: GrantFiled: February 20, 2009Date of Patent: March 4, 2014Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations IndustriellesInventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi ParandehAfshar

Patent number: 8650232Abstract: A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.Type: GrantFiled: October 26, 2009Date of Patent: February 11, 2014Assignee: VIA Technologies, Inc.Inventors: Rochelle L. Stortz, Raymond A. Bertram

Patent number: 8606842Abstract: Provided are Ndigit addition and subtraction units and Ndigit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.Type: GrantFiled: August 21, 2008Date of Patent: December 10, 2013Assignee: Tokyo Denki UniversityInventors: Hiroshi Kasahara, Tsugio Nakamura, Jin Sato

Publication number: 20130311534Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (41) adder. In some examples, only an XOR gate, an AND gate, two single bit 21 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (31) adder are needed to support 41 adders. Binary (21) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.Type: ApplicationFiled: April 18, 2013Publication date: November 21, 2013Applicant: Altera CorporationInventor: Altera Corporation

Patent number: 8572154Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.Type: GrantFiled: September 27, 2010Date of Patent: October 29, 2013Assignee: Texas Instruments IncorporatedInventors: Duc Q. Bui, Timothy D. Anderson

Patent number: 8516030Abstract: A carry lookahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry lookahead circuit includes a circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output.Type: GrantFiled: March 27, 2009Date of Patent: August 20, 2013Assignee: Fujitsu LimitedInventor: Moriyuki Santou

Patent number: 8407277Abstract: A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first bit and an inverter output to receive the complemented second bit; and an OR gate having first and second inputs coupled to a first AND gate output and a second AND gate output. An XOR gate output and an OR gate output generate the sum output bit and the carry output bit.Type: GrantFiled: October 26, 2008Date of Patent: March 26, 2013Assignee: Cadence Design Systems, Inc.Inventor: Sabyasachi Das

Patent number: 8370409Abstract: A method for operand width reduction is described, wherein two Nbit input operands (A, B) of a bit width of N are processed and two Mbit output operands (A?, B?) of a reduced bit width of M are generated in a way, that a postprocessing comprising an Mbit adder function followed by saturation to M bits performed on said two Mbit output operands (A?, B?) provides an Mbit result equal to an Mbit result of an Nbit modulo adder function of the two Nbit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.Type: GrantFiled: February 11, 2008Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Nicolas Maeding, Jochen Preiss

Publication number: 20120311009Abstract: A hybrid adder may include static partial sum circuits that operate to generate partial sums of operands, where each operand may be divided into groups that include multiple bits. A first subset of the static partial sum circuits may generate a partial sum of a corresponding group of the two or more operands assuming a carry in of 0 to the corresponding group, and a second subset may similarly assume a carry in of 1 to the corresponding group. The adder may further include a dynamic carry tree circuit that generates arithmetic carry signals, where each of the arithmetic carry signals corresponds to a respective group of sum bits. The adder may further include a multiplexer that, during operation, selects each of the groups of sum bits from either of the first or the second subsets of static partial sum circuits dependent upon corresponding ones of the arithmetic carry signals.Type: ApplicationFiled: May 2, 2012Publication date: December 6, 2012Inventors: Ben D. Jarrett, Justin J. Friesenhahn, Jon A. Loschke

Publication number: 20120265797Abstract: Disclosed is a method of modular multiplication of two Lbit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being kbit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first subloop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into pbit digits. Starting each subloop iteration, the p bits of the current digit of mi are simultaneously produced. A second subloop calculates and sums the remaining partial results of XYi+miM+R using mi from the first subloop.Type: ApplicationFiled: April 11, 2012Publication date: October 18, 2012Applicant: INSIDE SECUREInventor: Michael NIEL

Patent number: 8234319Abstract: A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first fourtotwo compressor, performing a first fourtotwo compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second fourtotwo compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.Type: GrantFiled: May 25, 2005Date of Patent: July 31, 2012Assignee: QUALCOMM IncorporatedInventors: Shankar Krithivasan, Christopher Edward Koob

Patent number: 8224883Abstract: A packed halfword addition and subtraction operation is performed by a microprocessor in parallel upon halfword operands obtained from designated top or bottom halfword locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom halfword locations of a designated destination register. The microprocessor includes an arithmeticlogic unit (ALU) with adder circuitry that can be selectively split into separate halfword adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected halfword operands. The halfword adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom halfword locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.Type: GrantFiled: June 29, 2009Date of Patent: July 17, 2012Assignee: Atmel CorporationInventors: Ronny Pedersen, Erik K. Renno, Oyvind Strom

Publication number: 20120134325Abstract: A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values.Type: ApplicationFiled: June 9, 2011Publication date: May 31, 2012Inventors: Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Andrey P. Sokolov, Yurii S. Shutkin

Publication number: 20120124120Abstract: According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first input sections, a first wave transmission medium having a continuous film including a magnetic body connected to the first input sections, and a first wave detector outputting a result of computation by spin waves induced in the first wave transmission medium by the signals corresponding to the two bit values. The threshold wave computing unit includes a plurality of third input sections, a third wave transmission medium having a continuous film including a magnetic body connected to the third input sections, and a third wave detector a result of computation by spin waves induced in the third wave transmission medium.Type: ApplicationFiled: January 13, 2012Publication date: May 17, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hirofumi Morise, Shiho Nakamura, Daisuke Saida, Tsuyoshi Kondo

Patent number: 8135767Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carryin input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carryin input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carryin input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carryin input.Type: GrantFiled: August 8, 2007Date of Patent: March 13, 2012Inventor: Thomas Kuenemund

Publication number: 20120047194Abstract: According to certain embodiments, a first characteristic function representing a first set of samples and a second characteristic function representing a second set of samples are generated. The first characteristic function and the second characteristic function are transformed to a first arithmetic function and a second arithmetic function, respectively. A first hash code and a second hash code are calculated from the first arithmetic function and the second arithmetic function, respectively. If the first hash code equals the second hash code, the first set of samples and the second set of samples are designated as equivalent; otherwise, the first set of samples and the second set of samples are designated as not equivalent.Type: ApplicationFiled: August 17, 2010Publication date: February 23, 2012Applicant: Fujitsu LimitedInventors: Stergios Stergiou, Jawahar Jain

Publication number: 20120036172Abstract: An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.Type: ApplicationFiled: August 9, 2010Publication date: February 9, 2012Applicant: International Business Machines CorporationInventor: Deepak K. Singh

Patent number: 8058903Abstract: An apparatus for providing a combined digital signal comprises a bit adder and a combiner. The combined digital signal contains information of a first digital input signal and a second digital input signal, wherein a block length of the first digital input signal is shorter than a block length of the second digital input signal. The bit adder is configured to add at least one filling bit to a block of the first digital input signal to obtain an adapted first digital input signal, so that the block length of the adapted first digital input signal is equal to a block length of the second digital input signal. The combiner is configured to combine the adapted first digital input signal and the second digital input signal to obtain and provide the combined digital signal.Type: GrantFiled: February 5, 2010Date of Patent: November 15, 2011Assignee: NTT DoCoMo, Inc.Inventors: Jian Zhao, Marc Kuhn, Armin Wittneben, Gerhard Bauch

Patent number: 7991820Abstract: The ONE STEP BINARY SUMMARIZER is a digital logic circuit. It is used for summarizing two binary numbers. It contains one Function Generator Module and one or more SUMMARIZER Units. For subtraction it is subtracting Register “A” from Register “B” and Register “B” from Register “A”. The two subtraction and one addition operations are executed simultaneously. The Function Generator Module determines the actual correct operation, (addition or subtraction) and selects the correct results for the resultant operand. The circuit utilizes the subtractionbycarry method; therefore the subtraction operation does not require any presorting, complementary operations, iterative additions, temporary storage, and multiple instruction sets, etc. The logicflow is similar, the operational speed is identical for the addition and subtraction operations; and therefore, it is a true Time Symmetrical circuit. It is independent from the initial operation selection, the signs and magnitudes of the input operands.Type: GrantFiled: August 7, 2007Date of Patent: August 2, 2011Inventor: Leslie Imre Sohay

Publication number: 20110153709Abstract: A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUTbased FPGAs. Given a targeted Kinput LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a postprocessing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8input LUTbased FPGA architecture.Type: ApplicationFiled: March 4, 2010Publication date: June 23, 2011Inventors: JuinnDar HUANG, JhihHong Lu, BuChing Lin, JingYang Jou

Patent number: 7962538Abstract: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider reusage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two Nbit operands as an input, adding the (N?M+1) most significant bits of said two Nbit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reducedbitlength output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined postprocessing can be correctly performed with said output operands.Type: GrantFiled: November 15, 2006Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jens Leenstra, Nicolas Maeding, Kerstin Schelm

Publication number: 20110106869Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.Type: ApplicationFiled: April 2, 2009Publication date: May 5, 2011Applicant: SARL DANIEL TORNOInventor: Daniel Torno

Publication number: 20100312945Abstract: An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.Type: ApplicationFiled: July 7, 2010Publication date: December 9, 2010Inventor: Maurice L. Hutson

Patent number: 7844654Abstract: An arithmetic unit of arbitraryprecision, including: a main processing unit, which splits up the first and the second arbitraryprecision values into Nbit (where N is a natural number) operands respectively in theleastsignificantbitfirst order for computing with the arbitraryprecision data and consecutively outputting a series of pairs of the first and second Nbit operands; and an Nbit arithmetic unit, which performs computing with the Nbit operands, while requesting the main processing unit to feed the next Nbit operands each time the computation completes. The carry bit generated by the operation is fed to the next Nbit operation.Type: GrantFiled: August 30, 2005Date of Patent: November 30, 2010Assignee: Seiko Epson CorporationInventor: Nobuo Karaki

Publication number: 20100262639Abstract: A digital data processor which receives an Nbit input signal from a data source and converts the Nbit input signal into an Mbit output signal, the Mbit being larger than the Nbit. The digital data processor includes: an weighted addition circuit which is operable to perform weighted addition on at least the input signal and a signal being timeshifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit which is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit which is operable to attach a predetermined bits to an LSD side of the input signal to generate an intermediate signal of M bits; and an addition circuit which is operable to perform addition of the intermediate signal and the processed input signal so as to generate the Mbit output signal.Type: ApplicationFiled: April 12, 2010Publication date: October 14, 2010Inventors: Ryoji SUZUKI, Yusuke Mori

Publication number: 20100198895Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced lookup table.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Inventors: Kameran Azadet, JianGuo Chen, Samer Hijazi, Joseph Williams

Publication number: 20100164543Abstract: In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.Type: ApplicationFiled: December 21, 2009Publication date: July 1, 2010Inventor: Daniel R. Shepard

Patent number: 7743084Abstract: A multioperand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multioperand decimal adder uses binary carrysave adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multioperand decimal adder may perform speculative or nonspeculative binary carrysave addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.Type: GrantFiled: December 16, 2004Date of Patent: June 22, 2010Assignee: Wisconsin Alumni Research FoundationInventors: Michael J. Schulte, Robert D. Kenney

Publication number: 20100146031Abstract: The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carrypropagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark Alan Erle, Brian John Hickmann

Patent number: 7716270Abstract: A carryripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.Type: GrantFiled: March 13, 2006Date of Patent: May 11, 2010Assignee: Infineon Technologies AGInventors: Joel Hatsch, Winfried Kamp

Patent number: 7685215Abstract: In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multibit adder, using lookup table (LUT) circuits as their building blocks. Efficient generation of carryout signals and fastcarry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate areainefficient lookahead carry logic without a significant delay in signal generation.Type: GrantFiled: October 24, 2005Date of Patent: March 23, 2010Assignee: Lattice Semiconductor CorporationInventors: Brian Gaide, Xiaojie He