Binary Patents (Class 708/700)
  • Patent number: 11301213
    Abstract: An integrated circuit with a large multiplier is provided. The multiplier may be configured to receive large input operands with thousands of bits. The multiplier may be implemented using a multiplier decomposition scheme that is recursively flattened into multiple decomposition levels to expose a tree of adders. The adders may be collapsed into a merged pipelined structure, where partial sums are forwarded from one level to the next while bypassing intervening prefix networks. The final correct sum is not calculated until later. In accordance with the decomposition technique, the partial sums are successively halved, which allows the prefix networks to be smaller from one level to the next. This allows all sums to be calculated at approximately the same pipeline depth, which significantly reduces latency with no or limited pipeline balancing.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Bogdan Pasca
  • Patent number: 10824692
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 3, 2020
    Assignee: Google LLC
    Inventors: Anand Suresh Kane, Ravi Narayanaswami
  • Patent number: 10620915
    Abstract: A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 14, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ying-Chun Wei, Min-Hang Hsieh, Jen-Hang Yang
  • Patent number: 10503503
    Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises generating a functional representation of logic to determine whether an instruction is an updating instruction or a non-updating instruction. The method further comprises generating a functional representation of a first arithmetic logic unit (ALU) coupled to a general register in the processor, the first ALU to execute the instruction if the instruction is an updating instruction and store an update value in the general register, and generating a functional representation of a second ALU in the processor to execute the instruction if the instruction is a non-updating instruction.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
  • Patent number: 10394524
    Abstract: Apparatus and corresponding methods are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 27, 2019
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 10340920
    Abstract: The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision may be restructured so that a set of sub-adders may perform the arithmetic on a respective segment of the operands. More specifically, the adder may be restructured so that a sub-adder of the set of sub-adders may concurrently output a generate signal and a propagate signal, which may both be routed to a prefix network. The prefix network may determine respective carry bit(s), which may carry into and/or select a sum at a subsequent sub-adder of the restructured adder. As a result, the integrated circuit may benefit from increased efficiencies, reduced latency, and reduced resource consumption (e.g., area and/or power) involved with implementing addition, which may improve operations such as encryption or machine learning on the integrated circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 2, 2019
    Assignee: INTEL CORPORATION
    Inventors: Martin Langhammer, Tim Michael Vanderhoek, Jeffery Christopher Chromczak, Trevis Chandler
  • Patent number: 10001994
    Abstract: A vector scan operation is performed to generate M data elements of a result vector, where each result data element corresponds to a combination of an additional data element S with at least some of the data elements of a source vector operand V. The vector scan operation is performed using a plurality of steps, each step comprising one or more combination operations for combining data elements. At least one of the steps includes two or more combination operations performed in parallel. At least two of the steps comprise a combination operation for combining a data element with the additional data element S. This approach enables the vector scan operation to be performed in fewer steps in the case where fewer than M data elements are active, so that the vector scan operation can be performed more quickly.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: June 19, 2018
    Assignee: ARM Limited
    Inventors: Matthias Boettcher, Giacomo Gabrielli, Mbou Eyole-Monono
  • Patent number: 9760375
    Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Markus Kaltenbach, David Lang, Jentje Leenstra
  • Patent number: 9740486
    Abstract: A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its respective register file, and together configured to perform operations specified in a second set of instructions on data stored across both register files. During utilization, the processor receives a first instruction of the first set specifying an operation, a target register, and a source register. Next, a second instruction upon which content of the source register depends is identified as being of the second set. In response, the first instruction is dispatched to the even slice. In accordance with the operation specified in the first instruction, the even slice uses content of the source register in its register file to produce a result. Copies of the result are written to the target register in both register files.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Markus Kaltenbach, David Lang, Jentje Leenstra
  • Patent number: 9735761
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 15, 2017
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 9658830
    Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan, Henry Kim
  • Patent number: 9552328
    Abstract: A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performs computing processing on the input data signal held in the input data holding register.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 24, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Hayato Higuchi, Takashi Hanai
  • Patent number: 9448767
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 20, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • Patent number: 9047081
    Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventor: Gopalan Ramanujam
  • Patent number: 8959134
    Abstract: Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being k-bit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first sub-loop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into p-bit digits. Starting each sub-loop iteration, the p bits of the current digit of mi are simultaneously produced. A second sub-loop calculates and sums the remaining partial results of XYi+miM+R using mi from the first sub-loop.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 17, 2015
    Assignee: Inside Secure
    Inventor: Michael Niel
  • Publication number: 20140214913
    Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Seok YU, Suk-Jin KIM
  • Patent number: 8788563
    Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: July 22, 2014
    Assignee: SARL Daniel Torno
    Inventor: Daniel Torno
  • Patent number: 8713086
    Abstract: A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B?2k.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Mujibur Rahman, Kai Chirca
  • Patent number: 8706795
    Abstract: Methods, apparatuses, and articles associated with SIMD adding two integers are disclosed. In embodiments, a method may include element-wise SIMD adding corresponding elements of a first SIMD-sized integer (A) and a second SIMD-sized integer (B) to generate a SIMD-sized integer result (R) and a carry bit. A may have an integer size (SizeA), while B may have an integer size (SizeB). The addition, in response to SizeA greater than SizeB, may further include updating R and the carry bit in view of one or more elements of A that do not have corresponding element or elements of B. Further, element-wise SIMD adding may include performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventor: Sergey Lyalin
  • Patent number: 8667046
    Abstract: A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice).
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: March 4, 2014
    Assignee: Ecole Polytechnique Federale de Lausanne/Service des Relations Industrielles
    Inventors: Philip Brisk, Alessandro Cevrero, Frank K. Gurkaynak, Paolo Ienne Lopez, Hadi Parandeh-Afshar
  • Patent number: 8650232
    Abstract: A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: February 11, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rochelle L. Stortz, Raymond A. Bertram
  • Patent number: 8606842
    Abstract: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: December 10, 2013
    Assignee: Tokyo Denki University
    Inventors: Hiroshi Kasahara, Tsugio Nakamura, Jin Sato
  • Publication number: 20130311534
    Abstract: A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
    Type: Application
    Filed: April 18, 2013
    Publication date: November 21, 2013
    Applicant: Altera Corporation
    Inventor: Altera Corporation
  • Patent number: 8572154
    Abstract: A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A?B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: October 29, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Duc Q. Bui, Timothy D. Anderson
  • Patent number: 8516030
    Abstract: A carry look-ahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry look-ahead circuit includes a circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 20, 2013
    Assignee: Fujitsu Limited
    Inventor: Moriyuki Santou
  • Patent number: 8407277
    Abstract: A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first bit and an inverter output to receive the complemented second bit; and an OR gate having first and second inputs coupled to a first AND gate output and a second AND gate output. An XOR gate output and an OR gate output generate the sum output bit and the carry output bit.
    Type: Grant
    Filed: October 26, 2008
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sabyasachi Das
  • Patent number: 8370409
    Abstract: A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A?, B?) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A?, B?) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tobias Gemmeke, Nicolas Maeding, Jochen Preiss
  • Publication number: 20120311009
    Abstract: A hybrid adder may include static partial sum circuits that operate to generate partial sums of operands, where each operand may be divided into groups that include multiple bits. A first subset of the static partial sum circuits may generate a partial sum of a corresponding group of the two or more operands assuming a carry in of 0 to the corresponding group, and a second subset may similarly assume a carry in of 1 to the corresponding group. The adder may further include a dynamic carry tree circuit that generates arithmetic carry signals, where each of the arithmetic carry signals corresponds to a respective group of sum bits. The adder may further include a multiplexer that, during operation, selects each of the groups of sum bits from either of the first or the second subsets of static partial sum circuits dependent upon corresponding ones of the arithmetic carry signals.
    Type: Application
    Filed: May 2, 2012
    Publication date: December 6, 2012
    Inventors: Ben D. Jarrett, Justin J. Friesenhahn, Jon A. Loschke
  • Publication number: 20120265797
    Abstract: Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2L. L/k iterations are performed, an iteration i involving XYi+miM+R, Yi, mi being k-bit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first sub-loop of k/p iterations calculates a partial result of XYi+miM+R on k least significant bits of X, M, R, following decomposition of X, mi into p-bit digits. Starting each sub-loop iteration, the p bits of the current digit of mi are simultaneously produced. A second sub-loop calculates and sums the remaining partial results of XYi+miM+R using mi from the first sub-loop.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 18, 2012
    Applicant: INSIDE SECURE
    Inventor: Michael NIEL
  • Patent number: 8234319
    Abstract: A method of completing a two's complement operation includes receiving a plurality of byte values and splitting the plurality of byte values into a first portion and a second portion. Further, the method includes inputting the first portion to a first segment of a first four-to-two compressor, performing a first four-to-two compression operation on the first portion to generate a first set of results having a first row and a second row that is offset one bit from the first row, and carrying in a first value of one to complete a first two's complement operation. The method also includes inputting the second portion to a second segment of a second four-to-two compressor and adding two values of one immediately to the right of the second portion in order to carry in a second value of one to the second portion to complete a second two's complement operation.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 31, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Shankar Krithivasan, Christopher Edward Koob
  • Patent number: 8224883
    Abstract: A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: July 17, 2012
    Assignee: Atmel Corporation
    Inventors: Ronny Pedersen, Erik K. Renno, Oyvind Strom
  • Publication number: 20120134325
    Abstract: A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by adding a plurality of first values related to a plurality of information bits, a plurality of second values related to the information bits and a plurality of third values related to a plurality of parity bits. Step (B) may generate a plurality of permutated values by permutating the sum values based on a configuration signal. The configuration signal generally identifies a current one of the communications standards. Step (C) may generate a plurality of branch metrics values by adding pairs of the permutated values.
    Type: Application
    Filed: June 9, 2011
    Publication date: May 31, 2012
    Inventors: Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Andrey P. Sokolov, Yurii S. Shutkin
  • Publication number: 20120124120
    Abstract: According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first input sections, a first wave transmission medium having a continuous film including a magnetic body connected to the first input sections, and a first wave detector outputting a result of computation by spin waves induced in the first wave transmission medium by the signals corresponding to the two bit values. The threshold wave computing unit includes a plurality of third input sections, a third wave transmission medium having a continuous film including a magnetic body connected to the third input sections, and a third wave detector a result of computation by spin waves induced in the third wave transmission medium.
    Type: Application
    Filed: January 13, 2012
    Publication date: May 17, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirofumi Morise, Shiho Nakamura, Daisuke Saida, Tsuyoshi Kondo
  • Patent number: 8135767
    Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: March 13, 2012
    Inventor: Thomas Kuenemund
  • Publication number: 20120047194
    Abstract: According to certain embodiments, a first characteristic function representing a first set of samples and a second characteristic function representing a second set of samples are generated. The first characteristic function and the second characteristic function are transformed to a first arithmetic function and a second arithmetic function, respectively. A first hash code and a second hash code are calculated from the first arithmetic function and the second arithmetic function, respectively. If the first hash code equals the second hash code, the first set of samples and the second set of samples are designated as equivalent; otherwise, the first set of samples and the second set of samples are designated as not equivalent.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 23, 2012
    Applicant: Fujitsu Limited
    Inventors: Stergios Stergiou, Jawahar Jain
  • Publication number: 20120036172
    Abstract: An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: International Business Machines Corporation
    Inventor: Deepak K. Singh
  • Patent number: 8058903
    Abstract: An apparatus for providing a combined digital signal comprises a bit adder and a combiner. The combined digital signal contains information of a first digital input signal and a second digital input signal, wherein a block length of the first digital input signal is shorter than a block length of the second digital input signal. The bit adder is configured to add at least one filling bit to a block of the first digital input signal to obtain an adapted first digital input signal, so that the block length of the adapted first digital input signal is equal to a block length of the second digital input signal. The combiner is configured to combine the adapted first digital input signal and the second digital input signal to obtain and provide the combined digital signal.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: November 15, 2011
    Assignee: NTT DoCoMo, Inc.
    Inventors: Jian Zhao, Marc Kuhn, Armin Wittneben, Gerhard Bauch
  • Patent number: 7991820
    Abstract: The ONE STEP BINARY SUMMARIZER is a digital logic circuit. It is used for summarizing two binary numbers. It contains one Function Generator Module and one or more SUMMARIZER Units. For subtraction it is subtracting Register “A” from Register “B” and Register “B” from Register “A”. The two subtraction and one addition operations are executed simultaneously. The Function Generator Module determines the actual correct operation, (addition or subtraction) and selects the correct results for the resultant operand. The circuit utilizes the subtraction-by-carry method; therefore the subtraction operation does not require any presorting, complementary operations, iterative additions, temporary storage, and multiple instruction sets, etc. The logic-flow is similar, the operational speed is identical for the addition and subtraction operations; and therefore, it is a true Time Symmetrical circuit. It is independent from the initial operation selection, the signs and magnitudes of the input operands.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: August 2, 2011
    Inventor: Leslie Imre Sohay
  • Publication number: 20110153709
    Abstract: A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 23, 2011
    Inventors: Juinn-Dar HUANG, Jhih-Hong Lu, Bu-Ching Lin, Jing-Yang Jou
  • Patent number: 7962538
    Abstract: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N?M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Tobias Gemmeke, Jens Leenstra, Nicolas Maeding, Kerstin Schelm
  • Publication number: 20110106869
    Abstract: A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits and a correction signal Ri+1 on N bits, on the basis of a binary input number c, an estimation signal Ui and a correction signal Ri on N bits emanating from a previous iteration i. The estimation signal Ui and the correction signal Ri represent a sum of a least two binary numbers in redundant form. The estimation signal Ui+1 and the correction signal Ri+1 represent, in redundant form, the sum of the at least two binary numbers in redundant form and the binary number c. In other words, such a method makes it possible to sum a further binary number with a result represented in a redundant binary form of the type “U/R”, this result resulting from an initialization or a previous summation, and then to generate a result also in a redundant binary form of the type “U/R”.
    Type: Application
    Filed: April 2, 2009
    Publication date: May 5, 2011
    Applicant: SARL DANIEL TORNO
    Inventor: Daniel Torno
  • Publication number: 20100312945
    Abstract: An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector. Addressing logic (90) associates a memory cell select (C) to each initial and subsequent address of each of the plurality of vectors. Cell select apparatus (98) accesses a memory cell (in 92) using a memory cell select (C) associated to a respective one of the initial and successive addresses of each vector.
    Type: Application
    Filed: July 7, 2010
    Publication date: December 9, 2010
    Inventor: Maurice L. Hutson
  • Patent number: 7844654
    Abstract: An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing with the arbitrary-precision data and consecutively outputting a series of pairs of the first and second N-bit operands; and an N-bit arithmetic unit, which performs computing with the N-bit operands, while requesting the main processing unit to feed the next N-bit operands each time the computation completes. The carry bit generated by the operation is fed to the next N-bit operation.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuo Karaki
  • Publication number: 20100262639
    Abstract: A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital data processor includes: an weighted addition circuit which is operable to perform weighted addition on at least the input signal and a signal being time-shifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit which is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit which is operable to attach a predetermined bits to an LSD side of the input signal to generate an intermediate signal of M bits; and an addition circuit which is operable to perform addition of the intermediate signal and the processed input signal so as to generate the M-bit output signal.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 14, 2010
    Inventors: Ryoji SUZUKI, Yusuke Mori
  • Publication number: 20100198895
    Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Publication number: 20100164543
    Abstract: In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.
    Type: Application
    Filed: December 21, 2009
    Publication date: July 1, 2010
    Inventor: Daniel R. Shepard
  • Patent number: 7743084
    Abstract: A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 22, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Michael J. Schulte, Robert D. Kenney
  • Publication number: 20100146031
    Abstract: The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Alan Erle, Brian John Hickmann
  • Patent number: 7716270
    Abstract: A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2w.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: May 11, 2010
    Assignee: Infineon Technologies AG
    Inventors: Joel Hatsch, Winfried Kamp
  • Patent number: 7685215
    Abstract: In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multi-bit adder, using look-up table (LUT) circuits as their building blocks. Efficient generation of carry-out signals and fast-carry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate area-inefficient look-ahead carry logic without a significant delay in signal generation.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: March 23, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brian Gaide, Xiaojie He