Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.

Abstract: An arithmetic circuit includes an arithmetic driving circuit and a detection circuit. The arithmetic driving circuit is configured to generate an arithmetic result value based on first and second arithmetic target values. The detection circuit is configured to detect whether an upper borrow digit value occurs, by receiving the arithmetic result value as feedback.

Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal.

Abstract: Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced.

Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

Abstract: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.

Abstract: A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.

Abstract: A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.

Abstract: A single stage computation method to perform a discrete cosine transform operation is provided. The discrete cosine transform operation is performed by executing a plurality of very large instruction words (VLIW) using a digital signal processor. The plurality of very large instruction words includes a first number of multiplications and a second number of additions, where the first number of multiplications is greater than the second number of additions.

Abstract: An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.

Abstract: One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more rounds of a block cipher algorithm. A plurality of N bit registers are respectively coupled to the plurality of digital logic components. An XOR component receives blocks of plaintext data and blocks of ciphertext data, and XORs blocks of plaintext data for respective plaintext packets with previously encrypted blocks of ciphertext data for those plaintext packets. The XOR component iteratively feeds the XOR'd blocks of data into a first of the plurality of the digital logic components. In addition, a circuit component is operative to selectively pass blocks of ciphertext data fed back from an output of a final logic component to the XOR component.

Abstract: A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength for the true output is the same as the output drive strength for the compliment output. In another embodiment, the symmetric differential domino carry generate gate has a first evaluation block of transistors and a second evaluation block of transistors, and the second evaluation block has the same number of transistors connected in a parallel relationship as the first evaluation block and the same number of transistors connected in a serial relationship as the first evaluation block.

Abstract: An ultrawideband radio frequency pulse is generated by shaping a carrier signal having a selected frequency with a window function. The shaped carrier is gated to produce the ultrawideband pulse. In further embodiments, the window function comprises a sinusoidal function, and the ultrawideband pulse is formed via a mixer and a CMOS radio frequency switch.

Abstract: A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is configured so that the transistors will each operate at a voltage below its threshold voltage. The circuit element includes a plurality of circuit sub-elements each having an output. The circuit sub-element outputs are connected together.

Abstract: A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.

Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the carry by comparing the input current and the threshold current in response to an input current and a sum signal generation unit for outputting a differential sum signal for the input current and the threshold current according to a comparison result of the carry generation unit.

Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.

Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.

Abstract: An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Abstract: A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*). A first stage has differential pairs (P1, P2, P3) receiving bits (A, B, C), respectively, and complements (A*, B*, C*), respectively. The pairs have common output arms and are powered by an identical current (I). First and second output arms include resistors (R1, R2, R3) and (R4, R5, R6), respectively, connected-in-series to a reference potential (M). The resistors define intermediate nodes (A1, A2, A3) in the first arm, (B1, B2, B3) in the second arm. Carry outputs are taken at nodes (A2, B2). A second stage has differential pairs (P4, P5, P6) whose inputs are connected to nodes (A1, B3) for pair (P4), (A2, B2) for pair (P5), and (A3, B1) for pair (P6). Pairs (P4, P6) each have a common arm with the pair (P5) and a non-common arm.

Abstract: A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength for the true output is the same as the output drive strength for the compliment output. In another embodiment, the symmetric differential domino carry generate gate has a first evaluation block of transistors and a second evaluation block of transistors, and the second evaluation block has the same number of transistors connected in a parallel relationship as the first evaluation block and the same number of transistors connected in a serial relationship as the first evaluation block.

Abstract: Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations.

Abstract: An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is one at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry— signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry— signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Abstract: In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2·g1+p2·p1·g0 /g0=/p2+/g2·/p1+/g2·/g1·/g0 In other words, the block carry generation logic /G0 is produced by a single PMOS transistor, a series circuit formed of two PMOS transistors connected in series, and a series circuit formed of three PMOS transistors connected in series. The block carry generation logic G0 is produced by a single NMOS transistor, a series circuit formed of two NMOS transistors connected in series, and a series circuit formed of three NMOS transistors connected in series. Block carry generation logics can be formed in such a way as to achieve not only a reduction of the layout area but also a higher operation rate.

Abstract: A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY—2 output, and the third data output is a CARRY—4 output.

Abstract: A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two binary inputs adapted to receive corresponding input binary digits, the circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and at least one of the input binary digits and (2) a switch, coupled to the power down circuit, that interrupts DC current to at least a portion of the logic gate as a function of the power down signal.

Abstract: An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.

Abstract: A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first presumed carry-in signal and a second candidate carry-out signal is based on a second presumed carry-in signal different than the first presumed carry-in signal. A two-level selector for simultaneously selects, for each of the pairs of candidate carry-out signals, either the first candidate carry-out signal or the second candidate carry-out signal as an actual carry-out signal, based on an actual carry-in signal. Both selected carry out signals are passed to.

Abstract: In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.

Abstract: A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. The carry generator receives an exclusive-OR value P(i, i=1,2,3,4) and a logic product value G(i) of two data, and an initial carry value C(1), and performs a function of G(4)+P(4).multidot.G(3)+P(4).multidot.P(3).multidot.G(2)+P(4).multidot.P(3 ).multidot.P(2).multidot.G(1)+P(4).multidot.P(3).multidot.P(2).multidot.P(1 ).multidot.C(1) to output a final carry value C(5). The carry generator includes a first NMOS transistor for executing an operation of P(4).multidot.G(3), second and third NMOS transistors for executing an operation of P(4).multidot.P(3).multidot.G(2), fourth to sixth NMOS transistors for executing an operation of P(4).multidot.P(3).multidot.P(2).multidot.G(1), seventh to eleventh NMOS transistors for executing an operation of P(4).multidot.