Abstract: Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n?1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Abstract: An ASK modulator for reducing the difference in the On/Off ratio due to the difference in the envelope frequency components without deteriorating an adjacent wave leakage power is disclosed. The ASK modulator includes a Manchester encoder that generates Manchester-encoded signals by applying Manchester encoding to an input signal sequence, a waveform shaping unit that generates band-limited encoded signals from the Manchester-encoded signals, and detects and limits minimum values of waveforms of the band-limited encoded signals to generates shaped signals, and a modulating unit that modulates carrier waves based on the shaped signals.

Abstract: An asynchronous adder permits asynchronous design in which dual-rail encoding is employed, not only for a control part but also for a datapath part including an ALU. An asynchronous adder of an exemplary embodiment includes a combinational circuit to perform full addition with, as an input value, an addend X, an augend Y and a carry-in Cin that are dual-rail encoded, and to output a sum output Z and a carry output Cout that are dual-rail encoded as an output value.

Abstract: A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first and second three-to-two reducer both include a symmetric carry generate gate.

Abstract: A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength for the true output is the same as the output drive strength for the compliment output. In another embodiment, the symmetric differential domino carry generate gate has a first evaluation block of transistors and a second evaluation block of transistors, and the second evaluation block has the same number of transistors connected in a parallel relationship as the first evaluation block and the same number of transistors connected in a serial relationship as the first evaluation block.

Abstract: A digital adder circuit is implemented using a Kogge-Stone architecture. Various embodiments utilize single-ended domino circuits, to which are input single-ended primary addends. Dual-function generator circuits generate differential sum and sum-complement output signals. The use of low VT devices and full CMOS circuitry provides a relatively high degree of noise immunity. Also described are a microprocessor having an ALU incorporating one or more of the adder circuits, as well as a method of adding two numbers which generates differential sum and sum-complement outputs but does not use full-differential domino circuits, thus providing considerable savings in circuit area, circuit conductors, and layout complexity.

Abstract: Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations.

Abstract: A method and apparatus are provided for performing a fast sum-and-compare operation. The apparatus of the present invention utilizes a single carry save adder in conjunction with a zero detect circuit for performing logic operations to determine whether or not the sum of a plurality of operands is equal to one or more constants. The Carry Save Adder generates a sum, M, and carry, L, that are output from the carry save adder to the zero detect circuit. The zero detect circuit produces internal carry signals that are passed between adjacent bit-cells of the zero detect circuit. The zero detect circuit generates outputs Zk1 through Zkn which are true if the condition A+B+C={k1, k2, k3 . . . kn} for all constants k1 through kn. The carry signals propagate through only one bit of the zero detect circuit, thereby providing the sum-and-compare circuit of the present invention with extremely high speed.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

Abstract: A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. The carry generator receives an exclusive-OR value P(i, i=1,2,3,4) and a logic product value G(i) of two data, and an initial carry value C(1), and performs a function of G(4)+P(4).multidot.G(3)+P(4).multidot.P(3).multidot.G(2)+P(4).multidot.P(3 ).multidot.P(2).multidot.G(1)+P(4).multidot.P(3).multidot.P(2).multidot.P(1 ).multidot.C(1) to output a final carry value C(5). The carry generator includes a first NMOS transistor for executing an operation of P(4).multidot.G(3), second and third NMOS transistors for executing an operation of P(4).multidot.P(3).multidot.G(2), fourth to sixth NMOS transistors for executing an operation of P(4).multidot.P(3).multidot.P(2).multidot.G(1), seventh to eleventh NMOS transistors for executing an operation of P(4).multidot.