Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: Methods, systems, and devices for split and duplicate ripple circuits are described. A ripple circuit may be divided into stages, which may operate in parallel. For example, a first stage may have a finite number of possibilities for an output that is relevant for a second stage, and the second stages may be replicated according to the finite number of possibilities. The replicated second stages thus may operate concurrently with each other and the first stage, with each of the replicated second stages assuming a different possible output from the first stage. Once operation of the first stage is complete, the true output of the first stage may be used to select one of the second stages as corresponding to the correct assumed output, and the output of the selected second stage may be or may be included in a set of output signals for the circuit.

Abstract: An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

Abstract: A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

Abstract: Generalized parallel counter circuitry is configured from logic elements—e.g., on a programmable integrated circuit device. Each logic element includes a logic stage, an adder and an output stage. The logic stage includes logic units, and a logic stage selector for selectively outputting to an input of the adder at least one of (a) outputs of the logic units, and (b) a first logic unit output of another one of the logic elements, and for selectively outputting to the output stage one of (a) an output of the logic units, and (b) a first output of the adder. The output stage includes at least two outputs, an output selector for selectively outputting, to the at least two outputs, at least one of (a) a second output of the adder, and (b) an output of the logic stage selector.

Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.

Abstract: A keyboard for a mobile device 400 having a processor 618 for interpreting signals comprises a plurality of keys 410-424 and corresponding indicia including keys associated with alphabetic characters corresponding to an array of letters A-Z. The keys 410-419 that are associated with alphabetic characters number fewer than twenty-six and correspond to one of a QWERTY, QWERTZ, AZERTY, or DVORAK key arrangement. Each of the plurality of keys 410-424 have multiple input surfaces and are arranged in an array of rows and columns that include a first outer column, at least one middle column, and a last outer column. The first and last columns of keys are operable to input at least three different signals to a processor 618 of a mobile device 400 depending upon what input surface of the key 410-424 is pressed. A middle column of keys is operable to input at least five different signals to a processor 618 depending on what input surface of the key 410-424 is pressed.

Abstract: A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.

Abstract: Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, Ax, from the first M-bit argument and a first data bit, Bx, from the second M-bit argument, and generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the Cx(0) bit is calculated assuming the row carry-out bit from the second row is a 0.

Abstract: A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of adder logic stages, each of the plurality of adder logic stages performing a carry propagate addition of the received portions to generate an intermediate sum, a propagate value and a carry; and further logic stages for combining the intermediate sums, carries and propagate values to produce a sum of the two data values. The control logic, further in response to a request to add a third data value to the sum before the further logic has completed sum, forwards portions of the third data value to respective ones of the plurality of adder logic stages, feedbacks the intermediate sums, and selectively feedbacks a carry generated from a preceding adder logic stage.

Abstract: An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series, each estimating block being capable of estimating each bit of the sum, and a correction circuit capable of generating a correction signal so as to correct each estimated bit of the sum after each estimate. Each correction signal of an estimated bit rank i of the sum is generated using the last rank i?1 estimated and corrected bit of the sum, the correction signal of said last rank i?1 bit, and the last estimated and corrected rank i?2 bit of the sum.

Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.

Abstract: A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay.

Abstract: A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force—1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force—1 signal. The two functions are implemented without introducing additional delay.

Abstract: In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.

Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.

Abstract: A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a Manchester-carry-chain configured bit carry circuit to generate first bit carry signals where a block carry exists in each of the M blocks and second carry bit signals where no block carry exists, based on the bit values; a control circuit to generate, independently of a clock enable signal at a logical level, selection-control signals based upon the block carry signals; and a summation selection circuit to select between the first bit carry signals and the second bit carry signals and to add the carry propagation bit values and the selected carry signals.

Abstract: Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: a first stage that produces separate sum and carry results in a first cycle, and a second stage that produces a final result in one or more immediately subsequent cycles. While this produces final results in two or more clock cycles, useable partial results are produced each cycle, thus maintaining a one operation per clock cycle throughput.

Abstract: Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carries corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carries are transferred. In addition, actual carry signals are selected from the provisional carries corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carries are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.

Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

Abstract: An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.

Abstract: An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input while the XOR output is made a selection signal, a second multiplexer for selecting one of the second carry input or the second data input, a third multiplexer for selecting one of the first or the second carry inputs while the carry selection input is made a selection signal, and a second XOR element for generating an XOR output of an output of the third multiplexer and the XOR output, and is characterized in that an output of the first multiplexer is made a first carry output, an output of the second multiplexer is made a second carry output, and an output of the third multiplexer is made an addition value.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculated initial sum is then performed. Next, an intermediate sum for each group of M-initial sums according to a respective initial carryout value of each initial sum is then generated. Once generated, an intermediate carryout value for each generated intermediate sum is then calculated. Finally, a final sum is calculated from the intermediate sums generated according to a respective intermediate carryout of each intermediate sum.

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.

Abstract: Provided is an adder composed of (N+1) circuit stages in the case of 2N bits. In the case of N=4 (that is, 16 bits), provisional carriers that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carriers corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carriers are transferred. In addition, actual carry signals are selected from the provisional carriers corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carriers are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.

Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Abstract: In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit adders.

Abstract: An adder for use in summing two binary numbers in an arithmetic logic unit of a processor or the like is disclosed and claimed. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.

Abstract: The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/−1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder comprises a plurality of byte adder cells and carry look-ahead (CLA) logic. The adder cells determine which of themselves is the least significant bit (LSB) byte adder cell. The LSB cell then adds one of the increment values to its loaded value. The other cells add 0x00 or 0xFF, depending upon the sign of the increment value, to a loaded value from memory. Each adder performs two adds, one for a carry-in of 0, and the other for a carry in of 1. Both results are sent to a MUX. The CLA logic determines each of the carries, and provides a selection control signal to each MUX. of the different cells.

Abstract: A multiplexer based adder circuit. The novel adder design is suitable for a number of bit sizes, but in one exemplary embodiment is a 64-bit adder. A complete 16-bit scaled adder is taught. The adder circuit is efficient and reconfigurable in that the adder can be partitioned to support a variety of data formats. The adder can add two 64-bit operands, four 32-bit operands, eight 16-bit operands, or sixteen 8-bit operands. The reconfigurability of the adder for different word sizes is achieved using only a small number of control signals for partitioning without increasing the adder size or reducing its speed. The novel adder circuit is designed using multiplexer circuits and two input inverted logic gates making the adder very fast. The adder design recognizes that pass transistor based multiplexer circuits and inverted logic gates are the fastest circuit elements for standard CMOS logic.

Abstract: A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry multiplexer selects one of a plurality of possible carry inputs to the following sections. The data processing circuit may make the specification of the selection of the carry control multiplexers by: the opcode of the instruction; a combination of the opcode and an opcode modification field; an immediate field directly specifying carry control signals; or designation a carry control register which stores the carry control signals. The adder unit may be divided into sections of equal size or of unequal size.

Abstract: A one's complement adder uses two two's complement adders, both of which are coupled to receive first and second addends at their addend inputs, however the first two's complement adder is adapted to output a first sum that is the one's complement sum that would result if no carry occurred upon addition of the first and second addends and the second two's complement adder is adapted to output a second sum that is the one's complement sum that would result if a carry did occur. A selector selects one of the first sum and the second sum as its output (and the output of the one's complement adder) based on whether or not a carry occurred.

Abstract: A method and system for use in a data processing system is proposed, wherein the Input Exponent is used already in the subblocks of the mantissa addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put together using zero detect signals and carry select signals of the Carry Select Adder of the mantissa addition. For the addition of two floating point numbers this reduces the number of required logic gates in the timing critical path. This allows a faster cycle time and/or less latency and/or more complex functions. The method and system according to the invention can be applied to adders of different mantissa widths or different exponent widths as well as power of radix 2.

Abstract: Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask signal based on an amount of shift and split mode information. An output selector replaces data shifted by the shifter with code extension data bit by bit based on the mask signal, and outputs data which are shifted and code-extended according to the split mode information and arithmetic/logical shift information. In a carry-select type adder/subtractor as another embodiment, if split parallel process is to be executed, both a pair of unit adders/subtractors execute an arithmetic operation to be carried out for the case where no carry is supplied from lower digits, and then a selector selects an arithmetic result, which is obtained when no carry is supplied from lower digits, regardless of the carry from the lower digits.

Abstract: A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

Abstract: A recursive divide and conquer strategy is applied to the structure of carry select adders. This adder is partitioned into two components, each computing the sums of their inputs with and without carry in, and each component is then recursively partitioned further. The two components are combined by selecting the appropriate part of the more significant sum using the carries of the less significant component.

Abstract: A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit comprises a carry look-ahead (CLA) tree portion and a summer portion. The CLA tree portion generates carry bits, as well as the logical relationship A.sub.i XOR B.sub.i, for application to a summer for bit position i. The carry bits contain information for either inverting or not inverting the A.sub.i XOR B.sub.i bit for both the sum and the sum plus 1 output of the summer. The sum bit and sum plus 1 bit are generated at approximately the same time.

Abstract: Disclosed is an integrated pass-transistor logic circuit which includes a conditional sum adder. This sum adder has seven sum generation blocks of module form and two carry generation blocks. With the sum adder, before carry propagation which is generated through multiplexer chain in respective sum generation blocks arrives at the final stage of the multiplexer chain, the final stage is driven by block carry signals BC.sub.i and /BC.sub.i provided from the respective carry generation blocks. The carry generation and the sum generation occur individually in the conditional sum adder. The sum generation blocks are constituted with pass-transistor logic and the carry generation blocks with Complementary Metal Oxide Semiconductor (CMOS) logic, the sum adder has a more faster operation speed and a more lower power dissipation, as compared with the prior art conditional sum adder having either the pass-transistor logic or the CMOS logic.

Abstract: A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first presumed carry-in signal and a second candidate carry-out signal is based on a second presumed carry-in signal different than the first presumed carry-in signal. A two-level selector for simultaneously selects, for each of the pairs of candidate carry-out signals, either the first candidate carry-out signal or the second candidate carry-out signal as an actual carry-out signal, based on an actual carry-in signal. Both selected carry out signals are passed to.

Abstract: A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero.