Abstract: An optical-electronic device can be controlled by a bias voltage to simulate an electronic component such as a resistor, capacitor, inductor with resistor, or capacitor with resistor. The optical-electronic device can be connected in a network to perform computations, model problems, simulate properties such as physical properties (for instance heat transfer), and achieve circuit performances to carry out computations in the analog domain, all at faster speed with smaller size and at less energy.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Abstract: A method is described for generating a challenge-response pair in an electric machine as the basis for an authentication. The electric machine has at least one stator and at least one rotor. A voltage signal or current signal which causes induction between the rotor and the stator is generated as the challenge, and a variable which is a function of the caused induction is determined as the response.

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

Abstract: A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further on using it to determine Elliptic curve scalar multiplication over a finite elliptic curve.

Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

Abstract: System and method for controlling/analyzing a process by solving a system of linear equations in real-time. Linear equations that model the process are stored. In an off-line stage a partitioning strategy is determined based on the linear equations, including determining groups of values for recursively partitioning a set of values measured and/or computed from the process. In an on-line stage: current process data are received from the process, including measurements from the process, and composing a set of values; the linear equations are recursively solved for a first group of the set, where the first group partitions the set into respective subsets of values, and where the recursively solving produces solved values for respective first groups of the set/subset of values; the linear equations are solved for remaining unsolved values in the set, thereby producing solved values for the set, which are stored and are useable to control/analyze the process.

Abstract: A system comprises a workload evaluator that is operable to receive a representative workload that is representative of competing demands for capacity of at least one shared computing resource. The workload evaluator evaluates the representative workload and computes a metric representing a degree of burstiness of demands present in the representative workload. The metric representing degree of burstiness of the representative workload may be used for estimating an upper bound on quality of service provided by a workload manager to the representative workload. The metric may also be used for evaluating at least one scheduler parameter setting of the workload manager to aid in determining an optimal parameter setting based at least in part on the estimated impact of the representative workload on QoS provided by the workload manager.

Abstract: A method is described for generating a challenge-response pair in an electric machine as the basis for an authentication. The electric machine has at least one stator and at least one rotor. A voltage signal or current signal which causes induction between the rotor and the stator is generated as the challenge, and a variable which is a function of the caused. induction is determined as the response.

Abstract: An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.

Abstract: Schedulability determination method of determining whether real-time scheduling of tasks is possible using processors, includes calculating Lk and ?i=1 . . . NMi*Uk, i, (1?k, i?N; k, i: integer) where Lk corresponds to task-k, Mi represents number of the one or more processors simultaneously used by task-i, Uk, i corresponds to task-k and task-i, and N represents number of tasks, and determining that real-time scheduling of tasks is possible using processors, if tasks all satisfy conditions, ?i=1 . . .

Abstract: In some embodiments, the Navier-Stokes matrix A may be developed on the fly using arrays of Dirichlet and von Neumann boundary conditions. As a result, the storage requirements are dramatically reduced and hardware accelerators or single instruction multiple data processors may be used to solve the Navier-Stokes equations.

Abstract: A method for converting a polynomial expression to a data structure for symbolic computation. One or more variables in the polynomial expression may be determined. The variables may be stored in a first array. One or more terms in the polynomial expression may be determined. One or more exponents of the variables in each term may be determined. The exponents may be stored in a second array. One or more coefficients of the terms may be determined. The coefficients may be stored in a third array.

Abstract: The invention provides bounded model checking of a program with respect to a property of interest comprising unfolding the program for a number of steps to create a program formula; translating the property of interest into an automaton; encoding the transition system of the automaton into a Boolean formula creating a transition formula; conjoining the program formula with the transition formula to create a conjoined formula; and deciding the satisfiability of the conjoined formula.

Abstract: Methods and apparatus for performing non-linear analysis using preconditioners to reduce the computation and storage requirements associated with processing a system of equations. A circuit, system or other device to be analyzed includes n unknown waveforms, each characterized by N coefficients in the system of equations. A Jacobian matrix representative of the system of equations is generated. The Jacobian matrix may be in the form of an n×n sparse matrix of dense N×N blocks, such that each block is of size N2. In an illustrative embodiment, a low displacement rank preconditioner is applied to the Jacobian matrix in order to provide a preconditioned linear system. The preconditioner may be in the form of an n×n sparse matrix which includes compressed blocks which can be represented by substantially less than N2 elements.

Abstract: A programmable Very Large Scale Integration (VLSI) chip and method for the analog solution of a family of partial differential equations commonly encountered in engineering and scientific computing: The Laplace equation, the diffusion or conduction equation, the wave equation, the Poission equation, the modified diffusion equation, the modified wave equation, and the wave equation with damping.

Abstract: The reliability of solutions of simultaneous algebraic equations with integral coefficients is improved and high-speed information processing is realized. A method processes information wherein, in a model in which restrictions among parameters are given by simultaneous algebraic equations with integral coefficients, when the simultaneous equations have only a finite number of solutions, zero points of a polynomial set F with integral coefficients, which represents the simultaneous equations and is described in a memory, are represented by rational expressions based on zero points of a one-variable polynomial regarding one variable so that the information is represented using the representation of rational expression. The method processes information by choosing a term order, calculates a Grobner basis, calculates a minimum polynomial f1, and controls a digital processor to find solutions represented by rational expressions.