Differential (e.g., Differential Analyzer) Patents (Class 708/804)
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Patent number: 11734009Abstract: A data processing system comprises fetch circuitry to fetch data as a sequence of blocks of data from a memory. Processing circuitry comprising a plurality of processing pipelines performs at least partially temporally overlapping processing by at least two processes so as to produce respective results for the combined sequence of blocks, i.e. the processing of the data is performed on a block-by-block process at least partially in parallel by the two processing pipelines. The processes performed may comprise a cryptographic hash processing operation performing verification of the data file and a AES MAC process serving to re-signature the data file.Type: GrantFiled: June 4, 2018Date of Patent: August 22, 2023Assignee: Arm LimitedInventors: Oded Golombek, Nimrod Diamant
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Patent number: 10002564Abstract: To provide a display device which can perform external correction and has a reduced area occupied by a read circuit. The display device includes a pixel and the read circuit. The pixel includes a transistor and a display element. The read circuit includes a function selection portion and an operational amplifier. The transistor is electrically connected to the function selection portion through a wiring. The operational amplifier is electrically connected to the function selection portion. The function selection portion includes at least one switch and can select the function of the read circuit by switching of the switch.Type: GrantFiled: October 28, 2015Date of Patent: June 19, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Hiroyuki Miyake
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Patent number: 8326593Abstract: Embodiments may include methods, systems, and computer-readable storage mediums that may be used to simulate phase noise for an oscillator circuit. In some embodiments, a method of simulating phase noise for an oscillator circuit may include providing an oscillator circuit description. A time-domain representation of a small signal phase noise of the oscillator circuit description may be determined. A shooting Newton matrix representation of the time-domain representation of the small signal phase noise may be generated. The shooting Newton matrix representation may be augmented to include a phase-shift factor and a pinning equation. The augmented shooting Newton matrix representation may be solved to determine a signal output of the oscillator circuit.Type: GrantFiled: May 25, 2010Date of Patent: December 4, 2012Assignee: Cadence Design Systems, Inc.Inventors: Yu Zhu, Xiaolue Lai
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Patent number: 8204925Abstract: System and method for controlling/analyzing a process by solving a system of linear equations in real-time. Linear equations that model the process are stored. In an off-line stage a partitioning strategy is determined based on the linear equations, including determining groups of values for recursively partitioning a set of values measured and/or computed from the process. In an on-line stage: current process data are received from the process, including measurements from the process, and composing a set of values; the linear equations are recursively solved for a first group of the set, where the first group partitions the set into respective subsets of values, and where the recursively solving produces solved values for respective first groups of the set/subset of values; the linear equations are solved for remaining unsolved values in the set, thereby producing solved values for the set, which are stored and are useable to control/analyze the process.Type: GrantFiled: May 19, 2009Date of Patent: June 19, 2012Assignee: National Instruments CorporationInventors: Aljosa Vrancic, Lothar Wenzel
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Publication number: 20110225225Abstract: Each ordinary differential equation of simultaneous ordinary differential equations is solved with an embedded Runge-Kutta method. A difference ? between an N-th order approximation and an (N+1)th order approximation is computed, and it is determined whether the difference is smaller than a predetermined threshold ?0. If ???0, then a step size is determined using a predetermined computation formula containing ?0/?, and then the process proceeds to next computation. A strand having an error of ?>?0 is directed to execute recomputation using a step size calculated based on ?0/?. Then the strand having the error executes recomputation by using a computed interpolated value. When the strand's error becomes smaller than the threshold ?0 the strand reaches the same time step as the strands computing the other ordinary differential equations having no error. The process thereby proceeds to next computation of the whole simultaneous ordinary differential equations.Type: ApplicationFiled: March 11, 2011Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arquimedes Martinez Canedo, Hideaki Komatsu, Takeo Yoshizawa
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Patent number: 7332974Abstract: A computer-implemented method computes the steady-state and control voltage of a voltage controlled oscillator, given a known frequency or a known period of oscillation of the voltage controlled oscillator. Differential algebraic equations representative of the voltage controlled oscillator are generated, where the differential algebraic equations includes a known period or frequency of oscillation and an unknown control voltage of the voltage controlled oscillator. The differential algebraic equations are modified using a finite difference method, a shooting method, or a harmonic balance method, to obtain a set of matrix equations corresponding to the differential algebraic equations. A solution to the matrix equations is obtained using a Krylov subspace method, using a preconditioner for the Krylov subspace method that is derived from a Jacobian matrix corresponding to the matrix equations, where the solution includes the control voltage of the voltage controlled oscillator in steady state.Type: GrantFiled: January 27, 2005Date of Patent: February 19, 2008Assignee: Berkeley Design Automation, Inc.Inventors: Amit Mehrotra, Amit Narayan
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Patent number: 7333924Abstract: A method for device level simulation of a circuit modeled by a set of CCR graphs, a computer system programmed to perform such a method, and a computer readable medium which stores code for implementing such a method. Typically, the circuit includes MOS transistors having unknown gate potentials, each CCR graph includes a top rail, and a bottom rail, and variable nodes, each of the transistors having unknown gate potential is modeled in the CCR graphs as a selectable resistor having a selected one of a first resistance and a much larger second resistance, and the method includes the steps of determining potentials at variable nodes of one of the CCR graphs with each selectable resistor of the graph having its first resistance (and also with each selectable resistor of the graph having its second resistance) without determining effective resistances between the variable nodes of the graph and the top rail or bottom rail.Type: GrantFiled: June 28, 2004Date of Patent: February 19, 2008Assignee: National Semiconductor CorporationInventors: Tathagato Rai Dastidar, Partha Ray
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Patent number: 6141676Abstract: A programmable Very Large Scale Integration (VLSI) chip and method for the analog solution of a family of partial differential equations commonly encountered in engineering and scientific computing: The Laplace equation, the diffusion or conduction equation, the wave equation, the Poission equation, the modified diffusion equation, the modified wave equation, and the wave equation with damping.Type: GrantFiled: July 22, 1998Date of Patent: October 31, 2000Assignee: New Mexico State University Technology Transfer CorporationInventors: Jaime Ramirez-Angulo, Mark R. DeYong