Interpolation/extrapolation Patents (Class 708/847)
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Patent number: 12003591Abstract: A catalogue system automatically detects changes to configuration file at a service application. Based on the changes to the configuration file(s), the catalogue system stores mapping data that identifies a resource item type that can be processed by the service application and one or more user actions that are available for processing resource items of the resource item type. The techniques thus provide for dynamic interaction with service applications.Type: GrantFiled: May 24, 2021Date of Patent: June 4, 2024Assignee: Palantir Technologies Inc.Inventors: Adam Campbell, Ashwin Ramaswamy, Juan Tamayo, Lee Avital, Taylor Morgan, Thomas Hasner
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Patent number: 11736047Abstract: Methods and apparatus to control a three-phase BLDC motor with a curve transformer having an index value for each stored input value and output value for providing stored corner points for outputs of the curve transformer. The curve transformer can output interpolated data for input data between adjacent ones of the input values.Type: GrantFiled: March 16, 2020Date of Patent: August 22, 2023Assignee: Allegro MicroSystems, LLCInventor: Yisong Lu
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Patent number: 8705359Abstract: Method of predicting capacity demands on a desired device used to support services for a number of subscribers within a market area having a number of devices. The method includes predicting the capacity demands as a function of historical capacity demands for the desired device and average subscriber capacity demands on the number of devices in the market area.Type: GrantFiled: March 13, 2006Date of Patent: April 22, 2014Assignee: Comcast Cable Holdings, LLCInventor: Claude H. Bou-Abboud
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Patent number: 8537171Abstract: Nonlinear compression of high precision image data (e.g., 12-bits per subpixel) conventionally calls for a large sized lookup table (LUT). A smaller sized and tunable circuit that performs compression with piecewise linear compressing segments is disclosed. The piecewise linear data compressing process is organized so that lumping together of plural ‘used’ high precision value points into one corresponding low precision data value point is avoided or at least minimized. In one embodiment, the compressed data is image defining data being processed for display on a nonconventional display screen where the piecewise linearly compressed data can be stored adjacent to other image data in a frame buffer where a composite image is assembled.Type: GrantFiled: May 13, 2011Date of Patent: September 17, 2013Assignee: Samsung Display Co., Ltd.Inventors: Michael Francis Higgins, Candice Hellen Brown Elliot
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Patent number: 8229987Abstract: A direct sampling circuit and a receiver which carry out discrete time analog processing with a high degree of design freedom and are provided with a filter property which is achievable to comply with the receipt of a broad band signal. A plurality of discrete time analog processing circuits (101) are connected in parallel with each other, a gm value and a capacitance of a capacitor in each circuit system are set independently based on a prescribed condition, and an output signal obtained from each circuit system is synthesized by means of a buffer capacitor (102), so that an equivalently high-dimensional IIR filter can be put into practice.Type: GrantFiled: March 5, 2007Date of Patent: July 24, 2012Assignee: Panasonic CorporationInventors: Yoshifumi Hosokawa, Katsuaki Abe, Noriaki Saito, Kiyomichi Araki, Yohei Morishita
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Patent number: 8218909Abstract: A method for deformable registration of 2 digital images includes providing a pair of digital images, including a fixed image and a moving image, extracting a set of edge images from each image of the pair of images, each edge set being extracted at a different resolution, selecting a pair of edge images with a lowest resolution, determining a mapping from edge points of the fixed image to edge points of moving image using a geodesic thin plate spline interpolation, applying the mapping to a next higher resolution edge point image of the moving image, selecting a pair of edge images at a next higher resolution, where a moving edge image is the moving edge image to which the mapping has been applied, repeating the steps at a next higher resolution for all edge images in the set of edge images, and applying the mapping to an entire moving image.Type: GrantFiled: August 26, 2008Date of Patent: July 10, 2012Assignee: Siemens AktiengesellschaftInventors: Ali Khamene, Fabrice Michel
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Patent number: 8077784Abstract: An OFDM (Orthogonal Frequency Division Multiplexing) demodulator includes: an FFT (Fast Fourier Transform) circuit for performing a fast Fourier transform on an OFDM signal; a circuit for extracting an SP (Scattered Pilot) signal from the fast Fourier transformed signal; a circuit for adding a positive or negative sign to the extracted SP signal; a memory for temporarily storing the signed SP signal and an information transmission signal; a carrier interpolation circuit for performing time axis interpolation and frequency axis interpolation on the signed SP signal by a plurality of methods; a complex division circuit for performing a complex division of the information transmission signal by interpolated data; and a memory interface for detecting a timing a prescribed number of signed SP signals have been obtained and an output timing of the interpolated data according to the interpolation method.Type: GrantFiled: May 21, 2007Date of Patent: December 13, 2011Assignee: Panasonic CorporationInventor: Tomoki Nishikawa
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Patent number: 7711209Abstract: According to one embodiment, a first correlation calculator calculates a correlation between first pixel blocks, and detects as first reference pixels actual pixels contained respectively in the first pixel blocks with the highest correlation. A second correlation calculator calculates a correlation between second pixel blocks, and detects as second reference pixels actual pixels contained respectively in the second pixel blocks with the highest correlation. The first pixel blocks include pixels arranged in a plurality of rows and columns The second pixel blocks include pixels arranged in at least one row less than the rows of the first pixel blocks and a plurality of columns. An interpolation calculator calculates, when the first reference pixels are located perpendicular to the actual pixel lines, the pixel value of the interpolation pixel based on the second reference pixels.Type: GrantFiled: February 9, 2009Date of Patent: May 4, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Tadayoshi Kimura
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Patent number: 7084883Abstract: An image processing device and method for processing an image defined by a combination of unit graphic forms or polygons are provided with an interpolated line completion unit which determines an interpolated line which is the line that interpolates a space between two vertices from an interpolation vector used to determine a line interpolating a space between a given vertex and another vertex among vertices of the unit graphic forms and from the coordinates of those vertices. An interpolated point computation unit is provided which determines as vertices of sub-unit graphic forms or subpolygons into which the polygons are to be split by the processing image device, interpolated points which are the points on the interpolated line. The interpolated line is a Bezier curve.Type: GrantFiled: August 29, 2001Date of Patent: August 1, 2006Assignee: Sony Computer Entertainment Inc.Inventor: Nobuo Sasaki