Abstract: Embodiments of the invention disclose devices, methods, and computer media for noise rejections in a remote sensing device, such as a LIDAR device. In an exemplary embodiment, a spatial filter includes an aperture dynamically created in synchronization with one or more directions in which emitted laser pulses from the LiDAR device are steered. Photons from all other directions except the one or more directions are blocked by the spatial filter. Reflected photons from the one or more directions pass through the spatial filter via the aperture, and are projected on one or more sets of photodetectors. Noises in the photons that pass through the spatial filter are further to be rejected based on one or more fixed temporal patterns identified in laser pulses emitted by the LiDAR device. The spatial filter can be implemented using an electrochromic display, an array of micromechanical (MEMS) mirrors, a liquid crystal display (LCD), or an electro-wetting display.

Abstract: A signal processor includes a signal receiving circuit, a pre-processing circuit, a period acquisition circuit, and a decoding circuit. The signal receiving circuit is configured to receive an input signal. The pre-processing circuit is configured to generate a square wave signal according to the input signal. The period acquisition circuit is configured to capture several periods of the square wave signal. The several signal periods includes several signal period groups, and each of the several signal period groups includes at least two signal periods of the several signal periods. The at least two signal periods are adjacent to each other. The decoding circuit is coupled to the period acquisition circuit and is configured to perform decoding according to a time length and a number of times of voltage value change of the several signal period groups to obtain a decoding result.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.

Abstract: The universal CMOS current-mode analog function synthesizer is based on approximating the required function using its sixth-order Taylor series expansion. These approximations can be implemented by adding the weighted output currents of a number of basic building blocks built around a basic current squarer, and a constant current. The circuit can simultaneously realize thirty-two different mathematical functions and can be easily expanded to accommodate many others.

Abstract: A method for constructing a conductor assembly of the type formed of one or more coil rows which, when conducting current, generate a magnetic field or in which, in the presence of a changing magnetic field, a voltage is induced.

Abstract: An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.

Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: Method and apparatus for interpolation of signals from a delay line is described. An input signal is obtained from which progressively delayed input signals are generated from the input signal. Two of the progressively delayed input signals are accessed and interpolated to provide a phase-adjusted signal.

Abstract: A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor ?(x0,y0) of the Taylor series equation. The DAC control register uploads a lead term F(x0,y0) of the Taylor series equation from the digital processor to the DAC. The first-order digital registers controls resistances of the R2R ladders. The second-order digital registers uploads coefficients Fx, Fy, Fxx, Fxy, Fyy of the Taylor series equation from the digital processor to the DAC. The analog integrator adds outputs from the DAC and the R2R ladder to generate approximation results for the Taylor series equation.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: Temperature compensation may be provided to a square function generator by adjusting a tail current of the square function generator. Temperature compensation of the square function generator may be provided, for example, by a second square function generator circuit and an error amplifier. The second square function generator may be substantially similar to the first square function generator. The error amplifier is arranged in cooperation with the first and second square function generators such that the output of the error amplifier adjusts the tail current of the square function generators. A plurality of temperature square function generators may be configured to provide a temperature-compensated cubic function. The temperature compensated cubic function may be used for S-correction in a display system such as a cathode ray tube.

Abstract: An arbitrary function generating circuit incorporating an analog multiplier, amplifier, and frequency multiplier to construct a nonlinear analog circuit equivalent to a generalized Lotka-Volterra equation for performing high-speed calculations.

Abstract: An on-board self test system for an electrical power monitoring device includes a test signal circuit in an electronic circuit of the monitoring device, and responsive to a programmable test input signal for producing an analog signal simulating an electrical power waveform, and a programmable memory in an electronic circuit of the monitoring device and operatively coupled with the test signal circuit for storing and reproducing upon command, one or more of the programmable test input signals.

Abstract: A method is provided for synthesizing an arbitrary waveform that approximates a specific waveform. The method includes specifying respective frequencies of component waveforms to be used to generate the arbitrary waveform, the frequencies being less than the maximum frequency needed to synthesize the specific waveform. The method further includes performing a least squares optimization of respective amplitudes and phases of the component waveforms across at least one predetermined time interval. The component waveforms having the amplitudes and phases optimized by the least squares optimization are then summed to produce the arbitrary waveform.

Abstract: A system and circuit is provided for digitally synthesizing the impedance of a transfer function. The impedance of the transfer function is digitally synthesized by generating a current that, when combined with an input voltage, results in the impedance of the transfer function. This is accomplished by sensing the input signal and processing it with a generator or multiplier such that a voltage is produced. The produced voltage controls a current source and creates a current having a value equal to the inverse of the transfer function impedance. The sensed or input voltage divided by the generated current is equal to the impedance of the transfer function. In this manner, many different transfer functions can be digitally synthesized without having to design an alternate circuit.