Abstract: A logarithmic conversion circuit comprises: an operation amplifier; an input resistor connected at a preceding stage of an inverting input terminal, of the operation amplifier, to which a current signal is inputted; and a logarithmic conversion device and a current feedback device connected in series between the inverting input terminal and an output terminal of the operation amplifier, and an inverse-logarithmic conversion circuit comprises: a current/voltage conversion circuit which, after the current signal having passed through the current feedback device is inputted, converts the inputted current signal to a voltage value corresponding thereto; and a subtraction circuit outputting the difference between an output voltage of the current/voltage conversion circuit and a predetermined reference voltage, a circuit constant of the subtraction circuit being set such that the difference output of the subtraction circuit has a linearity proportional to the current signal.

Abstract: The arbitrary power law function generator uses an equal number of exponential and logarithmic circuits, e.g., two exponential and two logarithmic circuits, which are current-mode, current-controlled circuits that provide positive, negative, integer, or non-integer powers independent of temperature. Moreover, the circuit can operate from a DC power supply as low as ±1.5V. SPICE simulation results using practical bipolar junction transistor (BM parameters are included to confirm the feasibility of the function generator.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, a guard circuit arranged to force an input current into an input terminal of the logging transistor, and a positioning circuit arranged to maintain a voltage of the logging transistor. The guard and positioning circuits may include first and second feedback loops, respectively. Another embodiment of a logarithmic circuit may include a logging transistor arranged to generate a logarithmic output in response to an input current, and a feedback loop arranged to provide adaptive compensation to the logging transistor. The feedback loop may be arranged to provide compensation in response to the magnitude of the input current. Another embodiment of a logarithmic circuit may include first and second logging transistors having collectors arranged to receive input currents, and first and second feedback amplifier arranged to drive emitters of the logging transistors.

Abstract: A logarithmically-responding circuit includes a differential-input amplifier that drives the control terminal of a three-terminal device that exhibits an exponential response in its output current. This arrangement allows the third terminal to be grounded. In a preferred embodiment the three-terminal device is a bipolar junction transistor (BJT). This, and other supporting circuit features described, enable single-supply, wide-range, fully temperature-compensated operation. A compensation technique significantly reduces errors caused by the finite ohmic emitter resistance of a BJT. To support use in logarithmically compressing the current generated by a photodiode, an adaptive bias signal can provided which maintains an essentially constant bias on the photodiode's internal junction.

Abstract: A logarithmically-responding circuit includes a differential-input amplifier that drives the control terminal of a three-terminal device that exhibits an exponential response in its output current. This arrangement allows the third terminal to be grounded. In a preferred embodiment the three-terminal device is a bipolar junction transistor (BJT). This, and other supporting circuit features described, enable single-supply, wide-range, fully temperature-compensated operation. A compensation technique significantly reduces errors caused by the finite ohmic emitter resistance of a BJT. To support use in logarithmically compressing the current generated by a photodiode, an adaptive bias signal can provided which maintains an essentially constant bias on the photodiode's internal junction.

Abstract: An integrated circuit has a command/control bus and a number of processing elements. The processing elements contain a number of parts, each part being connected to said command/control bus. Each one of the processing elements is re-configurable in response to commands on said command/control bus to provide any one of a plurality of different arithmetic operations.

Abstract: An integrated circuit has a command/control bus and a number of processing elements. The processing elements contain a number of parts, each part being connected to said command/control bus. Each one of the processing elements is re-configurable in response to commands on said command/control bus to provide any one of a plurality of different arithmetic operations.

Abstract: A modular exponentiator is adapted to receive a first communicated signal and derive a second signal therefrom by computation of a modular exponentiation of the form be mod n based on the first signal. The modular exponentiator divides the modular exponentiation according to the Chinese remainder theorem into first and second portions respectively having modulus values p and q of approximately half of an original modulus value n of the modular exponentiation. Each portion of the modular exponentiation is factored into respective pluralities of smaller modular exponentiations having precalculated exponent values. The respective pluralities of smaller modular exponentiations are then multiplied together to provide respective intermediate products. The intermediate products are then recombined to yield the modular exponentiation result.