Abstract: A controller includes a physical layer interface circuit configured to support a first port and a second port both conforming to a PCIe standard, the first port including a first number of lanes with a first order, the second port including a second number of lanes with a second order, and the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via traces arranged in an order in which at least a part of the first order and at least a part of the second order are changed based on Lane Reversal conforming to the PCIe standard.

Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

Abstract: A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method is provided that includes receiving a video timing pulse, determining, in response to receiving the video timing pulse, a video engine is busy processing a previous frame, and storing settings for a current frame in a pending queue in response to determining the video engine is busy processing the previous frame. The method further includes configuring the video engine with the settings for the current frame from the pending queue after the video engine has completed processing of the previous frame, and processing, using the configured video engine, the current frame.

Abstract: A communication device for connection with a power source and a host device is provided. The communication device comprises a device controller and a converter circuit. The device controller is adapted for data communication with the host device and the converter circuit is configured to provide a virtual device ground at least to the device controller, so as to compensate a ground potential difference between the host device and the communication device.

Abstract: In accordance with one aspect of the invention, an automation control device, such as a host or hub, is provided with functionality so that it becomes a multi-role automation control device. The multi-role automation control device is capable of controlling an expanded variety of “smart” or other devices. The multi-role automation control device may be implemented using a variety of underlying devices including a host, hub, soundbar, “smart” thermostat, “smart” amplifier, audio speaker, or other device.

Abstract: A method and apparatus for processing a transaction between a merchant and a customer of the merchant are described. The method may include generating, at an ingress server, an initial transaction message by generating a deterministic identifier for a card used in the transaction from card data received for the transaction and encrypting the received card data. The method may also include providing the initial transaction message from the ingress server to a payment server. Furthermore, the method may include updating, by the payment server in response to an authorization of the transaction determined based at least in part on the deterministic identifier for the card, the initial transaction message with authorization data, and providing the updated initial transaction message from the payment server to an egress server. The method may also include communicating a final transaction message to an authorization system for processing the transaction between the merchant and the customer based on the card data.

Abstract: A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices. Memory systems with memory modules incorporating such a command buffer and memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths.

Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Abstract: A system for controlling an information handling system is disclosed that includes a central processing unit, a memory device, a power supply and a memory speed controller configured to determine one or more system parameters of the central processing unit, the memory device and the power supply, to store a boot setting as a function of the one or more system parameters and to cause a system reboot after storing the boot setting.

Abstract: A motor for a fan, a ventilator, a pump or a compressor includes integrated motor electronics and at least one sensor unit for pressure or volume flow control. The at least one sensor unit may be a module that can be plugged onto or into the integrated motor electronics or may be at least partly integrated into the motor electronics. The motor may be an electronically commutated motor. The integrated motor electronics may be configured to supply the at least one sensor unit with energy.

Abstract: A method for dispatching input-output in a system. The system may include a centralized processing circuit, a plurality of persistent storage targets, a first input-output processor, and a second input-output processor. The method may include determining whether the first input-output processor is connected to a first target of the plurality of persistent storage targets; determining whether the second input-output processor is connected to the first target; and in response to determining that both the first input-output processor is connected to the first target, and the second input-output processor is connected to the first target, dispatching a first plurality of input-output requests, each to either the first input-output processor or the second input-output processor, the dispatching being in proportion to a service rate of the first input-output processor to the first target and a service rate of the second input-output processor to the first target, respectively.

Abstract: An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

Abstract: A secondary processor device ownership system includes a chassis that houses a plurality of devices, a secondary processing system, and a central processing system that includes an integrated switch device that is coupled to each of the plurality of devices and the secondary processing system. The central processing system is configured to provide a device ownership subsystem that configures the central processing system to own a first subset of the plurality of devices, configures the secondary processing system to own a second subset of the plurality of devices, and hides the second subset of the plurality of devices from at least one application provided by the central processing system.

Abstract: The disclosure relates to a unit for a bus system, a master/slave bus system with such units, and a method for assigning individual unit addresses for units of a bus system, wherein through the use of an enable signal, which is relayed from unit to unit, only one unit is respectively in an allocation mode in which the unit that is respectively in the allocation mode is allocated an individual unit address so that the units of the bus system can each be allocated with the unique individual address one after the other in the sequence of their cabling.

Abstract: A method of synchronizing time between a host device and a storage device is provided. The method includes: identifying, by the storage device, a time synchronization interval; notifying the time synchronization interval from the storage device to the host device; providing host time information from the host device to the storage device during the time synchronization interval; and synchronizing, by the storage device, time information of the storage device with the host time information.

Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. A first tile in a first node can include a processor with a processor output and a first register network configured to receive information from the processor output and information from one or more of the multiple other tiles in the first node. In response to an output instruction and a delay instruction, the register network can provide an output signal to one of the multiple other tiles in the first node. Based on the output instruction, the output signal can include one or the other of the information from the processor output and the information from one or more of the multiple other tiles in the first node. A timing characteristic of the output signal can depend on the delay instruction.

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Abstract: Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Abstract: A communication device for connection with a power source and a host device is provided. The communication device comprises a device controller and a converter circuit. The device controller is adapted for data communication with the host device and the converter circuit is configured to provide a virtual device ground at least to the device controller, so as to compensate a ground potential difference between the host device and the communication device.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.

Abstract: In one embodiment, a method includes transmitting pulse power on two wire pairs, the pulse power comprising a plurality of high voltage pulses with the high voltage pulses on the wire pairs offset between the wire pairs to provide continuous power, performing low voltage fault detection on each of the wire pairs between the high voltage pulses, and transmitting data on at least one of the wire pairs during transmittal of the high voltage pulses. Data transmittal is suspended during the low voltage fault detection.

Abstract: Systems and methods disclosed herein provide a novel solution for PCIe port bifurcation. Unlike conventional client systems, which rely on resistors, jumpers or DIP switches, the disclosed systems and methods enable PCIe ports to be configured in accordance with a plurality of user-selectable PCIe bifurcation settings provided within a boot setup menu. When an “Auto” setting is selected in the boot setup menu, the disclosed systems and methods enable PCIe ports to be: (a) configured in accordance with the bifurcation requirements of the PCIe adapter card(s) connected to the PCIe ports, and (b) automatically reconfigured when bifurcation requirements change. Unlike conventional server systems, which require the user to enter BIOS setup and manually change the PCIe bifurcation settings provided in the BIOS setup menu, the systems and methods disclosed herein enable PCIe ports to be automatically reconfigured, when bifurcation requirements change, without user intervention.

Abstract: Embodiments herein describe a retroactive tracer that retroactively generates traces using data stored in local caches. Rather than continually generating and collecting tracing data in a distributed system (which may requires massive amounts of storage and bandwidth), the embodiments herein store tracing data in local caches corresponding to nodes in the distributed system (e.g., a service, application, virtual machine, server, network device, etc.). When an error is detected when executing a task, the retroactive tracer can broadcast a request that the nodes send any trace data they may have corresponding to that task. The tracer can then retroactively generate the trace from the collected trace data. In contrast, if a task completes without an error, the nodes delete the trace data from their local caches (i.e., the trace data is not collected by the retroactive tracer).

Abstract: A distributed database maintains a table on a first plurality of partitions. A request to restore the table to a point-in-time is received. The database determines, based on log data of the partitions, a maximum version number of an operation processed by the partitions. The log data is processed to exclude, from the restoration, operations whose transactions were started after the point-in-time, by setting the version number of those operations to be greater than the maximum version number. The log data is then applied to a second plurality of partitions, where the version number of each applied operation is less than or equal to the determined maximum version number.

Abstract: A sensing device is for sensing an operating voltage of a remote device. A communications interface receives communications signals originating from the remote device over a communications bus. A data sampler takes data readings of a communications signal at a predetermined set of timing instants defined by the sensing device. A data metric (such as a duty cycle of high and low states) is obtained from the data readings and from this 5 an operating voltage of the remote device is obtained, based on a relationship between the voltage and the data metric. The invention is based on detecting timing changes which result from voltage changes. In particular, the slope of rising and falling edges of the communications signal are influenced by the voltage level, and this in turn influences the timing of high states (1s) and low states (0s).

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit a capability or mobility mode indication to a base station. The base station may select a timing advance (TA) adjustment scheme based on the information included in the indication. The base station may select a TA adjustment scheme in which the UE autonomously adjusts a TA value; the UE adjusts the TA value after receiving a command from the base station; or the UE transmits a message to the base station including a proposed TA adjustment, and the UE adjusts the TA value after receiving an approval message from the base station. The base station may transmit a TA adjustment scheme configuration to the UE including an indication of the selected TA adjustment scheme. The UE may adjust a TA value for an uplink transmission based on applying the TA adjustment scheme.

Abstract: One embodiment provides a method, including: connecting a USB device to a secure device; provisioning, at the secure device, the USB device, wherein the provisioning comprises encrypting, using a private key, a hash value associated with a device descriptor associated with the USB device into a product field of the device descriptor: introducing the provisioned peripheral device into a client device; determining, using a processor of the client device, that the USB device is an authorized USB device, wherein the determining comprises: decrypting, using a public key that corresponds to the private key, the hash value; producing, by running a hash function on the device descriptor minus the hash value, a new hash value; and identifying that the hash value is equivalent to the new hash value; and enabling the USB device to gain access to a system of the client device. Other aspects are described and claimed.

Abstract: One example method of operation may include receiving at a managing device an indication whether a first network device is a known network device, identifying a selected network mode of operation stored in memory of the managing device, and determining whether to cancel the selected network mode of operation based on whether the first network device is a known device.

Abstract: The present disclosure is directed to an electromechanical surgical system having an end effector and an adapter assembly for selectively interconnecting the end effector and a hand-held surgical instrument. A one-wire bidirectional serial communications interface or bus extends through the end effector, the adapter assembly, and the hand-held surgical instrument. The hand-held surgical instrument includes a master circuit coupled to the bus and configured to identify or control the adapter assembly or the end effector. A power source is couplable to the bus and configured to provide power to the adapter assembly or the end effector. A first switch connects the master circuit to the bus and a second switch connects the power source to the bus. A processor controls operation of the hand-held surgical instrument. The controller has a wake-up pin connected to the bus and is configured to receive a presence pulse from the adapter or end effector.

Abstract: Provided are techniques for selecting a disconnect by training a machine learning module. A machine learning module is provided that receives inputs and produces an output. The output produced from the machine learning module based on the inputs for the first I/O operation and an estimated amount of time to acquire resources for a first I/O operation is determined. An actual amount of time to acquire resources for the first I/O operation is determined. The machine learning module is retrained based on the inputs, the output, and the actual amount of time it took to acquire resources for the first I/O operation versus an estimated amount of time to acquire the resources for the first I/O operation. The retrained machine learning module is used to select one of disconnect from a channel, the logical disconnect from the channel, or the physical disconnect from the channel for a second I/O operation.

Abstract: A system for controlling an information handling system is disclosed that includes a central processing unit, a memory device, a power supply and a memory speed controller configured to determine one or more system parameters of the central processing unit, the memory device and the power supply, to store a boot setting as a function of the one or more system parameters and to cause a system reboot after storing the boot setting.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A system for providing policy-controlled communication between a plurality of different cloud computing environments includes a user interface that receives configuration settings to be applied to a plurality of first instances within a first cloud computing environment and a plurality of second instances within a second cloud computing environment. The system also includes a plurality of collectors that retrieve information from the first cloud computing environment and the second cloud computing environment, and a controller that determines policies for the plurality of first instances and the plurality of second instances as functions of the configuration settings and the information. Further, the system includes a configurator that applies the policies to the plurality of first instances and the plurality of second instances; a first tester that inspects operations of the plurality of first instances and detects violations of the policies; and an enforcer that responds to the detected violations.

Abstract: A computer-implemented method comprises receiving an index number for each of a plurality of physical processing units, each of the plurality of physical processing units communicatively coupled to each of a plurality of switch chips in a leaf-spine topology; assigning at least one of the plurality of physical processing units to a first virtual drawer by updating an entry in a virtual drawer table indicating an association between the respective index number of the at least one physical processing unit and an index of the first virtual drawer; and performing a drawer management function based on the virtual drawer table.

Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Abstract: A data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.

Abstract: Devices in an array of devices, coupled to a common SPI bus, are automatically assigned identifiers by an enumeration process. In some embodiments, the devices are coupled together in an enumeration daisy chain. The enumeration function is initiated, e.g., by a controller, with a single SPI transaction.

Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.

Abstract: A packet capture device incudes: a capture unit which captures packets that flow in a communication network at 200 Gbps; a control unit which temporarily holds the packets captured; and an interface which stores the packets temporarily held into a secondary storage device. The control unit includes: a first NUMA node including a first processor and a first memory; and a second NUMA node including a second processor and a second memory. The capture unit includes: a first capture unit which captures packets and stores the packets into a first memory; and a second capture unit which captures packets and stores the packets into a second memory.

Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.

Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.

Abstract: A data transmission method, including obtaining by a transmit end, at least two to-be-transmitted packets, determining a first interface used to transmit each of the packets in at least two interfaces of the transmit end, and determining an identifier of each of the packets that is related to the first interface, where the identifier represents an order of the first interface used to transmit each of the packets in the at least two interfaces used to send the at least two packets adding the identifier to a packet header of each of the packets and sending a packet added with the identifier to the receive end device through the first interface, so that the receive end device adjusts, based on the identifier, an order of the packet added with the identifier.

Abstract: The disclosed technologies include functionality for managing Multiple Physical Function NVMe Devices (“MFNDs”) and the physical functions (“PFs”) provided by MFNDs. For example, host devices can discover MFNDs, query the capabilities of MFNDs, and change the operating mode of an MFND between a user mode and a super administrator mode. Hosts can also utilize the disclosed technologies to create and delete individual child PFs on MFNDs. The disclosed technologies also include functionality for managing the settings associated with individual PFs of MFNDs. For example, hosts can query and modify the settings associated with individual child PFs of an MFND. The disclosed technologies also include functionality for managing the QoS provided by individual PFs of a MFND. For example, hosts can also query and modify the QoS provided by individual child PFs of an MFND.

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.