System Configuring Patents (Class 710/104)
  • Patent number: 11564172
    Abstract: A communication device for connection with a power source and a host device is provided. The communication device comprises a device controller and a converter circuit. The device controller is adapted for data communication with the host device and the converter circuit is configured to provide a virtual device ground at least to the device controller, so as to compensate a ground potential difference between the host device and the communication device.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 24, 2023
    Assignee: Microchip Technology Incorporated
    Inventor: Stefan Weiers
  • Patent number: 11496340
    Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 8, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yongyao Li, Fei Luo, Er Nie
  • Patent number: 11489528
    Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: November 1, 2022
    Assignee: Juniper Networks, Inc.
    Inventors: John Kenney, Bo Mi, Ryan Holmes
  • Patent number: 11475930
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Patent number: 11467729
    Abstract: Systems and methods for allocating memory and redirecting data writes based on temperature of memory modules in a cloud computing system are described. A method includes maintaining temperature profiles for a first plurality of memory modules and a second plurality of memory modules. The method includes automatically redirecting a first request to write to memory from a first compute entity being executed by the first processor to a selected one of a first plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the first plurality of memory modules and automatically redirecting a second request to write to memory from a second compute entity being executed by the second processor to a selected one of the second plurality of memory chips, whose temperature does not meet or exceed the temperature threshold, included in at least the second plurality of memory modules.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 11, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Raymond-Noel Nkoulou Kono, Nisha Susan John
  • Patent number: 11444791
    Abstract: In one embodiment, a method includes transmitting pulse power on two wire pairs, the pulse power comprising a plurality of high voltage pulses with the high voltage pulses on the wire pairs offset between the wire pairs to provide continuous power, performing low voltage fault detection on each of the wire pairs between the high voltage pulses, and transmitting data on at least one of the wire pairs during transmittal of the high voltage pulses. Data transmittal is suspended during the low voltage fault detection.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: September 13, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Chad M. Jones, Joel Richard Goergen, George Allan Zimmerman, Richard Anthony O'Brien, Douglas Paul Arduini, Jason Dewayne Potterf, Sung Kee Baek
  • Patent number: 11436020
    Abstract: Systems and methods disclosed herein provide a novel solution for PCIe port bifurcation. Unlike conventional client systems, which rely on resistors, jumpers or DIP switches, the disclosed systems and methods enable PCIe ports to be configured in accordance with a plurality of user-selectable PCIe bifurcation settings provided within a boot setup menu. When an “Auto” setting is selected in the boot setup menu, the disclosed systems and methods enable PCIe ports to be: (a) configured in accordance with the bifurcation requirements of the PCIe adapter card(s) connected to the PCIe ports, and (b) automatically reconfigured when bifurcation requirements change. Unlike conventional server systems, which require the user to enter BIOS setup and manually change the PCIe bifurcation settings provided in the BIOS setup menu, the systems and methods disclosed herein enable PCIe ports to be automatically reconfigured, when bifurcation requirements change, without user intervention.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 6, 2022
    Assignee: Dell Products L.P.
    Inventors: Chien Yi Juan, Che Nan Cheng, William D. Leara
  • Patent number: 11409634
    Abstract: Embodiments herein describe a retroactive tracer that retroactively generates traces using data stored in local caches. Rather than continually generating and collecting tracing data in a distributed system (which may requires massive amounts of storage and bandwidth), the embodiments herein store tracing data in local caches corresponding to nodes in the distributed system (e.g., a service, application, virtual machine, server, network device, etc.). When an error is detected when executing a task, the retroactive tracer can broadcast a request that the nodes send any trace data they may have corresponding to that task. The tracer can then retroactively generate the trace from the collected trace data. In contrast, if a task completes without an error, the nodes delete the trace data from their local caches (i.e., the trace data is not collected by the retroactive tracer).
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 9, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Khanh V. Nguyen, Bojesha Nagaraja, Aniruddh S. Dikhit
  • Patent number: 11403179
    Abstract: A distributed database maintains a table on a first plurality of partitions. A request to restore the table to a point-in-time is received. The database determines, based on log data of the partitions, a maximum version number of an operation processed by the partitions. The log data is processed to exclude, from the restoration, operations whose transactions were started after the point-in-time, by setting the version number of those operations to be greater than the maximum version number. The log data is then applied to a second plurality of partitions, where the version number of each applied operation is less than or equal to the determined maximum version number.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 2, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Rishabh Jain, Vaibhav Jain, Alexander Richard Keyes, Akshat Vig, Somasundaram Perianayagam, Stefano Stefani, Tony Petrossian, James Christopher Sorenson, Amit Gupta, Nathan Pellegrom Riley
  • Patent number: 11397197
    Abstract: A sensing device is for sensing an operating voltage of a remote device. A communications interface receives communications signals originating from the remote device over a communications bus. A data sampler takes data readings of a communications signal at a predetermined set of timing instants defined by the sensing device. A data metric (such as a duty cycle of high and low states) is obtained from the data readings and from this 5 an operating voltage of the remote device is obtained, based on a relationship between the voltage and the data metric. The invention is based on detecting timing changes which result from voltage changes. In particular, the slope of rising and falling edges of the communications signal are influenced by the voltage level, and this in turn influences the timing of high states (1s) and low states (0s).
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 26, 2022
    Assignee: SIGNIFY HOLDING B.V.
    Inventor: Hong Chen
  • Patent number: 11388690
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit a capability or mobility mode indication to a base station. The base station may select a timing advance (TA) adjustment scheme based on the information included in the indication. The base station may select a TA adjustment scheme in which the UE autonomously adjusts a TA value; the UE adjusts the TA value after receiving a command from the base station; or the UE transmits a message to the base station including a proposed TA adjustment, and the UE adjusts the TA value after receiving an approval message from the base station. The base station may transmit a TA adjustment scheme configuration to the UE including an indication of the selected TA adjustment scheme. The UE may adjust a TA value for an uplink transmission based on applying the TA adjustment scheme.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 12, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Tianyang Bai, Yan Zhou, Tao Luo, Junyi Li
  • Patent number: 11374816
    Abstract: One example method of operation may include receiving at a managing device an indication whether a first network device is a known network device, identifying a selected network mode of operation stored in memory of the managing device, and determining whether to cancel the selected network mode of operation based on whether the first network device is a known device.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 28, 2022
    Assignee: Biamp Systems, LLC
    Inventor: Christopher Pane
  • Patent number: 11374761
    Abstract: One embodiment provides a method, including: connecting a USB device to a secure device; provisioning, at the secure device, the USB device, wherein the provisioning comprises encrypting, using a private key, a hash value associated with a device descriptor associated with the USB device into a product field of the device descriptor: introducing the provisioned peripheral device into a client device; determining, using a processor of the client device, that the USB device is an authorized USB device, wherein the determining comprises: decrypting, using a public key that corresponds to the private key, the hash value; producing, by running a hash function on the device descriptor minus the hash value, a new hash value; and identifying that the hash value is equivalent to the new hash value; and enabling the USB device to gain access to a system of the client device. Other aspects are described and claimed.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: June 28, 2022
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Robert James Kapinos, Scott Wentao Li, Robert James Norton, Jr., Russell Speight VanBlon
  • Patent number: 11344359
    Abstract: The present disclosure is directed to an electromechanical surgical system having an end effector and an adapter assembly for selectively interconnecting the end effector and a hand-held surgical instrument. A one-wire bidirectional serial communications interface or bus extends through the end effector, the adapter assembly, and the hand-held surgical instrument. The hand-held surgical instrument includes a master circuit coupled to the bus and configured to identify or control the adapter assembly or the end effector. A power source is couplable to the bus and configured to provide power to the adapter assembly or the end effector. A first switch connects the master circuit to the bus and a second switch connects the power source to the bus. A processor controls operation of the hand-held surgical instrument. The controller has a wake-up pin connected to the bus and is configured to receive a presence pulse from the adapter or end effector.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Covidien LP
    Inventor: Richard Lech
  • Patent number: 11341407
    Abstract: Provided are techniques for selecting a disconnect by training a machine learning module. A machine learning module is provided that receives inputs and produces an output. The output produced from the machine learning module based on the inputs for the first I/O operation and an estimated amount of time to acquire resources for a first I/O operation is determined. An actual amount of time to acquire resources for the first I/O operation is determined. The machine learning module is retrained based on the inputs, the output, and the actual amount of time it took to acquire resources for the first I/O operation versus an estimated amount of time to acquire the resources for the first I/O operation. The retrained machine learning module is used to select one of disconnect from a channel, the logical disconnect from the channel, or the physical disconnect from the channel for a second I/O operation.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Beth A. Peterson, Lokesh M. Gupta, Matthew R. Craig, Kevin J. Ash
  • Patent number: 11321240
    Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christoph Raisch, Marco Kraemer, Carsten Otte, Jonathan D. Bradbury, David Craddock
  • Patent number: 11320885
    Abstract: A system for controlling an information handling system is disclosed that includes a central processing unit, a memory device, a power supply and a memory speed controller configured to determine one or more system parameters of the central processing unit, the memory device and the power supply, to store a boot setting as a function of the one or more system parameters and to cause a system reboot after storing the boot setting.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 3, 2022
    Assignee: DELL PRODUCTS L.P.
    Inventors: Chunge-Wei Wang, Chihchung Lin, Tse-An- Chu, Shih-Wei Yang, Yi Ling Tsai
  • Patent number: 11316713
    Abstract: A computer-implemented method comprises receiving an index number for each of a plurality of physical processing units, each of the plurality of physical processing units communicatively coupled to each of a plurality of switch chips in a leaf-spine topology; assigning at least one of the plurality of physical processing units to a first virtual drawer by updating an entry in a virtual drawer table indicating an association between the respective index number of the at least one physical processing unit and an index of the first virtual drawer; and performing a drawer management function based on the virtual drawer table.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Burkhard Steinmacher-Burow, Harald Huels
  • Patent number: 11314418
    Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: April 26, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rajesh Koul, Rodney N. Mullendore, James J. Walsh
  • Patent number: 11316741
    Abstract: A system for providing policy-controlled communication between a plurality of different cloud computing environments includes a user interface that receives configuration settings to be applied to a plurality of first instances within a first cloud computing environment and a plurality of second instances within a second cloud computing environment. The system also includes a plurality of collectors that retrieve information from the first cloud computing environment and the second cloud computing environment, and a controller that determines policies for the plurality of first instances and the plurality of second instances as functions of the configuration settings and the information. Further, the system includes a configurator that applies the policies to the plurality of first instances and the plurality of second instances; a first tester that inspects operations of the plurality of first instances and detects violations of the policies; and an enforcer that responds to the detected violations.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 26, 2022
    Assignee: Netskope, Inc.
    Inventors: Jonathan Michael Bosanac, Christopher Robert Geeringh, Jason Eggleston, Lonhyn Jasinskyj, John Sengenberger
  • Patent number: 11308021
    Abstract: Devices in an array of devices, coupled to a common SPI bus, are automatically assigned identifiers by an enumeration process. In some embodiments, the devices are coupled together in an enumeration daisy chain. The enumeration function is initiated, e.g., by a controller, with a single SPI transaction.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 19, 2022
    Assignee: Mixcomm, Inc.
    Inventors: Frank Lane, Enkhbayasgalan Gantsog
  • Patent number: 11308013
    Abstract: A data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 19, 2022
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventor: Erich Vlach
  • Patent number: 11296958
    Abstract: A packet capture device incudes: a capture unit which captures packets that flow in a communication network at 200 Gbps; a control unit which temporarily holds the packets captured; and an interface which stores the packets temporarily held into a secondary storage device. The control unit includes: a first NUMA node including a first processor and a first memory; and a second NUMA node including a second processor and a second memory. The capture unit includes: a first capture unit which captures packets and stores the packets into a first memory; and a second capture unit which captures packets and stores the packets into a second memory.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 5, 2022
    Assignee: TOYO CORPORATION
    Inventor: Keiichi Ogita
  • Patent number: 11295205
    Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Jinxia Bai, Rosario Cammarota, Michael Goldfarb
  • Patent number: 11263044
    Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 1, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Mangesh P. Nijasure, Michael Mantor, Ashkan Hosseinzadeh Namin, Louis Regniere
  • Patent number: 11256531
    Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Muruganandam Somasundaram, Jeffrey Paul Kubala, Seth E. Lederer, Jeffrey G. Chan, Jerry A. Moody
  • Patent number: 11243900
    Abstract: A data transmission method, including obtaining by a transmit end, at least two to-be-transmitted packets, determining a first interface used to transmit each of the packets in at least two interfaces of the transmit end, and determining an identifier of each of the packets that is related to the first interface, where the identifier represents an order of the first interface used to transmit each of the packets in the at least two interfaces used to send the at least two packets adding the identifier to a packet header of each of the packets and sending a packet added with the identifier to the receive end device through the first interface, so that the receive end device adjusts, based on the identifier, an order of the packet added with the identifier.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: February 8, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wenkai Ling, Jianrong Xu, Yong Liu
  • Patent number: 11238203
    Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Rameshkumar Illikkal, Ananth Sankaranarayanan, David Zimmerman, Pratik M. Marolia, Suchit Subhaschandra, Dave Minturn
  • Patent number: 11237761
    Abstract: The disclosed technologies include functionality for managing Multiple Physical Function NVMe Devices (“MFNDs”) and the physical functions (“PFs”) provided by MFNDs. For example, host devices can discover MFNDs, query the capabilities of MFNDs, and change the operating mode of an MFND between a user mode and a super administrator mode. Hosts can also utilize the disclosed technologies to create and delete individual child PFs on MFNDs. The disclosed technologies also include functionality for managing the settings associated with individual PFs of MFNDs. For example, hosts can query and modify the settings associated with individual child PFs of an MFND. The disclosed technologies also include functionality for managing the QoS provided by individual PFs of a MFND. For example, hosts can also query and modify the QoS provided by individual child PFs of an MFND.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 1, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Lei Kou, Scott Chao-Chueh Lee, Ho-Yuen Chau, Liang Yang, Chin Hwan Park, Yimin Deng
  • Patent number: 11237831
    Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: February 1, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Soujanya Narnur, Timothy David Anderson, Mujibur Rahman, Duc Quang Bui
  • Patent number: 11231940
    Abstract: An information handling system includes a non-volatile memory and a processor configured to determine whether a previous boot of the information handling system was successful while booting the information handling system. If the previous boot of the information handling system was successful, then the processor determines whether current configuration settings of the information handling system match most recent known good configuration settings. If the current configuration settings of the information handling system do not match the most recent known good configuration settings, then the current configuration settings are stored as a most recent restore point in the memory.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 25, 2022
    Assignee: Dell Products L.P.
    Inventors: Ruhull Alam Bhuiyan, Allen Chester Wynn, Carl C. McAdams, Gregory Alan Havenga, Ibrahim Sayyed
  • Patent number: 11194699
    Abstract: An example method of executing an application includes running a static analysis on the application and dependencies of the application. The example method also includes obtaining a template specifying one or more virtualized environments in which the application is executable. The example method further includes generating, based on the static analysis, a settings file specifying a set of system variables of a system, each system variable being an integration point between the application and a component of the system. The example method also includes generating, based on the settings file and the template, a set of environment configurations for the system. The example method further includes executing, by the system, the application in each environment configuration of the set of environment configurations.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 7, 2021
    Assignee: RED HAT, INC.
    Inventors: Alexander Braverman Masis, Jared Andre Wilkerson
  • Patent number: 11093369
    Abstract: A simulation system is provided for memory systems. The simulation system includes: a test device suitable for generating a test command; and a virtual device suitable for configuring at least one of multiple subsystems and a storage, each subsystem including firmware, configured for a firmware development stage, and performing a test on corresponding firmware of each configured subsystem with the storage using the test command.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Ivan Badrou, Sergei Musin
  • Patent number: 11082136
    Abstract: A method for communicating between a first system and a second system using a full-duplex synchronous serial link capable of simultaneously routing between both systems is disclosed. The data involved includes at least one message from the first system to the second, at least one message from the second system to the first, and a clock signal. The method involves the second system receiving a message and a clock signal sent by the first system, delayed and substantially in phase, the second system sends a message to the first system, the clock signal received by the second system is sent back to the first system with the message sent by the second system, and the first system receives the message sent by the second system and the sent-back clock signal, delayed and substantially in phase.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 3, 2021
    Assignee: Valeo Systemes de Controle Moteur
    Inventors: Valéry Becquet, Olivier Garot
  • Patent number: 11061694
    Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: July 13, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Shih-Hsien Wu
  • Patent number: 11032250
    Abstract: Provided is a network cabling apparatus and protective apparatus for the protected transmission of data, comprising two protective devices which are assigned to one another and can each be connected to one end of a data transmission device, each protective device having: a first interface for connection to the data transmission apparatus; a second interface for connection to a device; and a crypto unit which has a cryptographic function that can be configured in an equivalent manner on each of the assigned protective devices and which cryptographically protects the data to be transmitted.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 8, 2021
    Inventors: Rainer Falk, Steffen Fries, Stefan Seltzsam
  • Patent number: 11025810
    Abstract: A control module of an electronic device includes a control unit that recognizes modules and allocates unique addresses to the modules, and a storage unit that stores predetermined information including the unique addresses allocated to the modules. If communication is possible with a predetermined module, the control unit performs communication with the modules based on the predetermined information without updating the predetermined information. If communication is not possible with the predetermined module, the control unit updates the predetermined information to perform communication with the modules based on the updated predetermined information.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 1, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuya Miyahara
  • Patent number: 11023255
    Abstract: Methods, systems, and computer-readable storage media for receiving a configuration descriptor from configuration descriptor repository, the configuration descriptor declaring a configuration task, and providing an order of invoking two or more application programming interfaces (APIs) to respective components of the enterprise-side landscape to execute the configuration task, processing the configuration descriptor by a configuration executor of an integration services platform to automatically execute at least a portion of the configuration task by invoking the two or more APIs in the order, a response of a first API being provided as a request to a second API, and selectively indicating one of success and failure of the configuration task based on at least one response of the two or more APIs.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 1, 2021
    Assignee: SAP SE
    Inventor: Manikandan Rajasekar
  • Patent number: 11016781
    Abstract: Some example embodiments presented herein provide methods and memory modules for configuring vendor-specific registers in the memory modules to enable and/or disable vendor-specific functionality. The vendor-specific register space may be organized by a vendor-specific logic and accessed by a standard memory access command received while the memory is in a programming mode. A write command may be received from a host device to switch the memory module to a programming mode, and the memory module may be switched to the programming mode responsive to the command. A memory write command may be received from the host device involving the memory module switched to the programming mode, and a vendor-specific register may be configured based on the memory write command and the organization of the vendor-specific register indicated by the vendor-specific logic.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eldho Pathiyakkara Thombra Mathew, Yash Jajoo, Jai Babu Mahankud, Hari Babu Chimakurthy
  • Patent number: 11009930
    Abstract: A universal serial bus (USB) hub includes detection circuits for a D? and a D+ connection of a USB port and a control circuit. The control circuit is configured to disable, detection circuits, respective impedances. After disabling the respective impedances, the USB hub is further configured to detect, at the detection circuits, respective values from the D+ connection and the D? connection. The USB hub is further configured to, based upon the respective values, switch the USB port between a device port configuration and a host port configuration.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: May 18, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Jeffrey Hunt, Andrew Rogers
  • Patent number: 11005726
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system and a management controller communicatively coupled to the host system processor. The host system may include a host system processor and a device coupled to the host system processor. The management controller may be configured to provide management of the information handling system, provide a plurality of management interfaces, and provide a user interface for configuring a respective network interface affinity for each management interface to system management features supported by the management controller.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 11, 2021
    Assignee: Dell Products L.P.
    Inventors: Chandrasekhar Mugunda, Sruthi Reddy Mothukupally, Yogesh P. Kulkarni, Akkiah Choudary Maddukuri
  • Patent number: 10994718
    Abstract: A multi-master system includes a first master, a second master, and an integrated control circuit controlled by each of the first and second masters. The integrated control circuit includes a first dedicated block configured to provide a first function to the first master, a second dedicated block configured to provide a second function to the second master, and a global using block configured to provide a common function to each of the first and second masters.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 4, 2021
    Assignee: HYUNDAI AUTRON CO., LTD.
    Inventors: Hyung Min Park, Ji Haeng Lee, Dong On Jang, Won Hee Jo
  • Patent number: 10963035
    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 30, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, James Lionel Panian, Richard Dominic Wietfeldt, Mohit Kishore Prasad, Amit Gil, Shaul Yohai Yifrach
  • Patent number: 10949573
    Abstract: Embodiments of the present disclosure provide unlocking control methods and related produces. The method includes the following. A face image is collected. A first operation and a second operation are performed in parallel. The first operation is configured to detect whether the face image is a real face image. The second operation is configured to extract feature data of the face image. The feature data of the face image is matched with feature data of a preset face template when the feature data of the face image is extracted and the face image is detected to be the real face image. An unlocking operation is performed when the feature data of the face image is matched with the feature data of the preset face template.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 16, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Jian Wang, Kui Jiang
  • Patent number: 10924541
    Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: February 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, James Panian, Richard Wietfeldt
  • Patent number: 10908945
    Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 2, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Mark Landers, Martin John Robinson
  • Patent number: 10897831
    Abstract: Methods, systems, and apparatuses are described that enable the recovery of stranded power in a data center. For example, a power distribution system for recovering stranded power in a data center includes a first power distribution unit (PDU), a first busway segment that is operable to electrically connect the first PDU to a first set of server racks in a first row of server racks, a second busway segment that is operable to electrically connect the first PDU to a second set of server racks in a second row of server racks, a second PDU, a third busway segment that is operable to electrically connect the second PDU to a third set of server racks in a third row of server racks, and a fourth busway segment that is operable to electrically connect the second PDU to a fourth set of server racks in the second row of server racks.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 19, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Stephan W. Gilges, Keith A. Krueger, Robert G. Allison, Jayanthi Lakshmanan, Glen Robert Beyer, Yidian Sun, Scott T. Seaton, Daniel David Woodman
  • Patent number: 10881304
    Abstract: An exercise and communications system includes an interactive device, a remote device, and an external device, wherein the interactive device is configured to gather data relating to a user of the system and transmit the same to the remote device, and the remote device is configured to provide analyze the data and transmit a response to the interactive device, which in turn communicates the response to the user and additionally communication with an external device for retrieval of instructions, programs, and data, inter alia. An exercise and communications system facilitates communication between a plurality of users, each having an interactive device and a remote device.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: January 5, 2021
    Inventor: Richard J. Maertz
  • Patent number: 10877744
    Abstract: A read/write method and a read/write system for a FRU are provided. The read method for the FRU comprises: a chassis management module identifying an embedded processor connected to the FRU according to an ID of the FRU inputted by a user; the chassis management module transferring the ID of the FRU and a command for reading and writing the FRU to the embedded processor connected to the FRU through a serial port; the embedded processor reading the FRU and sending a reading result to the chassis management module when identifying a type of the command as read. By the present invention, a user would complete a refresh for a FRU by inputting contents in form of a string into each field to be refreshed. Moreover, the duration of refreshing a single FRU is within 30 seconds and a fast refresh for a Node FRU is achieved.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: December 29, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Zhao Chen
  • Patent number: 10855069
    Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 1, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes