Abstract: A system for controlling an information handling system is disclosed that includes a central processing unit, a memory device, a power supply and a memory speed controller configured to determine one or more system parameters of the central processing unit, the memory device and the power supply, to store a boot setting as a function of the one or more system parameters and to cause a system reboot after storing the boot setting.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A computer-implemented method comprises receiving an index number for each of a plurality of physical processing units, each of the plurality of physical processing units communicatively coupled to each of a plurality of switch chips in a leaf-spine topology; assigning at least one of the plurality of physical processing units to a first virtual drawer by updating an entry in a virtual drawer table indicating an association between the respective index number of the at least one physical processing unit and an index of the first virtual drawer; and performing a drawer management function based on the virtual drawer table.

Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Abstract: A system for providing policy-controlled communication between a plurality of different cloud computing environments includes a user interface that receives configuration settings to be applied to a plurality of first instances within a first cloud computing environment and a plurality of second instances within a second cloud computing environment. The system also includes a plurality of collectors that retrieve information from the first cloud computing environment and the second cloud computing environment, and a controller that determines policies for the plurality of first instances and the plurality of second instances as functions of the configuration settings and the information. Further, the system includes a configurator that applies the policies to the plurality of first instances and the plurality of second instances; a first tester that inspects operations of the plurality of first instances and detects violations of the policies; and an enforcer that responds to the detected violations.

Abstract: Devices in an array of devices, coupled to a common SPI bus, are automatically assigned identifiers by an enumeration process. In some embodiments, the devices are coupled together in an enumeration daisy chain. The enumeration function is initiated, e.g., by a controller, with a single SPI transaction.

Abstract: A data acquisition system includes a receptacle and a data acquisition device. The receptacle has a housing, sensor inputs to receive data signals from sensors coupled to an object, and a rib to block insertion of a standard Universal Serial Bus (USB) plug and facilitate insertion of a modified USB plug having a slot that mates with the rib. The data acquisition device includes circuitry to receive, store and process data, a USB plug having pins operatively coupled to the circuitry, a first subset of pins configured to receive data signals from the receptacle and a second subset of pins configured to support standard USB communication with USB-compliant devices, and a slot formed in the USB plug such that the slot facilitates interconnection of the USB plug both with standard USB-compliant devices and with the receptacle, the slot mating with the rib to facilitate interconnection.

Abstract: A packet capture device incudes: a capture unit which captures packets that flow in a communication network at 200 Gbps; a control unit which temporarily holds the packets captured; and an interface which stores the packets temporarily held into a secondary storage device. The control unit includes: a first NUMA node including a first processor and a first memory; and a second NUMA node including a second processor and a second memory. The capture unit includes: a first capture unit which captures packets and stores the packets into a first memory; and a second capture unit which captures packets and stores the packets into a second memory.

Abstract: A neural processing unit (NPU) is described. The NPU includes an NPU direct memory access (NDMA) core. The NDMA core includes a read engine having a read buffer. The NDMA core also includes a write engine having a write buffer. The NPU also includes a controller. The controller is configured to direct the NDMA core to perform hardware memory bandwidth optimization for reading/writing NDMA data in the read buffer and/or NDMA data in the write buffer. The NDMA core is also configured to transparently combine NDMA transaction requests for a data stripe to increase local access to available tensors in artificial neural networks.

Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.

Abstract: In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.

Abstract: A data transmission method, including obtaining by a transmit end, at least two to-be-transmitted packets, determining a first interface used to transmit each of the packets in at least two interfaces of the transmit end, and determining an identifier of each of the packets that is related to the first interface, where the identifier represents an order of the first interface used to transmit each of the packets in the at least two interfaces used to send the at least two packets adding the identifier to a packet header of each of the packets and sending a packet added with the identifier to the receive end device through the first interface, so that the receive end device adjusts, based on the identifier, an order of the packet added with the identifier.

Abstract: The disclosed technologies include functionality for managing Multiple Physical Function NVMe Devices (“MFNDs”) and the physical functions (“PFs”) provided by MFNDs. For example, host devices can discover MFNDs, query the capabilities of MFNDs, and change the operating mode of an MFND between a user mode and a super administrator mode. Hosts can also utilize the disclosed technologies to create and delete individual child PFs on MFNDs. The disclosed technologies also include functionality for managing the settings associated with individual PFs of MFNDs. For example, hosts can query and modify the settings associated with individual child PFs of an MFND. The disclosed technologies also include functionality for managing the QoS provided by individual PFs of a MFND. For example, hosts can also query and modify the QoS provided by individual child PFs of an MFND.

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

Abstract: An information handling system includes a non-volatile memory and a processor configured to determine whether a previous boot of the information handling system was successful while booting the information handling system. If the previous boot of the information handling system was successful, then the processor determines whether current configuration settings of the information handling system match most recent known good configuration settings. If the current configuration settings of the information handling system do not match the most recent known good configuration settings, then the current configuration settings are stored as a most recent restore point in the memory.

Abstract: An example method of executing an application includes running a static analysis on the application and dependencies of the application. The example method also includes obtaining a template specifying one or more virtualized environments in which the application is executable. The example method further includes generating, based on the static analysis, a settings file specifying a set of system variables of a system, each system variable being an integration point between the application and a component of the system. The example method also includes generating, based on the settings file and the template, a set of environment configurations for the system. The example method further includes executing, by the system, the application in each environment configuration of the set of environment configurations.

Abstract: A simulation system is provided for memory systems. The simulation system includes: a test device suitable for generating a test command; and a virtual device suitable for configuring at least one of multiple subsystems and a storage, each subsystem including firmware, configured for a firmware development stage, and performing a test on corresponding firmware of each configured subsystem with the storage using the test command.

Abstract: A method for communicating between a first system and a second system using a full-duplex synchronous serial link capable of simultaneously routing between both systems is disclosed. The data involved includes at least one message from the first system to the second, at least one message from the second system to the first, and a clock signal. The method involves the second system receiving a message and a clock signal sent by the first system, delayed and substantially in phase, the second system sends a message to the first system, the clock signal received by the second system is sent back to the first system with the message sent by the second system, and the first system receives the message sent by the second system and the sent-back clock signal, delayed and substantially in phase.

Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.

Abstract: Provided is a network cabling apparatus and protective apparatus for the protected transmission of data, comprising two protective devices which are assigned to one another and can each be connected to one end of a data transmission device, each protective device having: a first interface for connection to the data transmission apparatus; a second interface for connection to a device; and a crypto unit which has a cryptographic function that can be configured in an equivalent manner on each of the assigned protective devices and which cryptographically protects the data to be transmitted.

Abstract: Methods, systems, and computer-readable storage media for receiving a configuration descriptor from configuration descriptor repository, the configuration descriptor declaring a configuration task, and providing an order of invoking two or more application programming interfaces (APIs) to respective components of the enterprise-side landscape to execute the configuration task, processing the configuration descriptor by a configuration executor of an integration services platform to automatically execute at least a portion of the configuration task by invoking the two or more APIs in the order, a response of a first API being provided as a request to a second API, and selectively indicating one of success and failure of the configuration task based on at least one response of the two or more APIs.

Abstract: A control module of an electronic device includes a control unit that recognizes modules and allocates unique addresses to the modules, and a storage unit that stores predetermined information including the unique addresses allocated to the modules. If communication is possible with a predetermined module, the control unit performs communication with the modules based on the predetermined information without updating the predetermined information. If communication is not possible with the predetermined module, the control unit updates the predetermined information to perform communication with the modules based on the updated predetermined information.

Abstract: Some example embodiments presented herein provide methods and memory modules for configuring vendor-specific registers in the memory modules to enable and/or disable vendor-specific functionality. The vendor-specific register space may be organized by a vendor-specific logic and accessed by a standard memory access command received while the memory is in a programming mode. A write command may be received from a host device to switch the memory module to a programming mode, and the memory module may be switched to the programming mode responsive to the command. A memory write command may be received from the host device involving the memory module switched to the programming mode, and a vendor-specific register may be configured based on the memory write command and the organization of the vendor-specific register indicated by the vendor-specific logic.

Abstract: A universal serial bus (USB) hub includes detection circuits for a D? and a D+ connection of a USB port and a control circuit. The control circuit is configured to disable, detection circuits, respective impedances. After disabling the respective impedances, the USB hub is further configured to detect, at the detection circuits, respective values from the D+ connection and the D? connection. The USB hub is further configured to, based upon the respective values, switch the USB port between a device port configuration and a host port configuration.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system and a management controller communicatively coupled to the host system processor. The host system may include a host system processor and a device coupled to the host system processor. The management controller may be configured to provide management of the information handling system, provide a plurality of management interfaces, and provide a user interface for configuring a respective network interface affinity for each management interface to system management features supported by the management controller.

Abstract: A multi-master system includes a first master, a second master, and an integrated control circuit controlled by each of the first and second masters. The integrated control circuit includes a first dedicated block configured to provide a first function to the first master, a second dedicated block configured to provide a second function to the second master, and a global using block configured to provide a common function to each of the first and second masters.

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

Abstract: Embodiments of the present disclosure provide unlocking control methods and related produces. The method includes the following. A face image is collected. A first operation and a second operation are performed in parallel. The first operation is configured to detect whether the face image is a real face image. The second operation is configured to extract feature data of the face image. The feature data of the face image is matched with feature data of a preset face template when the feature data of the face image is extracted and the face image is detected to be the real face image. An unlocking operation is performed when the feature data of the face image is matched with the feature data of the preset face template.

Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Abstract: Methods, systems, and apparatuses are described that enable the recovery of stranded power in a data center. For example, a power distribution system for recovering stranded power in a data center includes a first power distribution unit (PDU), a first busway segment that is operable to electrically connect the first PDU to a first set of server racks in a first row of server racks, a second busway segment that is operable to electrically connect the first PDU to a second set of server racks in a second row of server racks, a second PDU, a third busway segment that is operable to electrically connect the second PDU to a third set of server racks in a third row of server racks, and a fourth busway segment that is operable to electrically connect the second PDU to a fourth set of server racks in the second row of server racks.

Abstract: An exercise and communications system includes an interactive device, a remote device, and an external device, wherein the interactive device is configured to gather data relating to a user of the system and transmit the same to the remote device, and the remote device is configured to provide analyze the data and transmit a response to the interactive device, which in turn communicates the response to the user and additionally communication with an external device for retrieval of instructions, programs, and data, inter alia. An exercise and communications system facilitates communication between a plurality of users, each having an interactive device and a remote device.

Abstract: A read/write method and a read/write system for a FRU are provided. The read method for the FRU comprises: a chassis management module identifying an embedded processor connected to the FRU according to an ID of the FRU inputted by a user; the chassis management module transferring the ID of the FRU and a command for reading and writing the FRU to the embedded processor connected to the FRU through a serial port; the embedded processor reading the FRU and sending a reading result to the chassis management module when identifying a type of the command as read. By the present invention, a user would complete a refresh for a FRU by inputting contents in form of a string into each field to be refreshed. Moreover, the duration of refreshing a single FRU is within 30 seconds and a fast refresh for a Node FRU is achieved.

Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.

Abstract: A multi-endpoint device sideband communication system includes a board including a board sideband communication subsystem coupled to a connector on the board. A multi-endpoint adapter device is connected to the board via the connector, and includes an adapter sideband communication subsystem connected to the connector via a first set of adapter sideband connections, and to each of a plurality of endpoint devices included on the multi-endpoint adapter device via respective second sets of adapter sideband communication connections. The adapter sideband communication subsystem receives a first sideband communication from the board sideband communication subsystem via the connector and, based on a first sideband communication policy stored in the adapter sideband communication subsystem, provides the first sideband communication to at least one of the plurality of endpoint devices via each respective second set of adapter sideband communication connections connected to that endpoint device.

Abstract: The present invention relates to a financial device and a control method and system thereof. The financial device may comprise: one or more selection portions; and a control unit configured to process any one of a plurality of financial processes, when any one of the one or more selection portions is input.

Abstract: A system, a method, and a computer program product for secure memory implementation for secure execution of virtual machines are provided. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus transports a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is set. If the real address is in the memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.

Abstract: Systems, methods, and computer program products to perform an operation comprising identifying at least one rule for a home screen of a mobile device, wherein the at least one rule is determined based on a current location of a mobile device, identifying a modification for a first object displayed on the home screen of the mobile device, wherein the modification is associated with the at least one rule and the current location of the mobile device, applying the modification to the first object, and outputting the home screen on the mobile device, wherein the outputted home screen includes the modified first object.

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

Abstract: A first device requesting a second device to execute a task is provided. The first device includes a communication unit configured to communicate with the second device and a processor configured to transmit content for executing the task to the second device through the communication unit as an event for requesting execution of the task is generated, and receive result data obtained as the second device executes the task through the communication unit.

Abstract: Various embodiments of the present technology may provide methods and system for communication between a host device and slave devices. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device (i.e., a master device). Each integrated circuit may provide a register to store a unique slave address, a global slave address, and an order number. The host device may communicate with each slave device individually using the unique slave address and communicate with all slave devices simultaneously using the global slave address and the order number.

Abstract: A control method for a host device includes assigning a first detection command and a first identification number to a first slave device; receiving first response information generated by the first slave device to determine the first function number of the first slave device; and determining whether the first slave device is cascaded to a second slave device. When the first slave device is not cascaded to the second slave device, the host device performs a first specific action according to the first function number, or it directs the first slave device to perform a first specific action. When the first slave device is cascaded to the second slave device, the host device assigns a second detection command and a second identification number to the second slave device and receives second response information generated by the second slave device.

Abstract: Embodiments are disclosed for methods and systems for selectively initializing elements of an operating system of a computing device. In some embodiments, a method of selectively loading hardware instances for a computing device includes receiving a notification identifying a driver for a hardware instance, initializing the driver identified in the notification, and for each hardware instance supported by the driver, determining if that hardware instance is associated with a first stage of initialization. The method may further include initializing the identified hardware instance and each other hardware instance supported by the driver that is associated with a first stage of initialization.

Abstract: A system includes the transmitter that transmits a first adjustment signal obtained based on a first parameter, detects, based on an output potential of the transmitter, a second parameter that is among values settable to the first parameter and sets the second parameter and the receiver that receives the first adjustment signal from the transmitter and acquire a second adjustment signal by adjusting the first adjustment signal based on a third parameter, sets the third parameter, counts the number of errors of the second adjustment signal based on a difference between the second adjustment signal and the test pattern, determines, based on the number of errors of the second adjustment signal, the second parameter to be set in the transmitter and controls the connection of the terminal resistor to the input terminal based on the second parameter.

Abstract: A computing device includes an accessory containing an option ROM, a first processor adapted to boot the computing device and to execute the option ROM, and a second processor adapted to be activated by the first processor to monitor execution of the option ROM by the first processor. The second processor is adapted to restore the first processor to a state prior to execution of the option ROM in response to the first processor becoming hung during execution of the option ROM. A computer program product includes program instructions executable by a processor to monitor execution of the option ROM by a first processor of a computing device, determine whether the first processor has become hung during execution of the option ROM, and restore the first processor to an execution environment that the first processor had prior to execution of the option ROM.

Abstract: A storage device includes a storage retaining content data, an input receiving instructions to reproduce the content data stored in the storage and a reproducer outputting the content data to an external reproducing device. The storage retains a table including identification information of the external reproducing device and a data format of the content data reproducible in the external reproducing device. The reproducer includes a notifier notifying reproduction information necessary for the external reproducing device to reproduce the content data before the content data are outputted to the external reproducing device in response to a reproduction instruction, and a data controller acquiring unique identification information for the external reproducing device when the external reproducing device is connected to the storage device and converting the content data into the data format reproducible in the external reproducing device and outputting the content data thereto.

Abstract: In one implementation, a system for providing a representation of a physical location of a port includes an identifier engine, a configuration engine, and a display engine. In an example, the identifier engine retrieves a value stored on a first memory resource located on a system board. In an example, a configuration engine identifies a memory resource location on a second memory resource that is to store physical port information using a system identifier associated with the value. In an example, a display engine causes the physical port information to be displayed.

Abstract: A three-dimensional integrated circuit has a plurality of layers disposed in a stacked relationship. Logic circuitry is embodied in a first layer of the three-dimensional integrated circuit. An input output circuit is electrically coupled to the logic circuitry and has a plurality of transistors embodied in at least two layers of the three-dimensional integrated circuit. The input output circuit has first and second input output circuitry, wherein the first input output circuitry operates faster than the second input output circuitry.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a service processor. The service processor generates a user interface on the service processor. The user interface providing access to platform specific configurations of the service processor. The service processor receives, through the user interface, an input for modifying a first configuration data item of the platform specific configurations. The service processor accordingly modifies the first configuration data item in accordance with the input.