Abstract: According to one embodiment, a data transfer device is provided. The data transfer device is configured to transfer data between a plurality of data transceivers and at least one memory having a first memory area. When one of the data transceivers has acquired an exclusive access right to the first memory area of the memory, the data transfer device stores address information corresponding to the first memory area.

Abstract: Provided herein are a storage device and a connecting seat for connecting the storage device to a host. More particularly, the storage device and the connecting seat may be used to transmit at least one SATA protocol data. The storage device comprises a PATA interface connector. The connecting seat is a PATA interface connecting seat that can be installed on a circuit board. A plurality of pins of the connector/connecting seat are defined to be in the true IDE mode and a plurality of pins of the connector/connecting seat are defined to be in the non-true IDE mode. The storage device and the circuit board with the connecting seat thereon communicate through the pins of the connector/connecting seat in the non-true IDE mode. Thereby, the manufacturing cost of the storage device or the host is lowered and the convenience is enhanced.

Abstract: A network interface controller includes a first NIC connected to a LAN and a second NIC, which can proceed to a low power consumption status, connected to the first NIC via a bus. The first NIC includes a storing unit arranged to store response history information transmitted from the second NIC, a registration determining unit arranged to determine whether the received data has been registered in the response history information when network data is received and the status of the second NIC is the low power consumption status, a transmitting unit arranged to transmit response data registered in association with the received data when the received data has been registered, and an activation signal transmitting unit arranged to transmit an activation signal to the second NIC when the received data has not been registered.

Abstract: A portable electronic apparatus is connected to a power supply device via a transmission line, and it includes a designated connector, a charge control circuit, and a judgment circuit. The designated connector includes five terminals respectively corresponding to five pins of a USB connector of the power supply device. When the power supply device is connected to the portable electronic apparatus, the first terminal of the designated connector is logic high, the fourth terminal of the designated connector is logic high, and the third terminal of the designated connector is logic high after pulling up the voltage level of the second terminal, the judgment circuit pulls down the voltage level of the third terminal and detects the voltage level of the third terminal so as to generate a determining result for determining a type of the power supply device.

Abstract: Methods for transmitting application specific or extended commands between a host and a memory card are disclosed. Commands for an extended card protocol are embedded in messages, along with a marker, in the data or command portion of a base card transmission protocol that is used to communicate between the host and the memory card. This allows for the transmission of application specific commands that lack a corresponding command in the base card protocol. The method can be implemented on the host side at the device driver level or the file level. In order to implement a read command in the extended card protocol, a write command in the base card protocol with an encapsulated read command in the extended protocol is first sent to a logical address, followed by a read command to the same logical address. Message set identifiers associate embedded commands and data received in separate transmissions.

Abstract: A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of transactions that occurred in the simulation of a circuit. In one aspect, the simulated signals are analyzed and converted into messages of a protocol used by the design. A combination of the messages represents a transaction. Thus, the simulated signals are then converted into a series of protocol transactions. In another aspect, a message recognition module performs the analysis of the simulated signals and converts the simulated signals into messages (e.g., request for bus, bus acknowledge, etc.). A transaction recognition module analyzes the messages and converts the messages into transactions (e.g., Read, Write, etc.). Using both the system and method the circuit description is converted into a higher level of abstraction that allows more comprehensive system-level analysis.

Abstract: Systems, methods and computer program products for generic device integration within an auto-id system. The system includes an auto-id node operable to collect data emitted by one or more automatic data acquisition devices, process the data, and make the data available to one or more enterprise applications, user interfaces, or other auto-id nodes. The auto-id node includes a device integration layer that is operable to handle communication between the auto-id node and different types of automatic data acquisition devices, device controllers, or device management systems.

Abstract: A protocol chip and a communication conversion circuit are provided in a channel adapter package that is in charge of communications with a host. The communication conversion circuit communicates with the protocol chip using a procedure that conforms to a communication protocol. The communication conversion circuit communicates with a microprocessor using a procedure that is common to multiple communication protocols. It appears from the microprocessor as though communications are being carried out with the same type of channel adapter package.

Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Abstract: In accordance with certain embodiments of the present disclosure, specifying integration points of a system-of-systems includes identifying an integration point that associates interfaces of system components. The integration point is characterized according to the identification to generate a set of attributes describing the interfaces. The integration point is specified according to the set of attributes.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: A processing unit package includes a processing unit disposed on an interposer and a device protocol translator disposed on the interposer. Through-silicon vias (TSVs) may be used to provide connections from the device protocol translator through the interposer to an external device. The device protocol translator uses a controller to control a plurality of buffers that store information received from respective information buses coupled to the processing unit, such that the processing unit information is translated according to a protocol of the external device.

Abstract: A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.

Abstract: Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In one embodiment, a peripheral, which is configured to be used with a data processing system, includes an interface to couple the peripheral to the data processing system, and at least one sensor, such as a proximity sensor, to sense a user of the peripheral, and a processor coupled to the interface and to the at least one sensor, wherein the processor configures the peripheral in response to data from the at least one sensor. The peripheral may communicate sensor data from its sensors to the data processing system, which may be a wireless PDA, and the data processing system analyzes the sensor data from its sensors and from the peripheral's sensors to decide how to configure the peripheral and/or the data processing system based on the sensor.

Abstract: In an MFP, a system controller is connected to an engine via a universal transmission line and a dedicated transmission line. When MFP is powered, the system controller sends a mode signal to the engine via the dedicated signal line. If the mode signal indicates that the power mode is to be set to a normal mode, the engine activates predetermined components. The system controller and the engine then establish communication via the universal bus. After establishing the communication, if the mode signal indicates that the power mode is to be set to a mode other than the normal mode, the system controller sends a setting command to the engine via the bus to set the power mode to any of a plurality of power-saving modes.

Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.

Abstract: The information processing system includes a plurality of information processing apparatuses connected via a network. Each apparatus includes one or more modules interconnected via a system bus. At least one of the modules is a network module having a network communication function. The information processing apparatus that inputs an external timing signal functions as a timing master, and the other information processing apparatuses function as a timing slave. The module in the timing master generates time synchronization information in the form of a packet and in the form of a command according to the timing signal and transmits the command to another module and transmits the packet to the timing slave via the network. The network module in the timing slave receives the packet from the timing master, converts the packet to the command to transmit to another module connected to the system bus and included in the timing slave.

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

Abstract: A method, system, and connector interface for transferring status information between a media player and an accessory. The method includes determining, by the accessory, when a button event occurs; and transmitting, by the accessory, at least one button status command to the media player, where the one or more button status commands comprise a context-specific button status command and at least one command associated with a particular media type. According to the method and system disclosed herein, the media player and accessory may utilize a plurality of commands in a variety of environments such as within a connector interface system environment to facilitate the transfer of status information.

Abstract: In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a logic having a first link interface to enable communication with an intellectual property (IP) logic adapted on a single semiconductor die with the logic, where the IP logic includes a second link interface coupled to the first link interface via an on-die interconnect. In this way, the IP logic can be unmodified with respect to a standalone device having the IP logic incorporated therein. Other embodiments are described and claimed.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: Techniques are disclosed relating to modifying packet data to be sent across a communication link and/or bus. Data may be modified in accordance with one or more data processing algorithms, and according to the capabilities of a destination device to receive such modified data. Lossless compression algorithms may be used on data in order to achieve a higher effective bandwidth over a particular bus or link. Encryption algorithms may be used, as well as data format conversion algorithms. One or more processing elements of a communication channel controller or other structure within a computing device may be used to modify packet data, which may be in PCI-Express format in some embodiments. A packet prefix or header may be used to store an indication of what algorithm(s) has been used to modify packet data so that a destination device can process packets accordingly.

Abstract: An image reading apparatus includes: a reading unit; a transmission unit and a limiting unit. The reading unit is configured to read a document and create image data. The transmission unit supports a plurality of transmission modes, and is configured to transmit the image data to an external apparatus using at least one selected from the plurality of transmission modes. The limiting unit is configured to limit selectable transmission modes of the transmission unit based on at least one of: a user-designated attribute of the document set by a user; a reading attribute of the reading unit; and a content of the document read by the reading unit.

Abstract: An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo.

Abstract: An embodiment of the invention provides a method for continuously detecting when a USB client device may be charged according to a BCS charging standard. Power is supplied from a USB host device to the USB client device with a first current limit. Next, the USB host device monitors data lines D+ and D? for a first part of a handshake. When the first part of the handshake is detected, a second part of the handshake is provided by the USB host device indicating that the USB client device may be changed according to the BCS charging standard. All current sources and all voltage sources that are coupled to the data lines D+ and D? are decoupled from data lines D+ and D? after the handshake is complete. After the data lines are decoupled, communication may begin between the USB host device and the USB client device.

Abstract: A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or a HDMI mode according to a mode signal. One embodiment of a method, among others, comprises: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring a dual mode DP and HDMI transmitter in accordance with the determination.

Abstract: The system provides predictive error-checking and conflict resolution by comparing data contained in cognitive artifacts such as orders/instructions and reports against one another and against existing domain-specific databases, procedural and conceptual models, reasoning schemes, (in military domain specific applications, that would be terrain, weather, equipment, artillery, logistics, rules of engagement, field manuals, military doctrine, models of war games, etc) to determine their validity and effectiveness. Possible situations, states, or conditions arising from inferred actors' intent are recognized through expert systems analysis and trigger information exchanges. The system further advance Intention Awareness by enabling users to view information corresponding to the applicable environment obtained from external application systems across interoperability bridge. Through its graphical user interface the system allow users to graphically visualize and communicate their intent.

Abstract: Technologies are provided herein for multiple platform support in a computer system firmware. A firmware is built for each hardware platform to be supported. At built time of the firmware for each platform to be supported, an instance of platform specific information is extracted from the built firmware and stored. Once the platform specific information instances have been collected for each platform to be supported, the platform specific information instances are stored in a multi-platform firmware. At run-time of the multi-platform firmware, the particular hardware platform that the multi-platform firmware is executing upon is identified. Once the platform has been identified, the particular instance of platform specific information corresponding to the identified platform is selected. The selected instance of platform specific information is then loaded and exposed for consumption by other programs.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A method and apparatus for loading and executing program code at a micro-processor are disclosed. In this method, a monitoring procedure is performed to monitor whether the micro-processor receives a loading request corresponding to a target program code. If the loading request is received, the target program code is loaded from an external memory into an internal memory of the micro-processor. The micro-processor is then rebooted to enter a first mode in which the target program code in the internal memory is to be executed.

Abstract: A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal.

Abstract: A protocol adapter for in-vehicle networks that provides diagnostics, analysis and monitoring. The protocol adapter has a pass-through feature (voltage translator)/smart mode that allows the protocol adapter to emulate older boxes. Visual indicators (LEDs) indicate the pass through feature is in operation. LEDs also indicate activity on the RS232 bus between the adapter and a PC. Single color and multiple color emitting LEDs indicate a program is being executed and identify the program that is being executed. The protocol adapter supports RP1202 and RP1210, J1708 and J1939 and J1939 Transport Layer. The protocol adapter has a Real Time Clock, Standard COMM port connection, 7-32 Volt Supply and is CE compliant. The adapter can be used wirelessly.

Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

Abstract: A method for transmitting data on a data line of a two-wire bus wherein the bus includes a data line and a clock line includes the step of pulling the data line of the two-wire bus low to define a start condition. Next, a first group of fixed data bits enabling a slave device to determine a clock signal for an address portion of a transmission of data are transmitted between a master device and the slave device. An address of the slave device is transmitted from the master device in a second group of data bits. A third group of fixed data bits enabling the slave device to determine the clock signal for a data portion of the transmission of data between the master device and the slave device are transmitted from the master device to the slave device.

Abstract: A battery management chip may include a battery management unit and a vertical bus circuit. The battery management unit can monitor a cell status of multiple cells in a battery module coupled to the battery management chip in response to an instruction from a host processor. The vertical bus circuit may transfer the instruction from the host processor to the battery management unit. The vertical bus circuit may include a first receiver, a command processor and a first transmitter. The first receiver can receive a first pair of differential input data signals. The command processor can process the first pair of differential input data signals. The first transmitter can output a first pair of differential output data signals.

Abstract: A memory card includes a first set of contacts and a second set of contacts. A first edge of the memory card includes an indentation. Insertion of the memory card into a first slot of a host device engages the first set of contacts. The indentation is configured to accept a pivoting lever arm located in the first slot when the memory card is inserted into the first slot.

Abstract: A packet communication device autonomously selects an appropriate operation mode according to a connection environment to an external device before a service of the device is started. When the device is connected to the external buses, connection interface units notify an external device discrimination unit of connection of the device. The external device discrimination unit issues a polling packet to the connected device, discriminates the connected external device on the basis of the response packet, and notifies an operation mode switching unit. The operation mode switching unit selects an operation mode conforming to a connection environment of the packet communication device to the external device and switches the operation mode of the device to the mode.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: A simple data transfer mechanism may be combined with static state bus signaling to replace a USB with a digital serial interconnect bus (DSIB). This may eliminate various pull-up/pull-down resistors required in USB, and enable the DSIB to operate with little or no leakage current when the bus is in an idle state, or data transmission state. All required functionality may be implemented using only two signal pins. The DSIB may also enable silicon solutions for high speed USB that do not require a PLL, since the clock may be provided by the transmission source and may thus not need to be recovered from the serial data stream. The DSIB may provide an easy reuse mechanism for USB silicon by enabling a designer to remove the analog PHY and replace it with a serial digital I/O transfer mechanism, while retaining the IP's USB timers, and other protocol specific features.

Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: Disclosed is a field device that transmits and receives data via a fieldbus in accordance with any of a plurality of communication protocols. The field device includes: a control section to give an instruction on a communication protocol to be used for transmitting or receiving data via the fieldbus; and a fieldbus controller including a transmitting and receiving section to transmit and receive data in accordance with any of the plurality of communication protocols, and a switching section to switch between the communication protocols to be used by the transmitting and receiving section based on the instruction from the control section.

Abstract: A method for transferring management data between processors over an Input/Output (I/O) bus system (232) includes receiving the management data at a managing processor (212) from a managed host processor (202) over the I/O bus system; and storing the management data in an addressable memory (304) of an I/O bus interface device (218) of the managing processor (212).

Abstract: A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.

Abstract: Handshaking circuits are provided in a communications cable and in a device operable to be mated with the communications cable. Before a device can utilize the power supply signal of such a communications channel, the two handshaking circuits must sufficiently identify one another over a power supply signal with a decreased voltage. The decreased voltage allows for a cable plug to be provided with a safe, protected power that cannot cause harm to a human. The decreased voltage also reduces the chance that a device can receive a primary power supply signal from the cable before the device sufficiently identifies itself. Accordingly, a laptop may be connected to a portable music player, but the voltage of the power supply signal provided by the laptop to the cable may be decreased on-cable until the handshaking circuit of the portable music player sufficiently performs a handshaking operation with a on-cable handshaking circuit.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.