Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Abstract: Systems and methods for multi-protocol serial communication interfaces are described. One example system includes an interface module including a buffer for storing a protocol selection. The system includes a protocol module coupled to the interface module and configured for providing one or more serial communication protocols. Based on the protocol selection, one of the serial communication protocols is selected. The system also includes a serial engine module coupled to the interface module and the protocol module. The serial engine module is configured for transmitting and receiving data or commands based on the selected serial communication protocol.

Abstract: It is expected to provide a communication apparatus, relay apparatus, communication system and communication method for effectively performing a communication timing adjustment when a collision has occurred on a communication line, efficiently reducing the communication collision with reducing processing loads on each apparatus, for making each apparatus effectively perform the transmission timing adjustment, and for improving the communication efficiency. ECUs are connected to communication lines with a bus topology. A relay apparatus is connected to the communication lines, obtains a time distribution based on a number of messages transmitted to the communication lines. When the bias occurs in the transmission timings, the relay apparatus transmits an instruction message that instructs to perform the timing adjustment for messages transmitted between the ECUs. In addition, it is determined whether a message to be relayed is held.

Abstract: Embodiments of the present invention are directed to a scalable wireless bus for intra-chip and inter-chip communication. The scalable wireless bus includes a plurality of wireless-enabled components (WECs). In an embodiment, the scalable wireless bus may have at least one of the number of links among WECs and the capacity of said links adapted based on one or more factors. For example, the number of links and the capacity of the links may be adapted according to one or more of, among other factors, expected activity level over the wireless bus, desired power consumption, delay, and interference levels.

Abstract: In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed.

Abstract: The disclosure provides a technique of enabling to appropriately confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus includes a master and a slave which is connected with the master by a plurality of signal lines. The master and the slave are configured to perform a handshake by changing a signal level of a respective data signal line for a period of time longer than a cycle of a clock each other.

Abstract: This specification discloses a protocol agnostic networking apparatus and method of networking. The networking apparatus receives physical layer signal through a plurality of communications ports that interface with external computing systems. A dynamic routing module interconnects the communications ports with discrete reconfigurable data conduits. Each of the data conduits defines a transmission pathway between predetermined communications ports. A management module maintains the data conduits based on routing commands received from an external computing system. The management module interfaces with the dynamic routing module to make and/or break data conduits responsive to received routing commands.

Abstract: A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner.

Abstract: A method and apparatus for establishing communication between a first device and a second device. In the method, the second device recognizes a mark representing the first device to establish communication with the first device, and establishes communication with the first device, based on information included in the mark.

Abstract: A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described.

Abstract: A method and system for network interface naming is described.

Abstract: A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system.

Abstract: An intelligent serial interface circuit in accordance with one embodiment of the invention can include a first communication interface circuit for enabling a first communication protocol. The intelligent serial interface circuit can also include a second communication interface circuit for enabling a second communication protocol. Furthermore, the intelligent serial interface circuit can include a detector circuit coupled to the first communication interface circuit and the second communication interface circuit. The detector circuit can be for automatically detecting a factor that indicates automatically enabling the first communication interface circuit and automatically disabling the second communication interface circuit. The detector circuit can be for detecting a coupling of a pin of the first communication interface circuit that is not used by the second communication interface circuit.

Abstract: A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period.

Abstract: A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: A control unit for controlling or regulating a component, including a processing arrangement for controlling or regulating the component for connecting the control unit to a bus for communicating with a further control unit; an application tool port for connecting the control unit to an application tool for communicating with the control unit; and a connecting arrangement for connecting the application tool port and the bus port so that the application tool is able to communicate via the bus port, and a bus, a motor vehicle, a method, an application tool, and computer program products.

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: A battery pack has first and second battery terminals, plural battery cells each with a battery element, a cell supervisor electrically connected to the battery element, and a communication section to communicate with the cell supervisor. The battery elements are connected serially between the first and second battery terminals. Bus interfaces are arranged in alternating fashion with the battery cells to define a daisy chain bus, each such bus interface being configured for signal communication, the interfaces respectively connecting the communication sections of two adjacent battery cells. A battery manager communicates with the battery cells via the daisy chain bus. The battery manager sends a command message to the battery cells using a through mode protocol, and each battery cell sends at least one of a confirmation message and a service request to the battery manager using a shift mode protocol.

Abstract: A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel.

Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a data packet for communication along an interconnect and to transmit the data packet. This data packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: A wireless device is provided. The wireless device has a processor for controlling operation of the wireless device; a first input device coupled to the processor for accepting an input; at least one display device coupled to the processor for communicating an output to the user; a communications subsystem coupled to the processor for communicating with a communications network; a universal serial bus (USB) storage device connected to a USB port of the wireless device; a memory coupled to the processor; and a storage device coupled to the processor. The wireless device includes a USB/network handling module resident in the memory for execution by the processor.

Abstract: Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In one embodiment, a peripheral, which is configured to be used with a data processing system, includes an interface to couple the peripheral to the data processing system, and at least one sensor, such as a proximity sensor, to sense a user of the peripheral, and a processor coupled to the interface and to the at least one sensor, wherein the processor configures the peripheral in response to data from the at least one sensor. The peripheral may communicate sensor data from its sensors to the data processing system, which may be a wireless PDA, and the data processing system analyzes the sensor data from its sensors and from the peripheral's sensors to decide how to configure the peripheral and/or the data processing system based on the sensor.

Abstract: Controller area network (CAN) communications apparatus and methods are presented for CAN flexible data rate (CAN FD) communications in a mixed CAN network with CAN FD nodes and one or more non-FD CAN nodes in which a CAN FD node wishing to transmit CAN FD frames sends a first predefined message requesting the non-FD CAN nodes to disable their transmitters before transmitting the CAN FD frames, and thereafter sends a second predefined message or a predefined signal to return the non-FD CAN nodes to normal operation.

Abstract: Embodiments of the present invention provide a method, an apparatus, and a system for performing time synchronization on PCIE (PCI Express, peripheral component interconnect express) devices. The method mainly includes: a PCIE device receiving, through a hardware interface, a time synchronization signal sent from a clock source device; parsing, by the PCIE device, the time synchronization signal to obtain clock information carried in the time synchronization signal, and using the clock information as a clock of the PCIE device. The PCIE devices are supported to access a synchronous network, and the PCIE devices are supported to be used as a global clock source.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: A motor vehicle has a FlexRay bus. Values for operating parameters are stipulated for the FlexRay bus. The value for at least one selected operating parameter is obtained from an optimization method in which, on the basis of prescribed messages to be transmitted via the FlexRay, a plurality of values for the at least one selected operating parameter have an allocation—associated with these values—of slots to the prescribed messages provided for them according to a predetermined rule, and a predetermined sequence of the allocation is rated according to a predetermined criterion.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

Abstract: Methods and structure are provided for provisioning a Redundant Array of Independent Disks (RAID) volume via an expander that can be used to provision a RAID volume managed by an external RAID controller. The structure includes a Serial Attached SCSI (SAS) expander. The expander comprises physical links with transceivers (PHYs) that directly couple with storage devices, a protocol target and a control unit. The control unit provisions a first RAID volume with multiple storage devices that are directly coupled with the PHYs, and is further masks the storage devices from a SAS domain, by presenting the PHYs directly coupled with the multiple storage devices as a single PHY coupled with a single logical device. The control unit is also operable to provision a portion of a second RAID volume on the logical device in response to the expander receiving a command from a RAID controller.

Abstract: In one embodiment a limited functionality link state protocol node has one or two interfaces configured to send and receive link state protocol packets. In response to receiving, by the partially-participating link state protocol node on a first interface, a particular link state protocol data unit (LSP): sending the particular LSP from a second interface of the partially-participating link state protocol node without updating the local link state database when the second interface is currently participating in the link state protocol distribution; and sending an acknowledgment of the particular LSP from the first interface when the second interface is not currently participating in the link state protocol distribution.

Abstract: A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.

Abstract: The invention relates to a bus coupler which converts a network-specific telegram arriving from an external network to an internal data telegram which transmits only the payload data from the network-specific telegram. The internal data telegram also contains at least one state information field for internal control information. The internal data telegram is transferred from the bus coupler to an internal bus system to which multiple bus users are connected in series. Each bus user connected to the internal bus system is able to monitor, in a decentralized and preferably autonomous manner, the communication quality of the lower-level bus system, and to initiate actions, depending on the implementation, on the basis of the internal control information received from the bus coupler, the internal control information generated by the particular bus user, and/or the internal control information received from the directly adjacent bus users.

Abstract: A dynamic bus clock rate adjusting method is to be executed by a bus controller and a CPU. The bus controller is coupled with a bus that is coupled with a plurality of slave devices. The method comprises the steps of: configuring the bus controller to generate, upon receipt of a request signal from one of the slave devices, an access instruction including an address from which the request signal is sent; and configuring the CPU to determine which of the slave devices the address of the access instruction corresponds so as to obtain a working clock rate thereof, and to set the bus controller to adjust an operating clock rate of the bus according to the working clock rate, and to perform the access instruction on the slave device via the bus.

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

Abstract: In an embodiment, a storage device may include a tangible non-transitory physical storage for storing information. The storage device may also include an interface. The interface may be used to receive a signal that may be associated with one of a plurality of different protocols. The signal may be received serially. The storage device may include circuitry which may be used to identify a protocol associated with the received signal. The protocol may be identified based on an attribute associated with the received signal. Alternatively or in addition to, the protocol may be identified based on information encoded in the received signal. The information encoded in the received signal may include, for example, a data header that may be associated with the protocol.

Abstract: The disclosure provides an HVAC data processing and communication network and a method of manufacturing the same. In an embodiment, a system device configured for use in the network includes a physical layer interface and a communication module. The physical layer interface is configured to interface to a data bus. The communication module is configurable to send and receive messages over the data bus via the physical layer interface. The system device also includes a non-volatile memory configured to store configuration data. The messages include a first class of messages that address the system device using only a device designator of the device, and a second class of messages that address the system device using a message ID formed from a portion of the device designator and an offset.

Abstract: An input/output connection device includes a generating section which generates an inspection packet that has a tag that uniquely identifies the packet, a transmitting section which transmits the inspection packet to the input/output device, a receiving section which receives a packet, a first determining section which determines, on the basis of a tag of the packet received by the receiving section, whether or not the received packet is a packet transmitted in response to the inspection packet transmitted by the transmitting section, and a second determining section which analyzes the received packet and determines whether or not the input/output device is normal when the first determining section determines that the received packet is the packet transmitted in response to the inspection packet.

Abstract: In a communication system, a bus allows information to be communicated thereon as signals. Each of the signals has an electrical dominant level thereon and an electrical recessive level thereon. The electrical dominant level is asserted on the bus in priority to the electrical recessive level. Each of a master node and at least one autonomous communicating slave node detects that the bus is in an idle state when the electrical recessive level on the bus is continued for a predetermined period or more, transmits a corresponding header via the bus after detection of the bus being in the idle state, and performs arbitration on the bus based on the corresponding header.

Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract: A method is included for loading a main loadable file and at least one optional loadable file during initialization of a computer system. The method includes loading a main loadable file which includes a resident portion and an input/output network interface software component. The resident portion is a utilization software component configured to use transmission protocols. The method also includes determining which optional loadable files are required to be loaded. The optional loadable files each include an optional portion. The method also includes loading the optional loadable files which contain optional portions corresponding to required protocols.

Abstract: Methods and apparatus for enabling FCS and zoning operations in an enhanced SAS expander. Features and aspects hereof provide for enhanced logic within a SAS expander to detect receipt of an SAF in a zoning capable SAS expander and to modify the SAF to correct the zone group identifier and associated CRC to enable switching among a plurality of established connection (as provided by FCS enhancement) while maintaining accurate zoning information.

Abstract: A method of controlling connection between nodes in a digital interface whereby a first node that is a master node determines a second node to be the master and controls a point-to-point connection or a broadcast connection to another node. The first node having the display device determines the second node to be the master in accordance with a user selection, and transmits a connection command of a predetermined format for transmitting a data stream to the second node. The second node determined as the master in accordance with the transmitted connection command of the predetermined format is allocated with a channel and a bandwidth from an isochronous resource manager (IRM), and performs a point-to-point connection between the second node and the first node to transit the data stream. Thus, the transmission/reception, reproduction, and control of the data stream of the program can be smoothly performed.

Abstract: An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

Abstract: A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.

Abstract: An optical memory extension architecture. A first electrical logic circuit on a first die communicates data according to a packetized, point-to-point interconnect protocol at a full data rate. A first gasket circuit is coupled to receive the data from the first electrical logic circuit. The first gasket circuit causes the data to be converted to an optical format to be transmitted at a rate that is at least double the full data rate. A second gasket circuit is coupled to receive the data in the optical format from the first gasket circuit. The second gasket circuit causes the data to be converted to an electrical format conforming to the packetized, point-to-point interconnect protocol. A second electrical logic circuit on a second die is coupled to receive the data from the first electrical logic circuit through the first gasket circuit and the second gasket circuit.