Bus Master/slave Controlling Patents (Class 710/110)
  • Patent number: 12039294
    Abstract: A processing device includes: a receiving module for receiving a configuration from a control device, wherein the configuration includes a destination address, a length, a filled value and a function type; a control module for (A) configuring an access state for accessing a slave device according to the function type and (B) comparing a counting value with the length to generate a comparison result according to the function type, determining whether data received from the slave device reaches an end to generate a determination result, or both; a reading module for reading the data according to the access state; a writing module for writing the filled value to the destination address according to information of the access state, the determination result and the comparison result; and a transmitting module for transmitting an interrupt signal to the control device according to result(s) of the determination result and the comparison result.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: July 16, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yuefeng Chen, Xuanming Liu
  • Patent number: 12041354
    Abstract: Provided is a drive apparatus including: a first drive unit group including first drive units, each for generating a magnetic field to drive a first object provided with a first lens and magnet in an optical axis direction; and a second drive unit group including second drive units, each for generating a magnetic field to drive a second object provided with a second lens and magnet in the direction. Each of the first and second drive units includes a first and second terminal connected via a clock and data signal line to a master controlling the drive unit as a slave. In at least one of the first drive units, the first and second terminals are respectively forward-connected to the clock and data signal lines. In at least one of the second drive units, the second and first terminals are respectively reverse-connected to the clock and data signal lines.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: July 16, 2024
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Keita Okada, Takahito Hara
  • Patent number: 12003346
    Abstract: Described herein are embodiments for dual-port communication and power delivery for one-wire applications. Embodiments of one-wire bridge devices are disclosed to provide a dual-port link for two one-wire masters to communicate with one another in a multi-voltage system while intermittently allowing charging voltage. The configuration may be used to set a bidirectional pass through mode that allows level shifted fast logic signals to pass through the two one-wire links. A timer may also be configurable to time-out the pass through mode from edge in-activity. Power may be derived for operation directly from one of the links, eliminating the need for an external power supply when local power is not available. When local power is available, the other one-wire link provides local access and the pass through mode. Such configurations make it easy for a two-contact solution to be both a communication channel and a power supply for battery charging.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 4, 2024
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Wuguang Liu, Stewart Merkel
  • Patent number: 11988659
    Abstract: A method of analyzing molecules using a nanopore array including a plurality of cells included on a chip is disclosed. Nanopores are caused to be formed in at least a portion of the plurality of the cells. A first physical measurement of the nanopores is evaluated. It is determined whether to cause the molecules to interact with the nanopores. At least a portion of the nanopores is caused to interact with the molecules. A second physical measurement of the nanopores that indicates a property of the molecules is evaluated. It is determined whether to cause the nanopores to be reformed so that the cells may be reused to interact with additional molecules.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 21, 2024
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: Roger J. A. Chen, David J. Fullagar
  • Patent number: 11985219
    Abstract: Provided herein is a digital communications bus suitable for automotive applications, along with bus controllers and sensors that use the bus and its associated communication methods. One illustrative sensor includes: a clock signal generator; a bus interface coupled to differential signal conductors to detect periodic synchronization pulses from a bus controller; and a controller that aligns a clock signal from the clock signal generator with the periodic synchronization pulses. The bus interface sends digital data between the periodic synchronization pulses to the bus controller using the clock signal to control symbol transitions.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: May 14, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jean-Paul Anna Joseph Eggermont, Johannes Vorenholt, Peter Hus
  • Patent number: 11977506
    Abstract: A controller enumerates a plurality of devices while operating in a daisy-chain mode of operation and then causes the devices to operate in a parallel mode of operation in which the devices are individually addressed.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 7, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: James E. Heckroth, Patrick Johannus De Bakker, Ion Constantin Tesu, Phillip M. Matthews
  • Patent number: 11968173
    Abstract: A communication system includes a first device, second devices, and a communication line providing a serial connection from the first device to the second devices to establish a communication connection. An address setting device of the communication system is configured to set addresses of the second devices. The address setting device includes a communication controller. The communication controller is configured to transmit a transmission signal toward the second devices through the communication line and change at least one of an amplitude or a frequency of the transmission signal, and associate the addresses of the second devices with connection precedence of the second devices to the first device based on a reception signal received through the communication line.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 23, 2024
    Assignee: Daikin Industries, Ltd.
    Inventors: Hiroshi Doumae, Shin Higashiyama, Hiroki Ueda
  • Patent number: 11962425
    Abstract: A master communication device of this communication system comprises: a generation unit that generates transmission data consisting of consecutive data to all slave communication devices following one header; and a transmission unit that transmits the transmission data generated by the generation unit at the fastest cycle, among communication cycles requested by the plurality of slave communication devices. Each of the plurality of slave communication devices of the communication system comprises: a storage unit that adds information indicating reliability to data received from the master communication device and stores the same; a comparison unit that compares the reliability of subsequently received data and the reliability of the data stored in the storage unit; and a selection unit that selects the data stored in the storage unit if the reliability of the data stored in the storage unit is higher than the reliability of the data subsequently received by the comparison unit.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 16, 2024
    Assignee: FANUC CORPORATION
    Inventors: Teruki Nakasato, Tomomasa Nakama
  • Patent number: 11960392
    Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 16, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Dan Saad, Yaniv Shapira, Erez Izenberg
  • Patent number: 11947484
    Abstract: A universal serial bus (USB) hub with a host bridge function and a control method thereof are provided. The USB hub utilizes a host bridge controller to connect two upstream ports so that two host devices connected to the two upstream ports are capable of transmitting/receiving data each other synchronously, thereby increasing usage convenience and flexibility and making full use of the tow upstream ports.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 2, 2024
    Assignee: GENESYS LOGIC, INC.
    Inventor: Wei-te Lee
  • Patent number: 11947478
    Abstract: A method for programming and controlling of a plurality of slave devices serially connected in a daisy chain configuration using a master device includes assigning a unique slave address to each slave device in the plurality of slave devices by sending an initialization data packet from the master device serially through the plurality of slave devices; storing, in each of the plurality of slave devices, the assigned slave address; defining a data packet; and transmitting the data packet serially to one or more of the plurality of slave devices. The data packet has a target slave address, a read/write command, a start address, and optionally a register address and an increment value.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 2, 2024
    Assignee: SCT LTD.
    Inventors: Shang-Kuan Tang, Eric Li, Jim Wickenhiser
  • Patent number: 11942962
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anand Kumar G, Srinivasa Chakravarthy
  • Patent number: 11928065
    Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. A selection line for each one of the slave devices couples the master device with a respective slave device and is dedicated to selection by the master device of the respective slave device for communication over the shared data communication bus. Each of the slave devices is able to send an interrupt request to the master device over the respective selection line to be served by the master device initiating a communication over the shared data communication bus, each selection line thereby being a bidirectional communication line between the respective slave device and the master device.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 12, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Eyuel Zewdu Teferi, Alessandra Maria Rizzo Piazza Roncoroni
  • Patent number: 11929848
    Abstract: A device for coupling a fieldbus to a local bus for connection to at least one data bus subscriber, the device comprising a first unit that is connectable to the fieldbus and is adapted for sending and receiving data via the fieldbus; a second unit that is connectable to the local bus and is adapted for sending and receiving data via the local bus in at least one data packet; a data management unit that is connected to the first unit and the second unit, wherein the data management unit is adapted for transferring first symbols from data received via said first unit to said second unit in a sequence-dependent manner; and wherein the second unit is adapted to send at least one data packet including the first symbols on the local bus. In addition, a corresponding method for transferring data is described.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: March 12, 2024
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventors: Frank Quakernack, Hans-Herbert Kirste
  • Patent number: 11928066
    Abstract: The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 12, 2024
    Assignee: IRISTICK NV
    Inventors: Jasper Van Bourgognie, Vianney Le Clément de Saint-Marcq, Riemer Grootjans, Peter Verstraeten
  • Patent number: 11880325
    Abstract: A method includes detecting, by a coexistence controller of a system on a chip (SoC), an occurrence of a coexistence event of an SoC component; providing, by the coexistence controller, an indication of the occurrence of the coexistence event to a coexistence coordinator; and changing, by the coexistence controller, an operating point of the SoC from a current operating point to a new operating point responsive to receiving an operating point change request from the coexistence coordinator.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: January 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eli Dekel, Yaron Alpert
  • Patent number: 11880289
    Abstract: A self-detection mechanism for an IC is disclosed that determines whether the IC's internal bus is in a hanging state. An initialization sequence can be modified after a soft reset by reading data from an internal DRAM of the IC using a Direct Memory Access (DMA) controller as part of the initialization sequence. The read command is issued over the internal bus and, if the bus is hanging, the read command is not completed. Monitoring can be performed by waiting a predetermined period of time (e.g., 100 ms) to determine if the read was properly completed. If so, no further action is needed. If the read was not completed, then a hard reset is requested to be performed. Thus, an initialization sequence can be modified to run dummy transactions through the internal bus, and validate that all paths are functional.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: January 23, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Noga Smith, Ron Diamant, Saar Gross
  • Patent number: 11868291
    Abstract: A data transfer system includes a bus system; a master unit; at least one slave unit, which is allocated to the master unit and is designed to send interrupt requests directed to the master unit; and a monitor unit, which is connected between the master unit and the bus system. The monitor unit receives messages sent by the master unit and the interrupt requests sent by each slave unit allocated to the master unit. Polling messages directed by the master unit to an allocated slave unit are not forwarded by the monitor unit to the bus system until the slave unit sends an interrupt request via an interrupt request line.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 9, 2024
    Assignee: Siemens Aktiengesellschaft
    Inventors: Aharón Jesús Vargas Barroso, Christian Wagner
  • Patent number: 11870922
    Abstract: A mobile terminal of an electronic device, according to the present invention, comprises a terminal body coupled to a case, and a first display unit coupled to the case, wherein the case comprises: a first body formed to accommodate at least a portion of the terminal body; a second body in which a second display unit is arranged; a wiring part electrically connecting the first body to the second body so that data received from the mobile terminal is transmitted to the second display unit; and a wireless communication unit connected to the wiring part so as to transmit/receive a signal to/from the mobile terminal.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 9, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Jungbin Lee, Seongmi Kim, Byungkee Chae, Minhaeng Cho
  • Patent number: 11853727
    Abstract: In a method of group control and management among electronic devices, wherein the electronic devices is in communication with a control device, a projectable space instance is provided for the control device to create a workspace, wherein a control and management tool and a plurality of unified tools for driving respective electronic devices are selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance. The control and management tool realizes at least one status information of at least a first one of the electronic devices by way of the unified tools, and controls at least a second one of the electronic devices to execute at least one task corresponding to the at least one status information.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: December 26, 2023
    Assignee: ABLE WORLD INTERNATIONAL LIMITED
    Inventors: Wai-Tung Cheung, Chun-Hsiao Lin, Shih-Cheng Lan, Ho-Cheung Cheung
  • Patent number: 11855420
    Abstract: Methods and apparatus can be used to turn an existing 240 VAC or 480 VAC/600 VAC outlet into two or more time-sharing, i.e., one operating at a time, outlets. An AC switch box with two time-sharing outlets can be made with either a mechanical switch for switching which load receives power, or automatically, by a microcomputer system, for example. In the automatic AC switch box, the non-favored outlet may be typically powered on unless a load is detected at the favored/default outlet, when power to the non-favored outlet is automatically disconnected until the load is reduced or eliminated.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: December 26, 2023
    Inventors: Vincent Hung Nguyen, Trang Lan Do
  • Patent number: 11847083
    Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: December 19, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Patent number: 11843529
    Abstract: A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 12, 2023
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Eric D. Meyer, Nima Osqueizadeh
  • Patent number: 11836104
    Abstract: A bus arrangement includes a coordinator, a first subscriber having a first optical display, a second subscriber having a second optical display, a third subscriber having a third optical display, and a bus that couples the coordinator to the first, second, and third subscribers. In a standard operating phase, the first subscriber is configured to display first local information of the first subscriber on the first optical display, the second subscriber is configured to display second local information of the second subscriber on the second optical display, and the third subscriber is configured to display third local information of the third subscriber on the third optical display. The coordinator is configured to switch from a standard operating phase to a display operating phase based on detecting a fault in the first subscriber.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 5, 2023
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Franz Heller, Matthias Hansing, Olaf Boecker
  • Patent number: 11835639
    Abstract: Systems and methods for determining a location of one or more user equipment (UE) in a wireless system can comprise receiving reference signals via a location management unit having two or more co-located channels, wherein the two or more co-located channels are tightly synchronized with each other and utilizing the received reference signals to calculate a location of at least one UE among the one or more UE. Embodiments include multichannel synchronization with a standard deviation of less than or equal 10 ns. Embodiments can include two LMUs, with each LMU having internal synchronization, or one LMU with tightly synchronized signals.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Felix Markhovsky, Truman Prevatt, Russ Markhovsky
  • Patent number: 11829220
    Abstract: The present disclosure discloses a power management circuit, a chip and an upgrade method therefor, and a server. In the circuit, one terminal of a micro controller unit is connected to a control board and a processor of the chip, and the other terminal of the micro controller unit is connected to a power management integrated circuit unit, a voltage conversion unit, and a voltage regulator unit. The micro controller unit receives operation instructions sent by the control board and the processor, stores the operation instructions, reads a power-on/off operation instruction in the operation instructions that is sent by the control board, and sends the power-on/off operation instruction to the power management integrated circuit unit to enable the power management integrated circuit unit performs corresponding control on the voltage conversion unit and the voltage regulator unit to complete a power-on/off operation on the processor.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: November 28, 2023
    Assignee: SOPHGO TECHNOLOGIES LTD.
    Inventors: Chao Wei, Taiqiang Cao
  • Patent number: 11829318
    Abstract: A handshake protocol circuit, a chip and a computer device. In the present handshake protocol circuit, according to level signals of a first protocol signal input end, a first protocol signal output end, a second protocol signal input end and a second protocol signal output end, a control circuit controls a data storage circuit to store and output operation data, which is equivalent to caching the operation data by the storage circuit. Therefore, when the number of functional module circuits is relatively large, the continuity of combination logic of handshake protocols between the module circuits is relatively reduced, thereby relatively ensuring the normal communication of data between the functional module circuits. In addition, the present disclosure further provides a handshake protocol chip and a computer device.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 28, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Hongliang Wang, Qi Mou, Fancheng Meng
  • Patent number: 11824658
    Abstract: The wireless channel of the wireless communication system is selectively disrupted or interfered with based on the logical states of the data to be transmitted by an electronic device having no wireless data signal transmitting circuitry. A host device transmits a query packet which includes a header and a series of sub-frames to be received by a receiving device. As each sub-frame is transmitted, the electronic device can selectively disrupt the wireless channel by changing its characteristics such that the receiving device can no longer decode that sub-frame based on channel estimation from the header of the frame. Wireless channel disruption occurs in response to a specific state of the bit of data of a message to be communicated by the electronic device. The receiving device then issues a status reply to the host device indicating which sub-frames are decodable and which sub-frames are undecodable based on the initial channel estimation. The host device decodes the status reply to extract the message.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: November 21, 2023
    Inventors: Ali Abedi, Timothy Benedict Brecht, Farzan Dehbashi, Mohammad Hossein Mazaheri Kalahrody, Omid Salehi-Abari
  • Patent number: 11809346
    Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: November 7, 2023
    Assignee: Amtel Corporation
    Inventors: Guillaume Pean, Vincent Debout, Marc Maunier
  • Patent number: 11809365
    Abstract: A data transmission method, applicable between a first USB host and a second USB host, is provided. The first USB host includes a host software, and the second USB host includes a controlled software. The data transmission method includes the following steps. A connection is established from a USB hub to the first USB host via its first USB port. A connection is established from a USB hub to the second USB host via its second USB port. A first USB transmission channel between the first USB host and the second USB host is provided by the USB hub. A first data is transmitted to the USB hub via the first USB port and the first data is transmitted to the second USB host through the first USB transmission channel of the USB hub via the second USB port by the host software and the controlled software.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: November 7, 2023
    Assignee: GENESYS LOGIC, INC.
    Inventor: Wei-Te Lee
  • Patent number: 11789896
    Abstract: A flexible processor includes (i) numerous configurable processors interconnected by modular interconnection fabric circuits that are configurable to partition the configurable processors into one or more groups, for parallel execution, and to interconnect the configurable processors in any order for pipelined operations, Each configurable processor may include (i) a control circuit; (ii) numerous configurable arithmetic logic circuits; and (iii) configurable interconnection fabric circuits for interconnecting the configurable arithmetic logic circuits.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: October 17, 2023
    Assignee: STAR ALLY INTERNATIONAL LIMITED
    Inventor: Wensheng Hua
  • Patent number: 11789108
    Abstract: Systems and methods for determining a location of one or more user equipment (UE) in a wireless system can comprise receiving reference signals via a location management unit having two or more co-located channels, wherein the two or more co-located channels are tightly synchronized with each other and utilizing the received reference signals to calculate a location of at least one UE among the one or more UE. Embodiments include multichannel synchronization with a standard deviation of less than or equal 10 ns. Embodiments can include two LMUs, with each LMU having internal synchronization, or one LMU with tightly synchronized signals.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 17, 2023
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Felix Markhovsky, Truman Prevatt, Russ Markhovsky
  • Patent number: 11775463
    Abstract: A system-on-chip including: a first slave having a first safety level; a second slave having a second safety level; a first master having a third safety level, the first master outputs a first access request for the first slave and a second access request for the second slave; a safety function protection controller that outputs first attribute information corresponding to the first safety level, second attribute information corresponding to the second safety level, and third attribute information corresponding to the third safety level; and an interconnect bus that receives the first, second and third attribute information, transfers the first access request to the first slave when it is determined that the third safety level is higher than or equal to the first safety level, and blocks the second access request when it is determined that the third safety level is lower than the second safety level.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byungtak Lee, Hee-Seong Lee, Myungkyoon Yim
  • Patent number: 11768529
    Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 26, 2023
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Siva Naga Subrahmanya Saratchandra Bhagavathula, Rakesh Kumar Polasa, Kaustubh Kumar, Munnangi Sirisha
  • Patent number: 11755243
    Abstract: An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: September 12, 2023
    Assignee: Arm Limited
    Inventor: Simon John Craske
  • Patent number: 11749374
    Abstract: A memory device includes a memory cell array, a data accessing circuit, a data bus inversion calculator, a multiplexer, and an output result judging circuit. The data accessing circuit performs a data write-in operation or a data read-out operation on the memory cell array. The data accessing circuit reads read-out data from the memory cell array. The data bus inversion calculator generates inversion indication data according to the read-out data. The multiplexer outputs the inversion indication data or test data according to a mode signal. The output result judging circuit compares the read-out data with the inversion indication data or the test data to generate output information.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 5, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Tzu-Yin Wei
  • Patent number: 11720516
    Abstract: An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.
    Type: Grant
    Filed: August 15, 2021
    Date of Patent: August 8, 2023
    Assignee: APPLE INC.
    Inventors: Vadim Ostrovsky, Myunghyun Ha
  • Patent number: 11716101
    Abstract: One example discloses a multi-radio device, including: a controller configured to be coupled to a first radio that is configured to transmit a first signal, and a second radio that is configured to transmit a second signal; wherein the controller includes a detection element configured to detect a third signal generated in response to simultaneous transmission of the first and second signals; wherein the controller includes a decision element configured to modulate one or more information packets in the first and second signals in response to the third signal.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: August 1, 2023
    Assignee: NXP USA, Inc.
    Inventors: Yi-Ling Chao, Yiqing Shen
  • Patent number: 11698880
    Abstract: A system on chip including a first master circuit, a second master circuit, a routing circuit, a bridge control circuit, and a peripheral circuit is provided. The first master circuit provides a first command. The second master circuit provides a second command. The routing circuit receives the first command and the second command and provides an output command. The bridge control circuit receives the output command and stores an attribute setting value. In response to the routing circuit receiving the first command and the first command pointing to the peripheral circuit, the routing circuit uses the first command as the output command and the bridge control circuit determines whether attribute information of the output command matches the attribute setting value. In response to the attribute information of the output command matching the attribute setting value, the bridge control circuit provides the output command to the peripheral circuit.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 11, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Shun-Hsiung Chen
  • Patent number: 11689044
    Abstract: A battery with a battery management system is capable of charging the battery with recaptured energy from an energy regeneration device. The battery management system charges the battery with the energy regeneration device if the output voltage from the energy regeneration device is larger than the charging voltage of the battery.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 27, 2023
    Assignee: Lithium Power Inc.
    Inventors: Zhixian Zhang, Chit Fung So
  • Patent number: 11687485
    Abstract: A system for monitoring inter-integrated circuit (12C) communication includes a power supply, a battery backup unit, an 12C serial clock line (SCL) coupled between the power supply and the battery backup unit, an 12C serial data line (SDA) coupled between the power supply and the battery backup unit, and a controller. A first monitor line is coupled between the controller and the 12C serial clock line, and a second monitor line is coupled between the controller and the 12C serial data line. The controller is configured to monitor a digital communication transmitted on the 12C serial clock and data lines between the power supply and the battery backup unit, interpret a message included in the monitored digital communication, and perform a control function according to the interpreted message.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: June 27, 2023
    Assignee: Astec International Limited
    Inventor: Donald Cedrick Ongyanco
  • Patent number: 11688435
    Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Peter Mayer, Wolfgang Anton Spirkl, Michael Dieter Richter, Martin Brox, Thomas Hein
  • Patent number: 11665846
    Abstract: A modular I/O system for an industrial automation network includes a network adapter including first and second adapter modules, wherein each adapter module is configured for connection with an industrial network. The I/O system further includes a first I/O device with first and second I/O modules each configured for operative connection to a controlled system for input/output of data with respect to the controlled system. The I/O system further includes first and second independent backplane data networks that connect each of the first and second adapter modules to each of the first and second I/O modules. The network adapter includes first and second removable backplane network switches and the first I/O device includes third and fourth removable backplane network switches that establish the backplane networks. The backplane network switches can be Ethernet gigabit switches.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 30, 2023
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Daniel E. Killian, Sivaram Balasubramanian, Kendal R. Harris, Chandresh R. Chaudhari
  • Patent number: 11663156
    Abstract: A system can include a serial, full-duplex, synchronous peripheral communication interface composed of four communication lines that communicatively couple a host processor to an optical sensor, the four communication lines including: a clock (CLK) line; a chip select (CS) line; a host output (MOSI) line; and a sensor output (MISO) line, the MISO line operating according to the following conditions when the CS line is selected: provide a service register data indicating when one or more predetermined conditions have occurred prior to receiving any commands from the host processor; provide a state register data defining the one or more predetermined conditions that occurred; and in response to receiving a command from the host processor received after the service register data and state register data is provided, the command requesting input device operational data, provide the operational data to the host processor.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: May 30, 2023
    Assignee: Logitech Europe S.A.
    Inventors: François Morier, Berni Joss
  • Patent number: 11650754
    Abstract: Embodiments of the present disclosure provide a data accessing method, a device and a storage medium. The method includes: obtaining a first accessing request and a second accessing request for a storage device; loading first data associated with the first accessing request from a source device to a pre-allocated buffer area with a size same as a size of a single physical storage block of the storage device; determining a first part of the second data when the first size of second data associated with the second accessing request is greater than or equal to the second size of an available space of the buffer area, a size of the first part being the same as the second size; and providing the first data and the first part to a target device associated with the first accessing request and the second accessing request.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: May 16, 2023
    Assignee: KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
    Inventors: Zihao Liang, Jian Ouyang
  • Patent number: 11609877
    Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) without a chip select pin are disclosed. A communication link between a host and a device may include a clock line, a host to device line, and a device to host line. The host may signal a start or stop condition using the clock line and the device may send an acknowledgment of the host's signaling through the device to host line. Once acknowledgment is made, the host may then signal on the host to device line using a protocol such as SPI.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: March 21, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kishalay Haidar, Amit Gil
  • Patent number: 11611452
    Abstract: A gateway for data communication in a vehicle includes: a first communication interface, configured to use a first communication protocol; and a second communication interface configured to use a second communication protocol. The gateway is configured to transmit data from the first to the second communication interface and to transmit data from the second communication interface to the first communication interface. The gateway further includes a media converter configured to convert quality of service information from the first to the second communication protocol and from the second to the first communication protocol.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 21, 2023
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Christoph Arndt, Stefan Brunner, Helge Zinner
  • Patent number: 11584565
    Abstract: The collapsible container is constructed from semi-rigid to rigid wall panels, such as eight panels, that are held together by fasteners that allow the wall panels to be folded in multiple manners while remaining attached. When in use, the eight panels form side walls, a front wall, a rear wall, and a bottom floor of a basket or container that are attached and rigid. The rigid walls and floor of the container secures, holds, and supports items within the container. When fully opened and ready for use, the bottom panels of the floor are connected to the side wall panels by at least one rigid hook shaped fastener, including two fasteners. When fully collapsed, the eight rigid panels fold so that all eight panels are stacked immediately upon one another.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 21, 2023
    Inventor: Hugh Mills Jarratt
  • Patent number: 11567882
    Abstract: A method for delivering multiple write commands is provided. The method includes: encoding data to be written and corresponding addresses in the multiple write commands to obtain encoded data and an encoded address, wherein the addresses are not sequential; generating a virtual burst write command according to the encoded data and the encoded addresses; and transmitting a virtual burst-mode start indicator and the virtual burst write command through a serial bus.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: January 31, 2023
    Assignee: Himax Imaging Limited
    Inventors: Ray Chi Chang, Chih-Yen Yang
  • Patent number: 11567895
    Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Amit Kumar Srivastava, Nobuyuki Suzuki