Abstract: A method of recovering an error in data communication according to an exemplary embodiment of the present inventive concept includes performing data communication between a first device and a second device through a data line and a clock line; detecting a communication error in the data communication when the first device is in an output mode; and in response to the detecting, outputting, by the second device, a stop signal to the data line repeatedly until the first device is in an input mode. According to exemplary embodiments, if a device stays in an output mode due to a communication error, a stop signal is repeatedly output to the device until the device switches to an input mode, whereupon the communication error can be recovered from. Thus, quality of data communication can be improved.

Abstract: Ringing on the clock line on a synchronous serial data bus limits the maximum distance between the clock transmitter and receiver. The present disclosure provides a serial transmission protocol and a synchronous serial data bus for long distance serial data transmission between the clock source and the clock receiver that tolerates ringing on the transmission lines by constructing the clock signal at the receiver end of the link.

Abstract: An apparatus for controlling appliances aboard a vehicle, including a first data processing device having a network interface that can have a vehicle network for bidirectional data transmission between the first data processing device and connected network appliances. Also provided are an input/output device, a graphics processor device connected to the screen thereof and to the first data processing device, a user interface module provided in the first data processing device and that implements a graphical user interface having pages, and at least one separate second data processing device connected to the first data processing device via a separate bidirectional data link and having a network interface for connection to a vehicle network. Via each bidirectional data link it is exclusively possible to transmit predefined data records having data of predefined data types for display on pages from the second data processing device to the first data processing device.

Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

Abstract: The disclosed invention improves the transfer efficiency of a bus transfer device. A semiconductor device includes a bus transfer device including a read data transfer path which can transfer read data having an n-bit width at a maximum. If first read data and second read data corresponding respectively to a first transaction and a second transaction have a total bit width of n bits or less, the bus transfer device can simultaneously transfer data obtained by unifying the first read data and the second read data, first transaction identification information, and second transaction identification information through the read data transfer path.

Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

Abstract: The disclosure relates to an interface circuit, method and device for state switching and belongs to the terminal technology field. Aspects of the disclosure provide a circuit for switching a device between a master state and a slave state. The circuit includes a first interface configured to couple the circuit with internal circuits of the device, a second interface configured to couple the circuit with a connector structure that is configured to couple the device with another device that is external to the device and control circuits configured to provide a first signal to the internal circuits via the first interface to switch the internal circuits from a first state to a second state, and provide a second signal via the second interface to the other device to switch the other device from the second state to the first state.

Abstract: Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial computer bus; a first master coupled to the bus; a second master coupled to the bus; a slave device coupled to the bus; a first I/O line from the first master going to the second master and the slave device; and a second I/O line from the second master going to the first master and the slave device. A bus arbitration protocol for arbitrating use of the bus restricts the masters to a single transaction each time either master becomes a bus master, and the masters are each adapted to use the I/O lines to signal to each other not to become a bus master. Numerous other aspects are disclosed.

Abstract: A method of processing a request for a service of a control plane in a computer system includes receiving the request, from a client, at a service host process executing on a software platform of the computer system; generating an operation object in the service host process that encapsulates a request/response pattern started by the request, the operation object including a plurality of fields that store a context for the request/response pattern within the service host process; determining a key based on the context stored by the plurality of fields; obtaining a rate limit associated with the key; and permitting or denying the request for the service based on whether a rate of requests targeting the service exceeds the rate limit.

Abstract: Some embodiments relate to a cellular network which facilitates transmission of messages, such as SMS or MMS messages, to/from respective user equipment (UE) devices of a user. Each of the UE devices may provide a relative priority value indicating a priority for receipt of messages relative to the other UE devices associated with the user. When a message intended for the user is received at the cellular network, the priority information associated with each of the user's at least two UE devices may be retrieved. The message may then be selectively delivered (by the cellular network) to one of the first UE device or the second UE device based on the relative values of the first priority value and the second priority value. If a delivery attempt fails to the highest priority device, the cellular network may attempt to deliver the message to the second highest priority UE device.

Abstract: An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting a remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs a co-processor request completion sequence (status update, write to flag, interrupt) included in the co-processor command.

Abstract: A control method for a first device of an inter-integrated circuit (I2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I2C system when determining that the status information of the first device matches the target status.

Abstract: A solid state drive (SSD) device includes a Peripheral Component Interconnect-Express (PCIe) interface, a non-volatile storage media, and a memory that stores code, the code including an Advanced Host Controller Interface (AHCI) controller, and a Non-Volatile Memory-Express (NVMe) controller. The SSD device is operable to select one of the AHCI controller and the NVMe controller to process data storage commands between the PCIe interface and the non-volatile storage media.

Abstract: A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the anticipated numbers of transfers extracted from the address calls of the stream of address calls with the number of transfers in the transfer batches of the stream of batches. Pairing a predetermined number of consecutive address calls of the stream of address calls with consecutive batches of the stream of batches based on the comparison.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.

Abstract: In an embodiment, a computer-implemented method for automatically updating imported information in a destination system upon a change to a corresponding module in the source system, includes, responsive to the source system detecting a change to a source module in the source system changing, where the source module corresponds to an imported module of the destination system, loading breadcrumbs in the source system corresponding to the source module. The computer-implemented method further includes determining, based on the loaded breadcrumbs, destination modules linked to the changed source module. The computer-implemented method further includes exporting changes to the destination modules at the destination system from the source system. Therefore, the data remains synchronized between the two systems as changes are made on either system.

Abstract: A content delivery network (CDN) includes a single autonomous CDN partitioned into multiple virtual CDNs, the multiple virtual CDNs being organized into a CDN hierarchy. Each virtual CDN is allocated separate physical resources. Within the CDN hierarchy, at least one parent virtual CDN has at least one child virtual CDN. A parent virtual CDN grants at least one privilege to at least one child virtual CDN.

Abstract: An optical module and a method of transmitting data in the optical module are provided in the present disclosure. According to an example, the optical module may comprise a micro controller unit (MCU) and N number of first driving chips having a same chip address. The MCU may be configured with a serial data (SDA) bus interface and N number of first serial clock (SCL) bus interfaces. Each of the N number of first driving chips may be configured with a SDA bus interface which is configured to be connected with the SDA bus interface on the MCU and a SCL bus interface which is configured to be connected with one of the N number of first SCL bus interfaces on the MCU.

Abstract: Memory systems may include a memory portion, and a controller suitable for receiving information data, generating first stage data, generating a first portion parity information, generating a second portion parity information based at least in part on the first portion parity information and the first stage data, and outputting the second portion parity information.

Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

Abstract: A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

Abstract: An electronic device coupling system includes a plurality of electronic devices and an external power supply. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device has a sequence number according to an insertion sequence, the sequence number is corresponds to all the information of local electronic device, the sequence numbers of the plurality of electronic devices are sorted according to the insertion sequence, the sequence number of the master device is a first number of the sequence, and the master device is coupleable to at least one slave device by the sequence number and all the information corresponding to the sequence number. The at least one slave device is a customized group of the master device.

Abstract: A method and system to reduce power consumption are described. The system can include a first device and a second device of a plurality of devices. The second device can be coupled to the first device via an interconnect. A serialization capability of the first device can be determined. Further, access to the second device one or more of the plurality of devices can be determined. The interconnect can be serialized based on the determined serialization capability and the determined access to the second device.

Abstract: A bicycle electrical component is basically provided with a wireless communication unit, a movable member, an electrical actuation unit and a support structure. The wireless communication unit includes a first housing and a wireless communication member that is contained within the first housing. The electrical actuation unit includes a second housing and an electrical actuator that is contained within the second housing. The electrical actuator is configured to actuate the movable member. The second housing is different from the first housing. The support structure detachably supports the wireless communication unit to the bicycle electrical component.

Abstract: A method of operating an I2C slave having an I2C clock pin and an I2C data pin is disclosed. The method includes (a) receiving a command via the I2C clock pin and the I2C data pin, (b) driving the I2C data pin to logic low for a first duration, (c) not driving the I2C data pin to logic low for a second duration, and (d) repeatingly alternating (b) and (c) until a termination event occurs. (b) and (c) are not synchronized to transitions of the I2C clock pin. Other methods and systems are disclosed.

Abstract: A method for operating a rail vehicle includes, at least to some extent, using a secondary ETCS device which travels along with the rail vehicle but is not used for its operation, if a fault occurs in a primary ETCS device. A secondary EVC takes over the role of a primary EVC and, in many applications, at least some train control functions. The advantage is that train control can, at least in some fault cases, be continued in an automated way in the case of a failure of a component of the primary ETCS device. A rail vehicle and an apparatus for the operation of a rail vehicle are also provided.

Abstract: A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

Abstract: Embodiments of a method and system are disclosed. One embodiment of a method for address decoding in a data communications system using a serial data transfer bus is disclosed. The method involves, detecting a start command from a master device of the data communications system at the serial data transfer bus, and disabling an address decoder of a slave device of the data communications system in response to the detecting the start command.

Abstract: Consistency of replicated data copies with statement-based replication is provided without requiring transaction serializability. At a subordinate replication node, a transaction start message, replicated data modification statements, and a transaction commit message are received for a next committed transaction from a master replication node, wherein the transaction start message carries a master transaction identifier, an invisibility list consisting of identifiers of other master transactions that had started and not yet committed when this master transaction started, and an earliest invisible master transaction identifier. The master transaction identifier, invisibility list, and earliest invisible transaction identifier are mapped to subordinate transaction identifiers to preserve an order of transaction identifiers from the master replication node.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a communications bus, at least one target device communicatively coupled to the communications bus, and a plurality of master devices communicatively coupled to the communications bus and communicatively coupled to one another via a secondary arbitration connection. Each of the plurality of master devices may be configured to assert a respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate ownership of the communications bus and deassert the respective secondary arbitration signal of the master device on the secondary arbitration connection to indicate non-ownership of the communications bus.

Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.

Abstract: An advanced extensible interface 4 (AXI4) topology is provided. The topology includes a main entity, parallel sub entities comprising a first sub entity having a first functionality and a second sub entity comprising parallel third sub entities having a second functionality, which is different from the first functionality, and a controllable element in series with the parallel third sub entities and an AXI4 interconnect element serially interposed between the main entity and the parallel sub entities. For a transaction issued by the main entity with an augmented address including first and second addresses, the first address is readable by the AXI4 interconnect element to select one of the first and second sub entities for transaction execution and the second address is readable by the controllable element to select one of the third sub entities for transaction execution.

Abstract: A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.

Abstract: A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.

Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Abstract: A control method executed by an information processing device including a memory configured to store information on a plurality of temporary routes set for each kind of service, the control method includes receiving a routing request from a switch among a plurality of switches; extracting, from the memory, a temporary route corresponding to a service related to the routing request when it is determined that processing congestion of the information processing device occurs; setting the extracted temporary route for one or more related switches among the plurality of switches; determining a route corresponding to the service, based on a predetermined condition of the service, when it is determined that the processing congestion of the information processing device has subsided; and setting the determined route for the one or more related switches among the plurality of switches.

Abstract: A data processing system having a master device and a plurality of slave devices uses interconnect circuitry to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi-transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction. Transaction requests are then issued from the request distribution circuitry to each determined slave device to identify which transactions need to be performed by each slave device.

Abstract: This monitoring system for photovoltaic power generation includes: a first to n-th power collecting systems each for supplying a power conditioner with collected outputs from plural photovoltaic panels via a connection box; slave devices provided for connection boxes respectively belonging to the first to n-th power collecting systems, each slave device collecting measurement information about power generation and transmitting the collected measurement information by use of a direct current electrical path of the power collecting system thereof; a master device provided at a power collection end on an inlet side of the power conditioner to obtain the measurement information; a system selection unit for selecting one power collecting system upon reception of a selection signal from the master device and causing power line communication to be performed by use of a direct current electrical path of the selected power collecting system; and a monitoring device connected to the master device.

Abstract: A LIN communication system includes a master controller, and at least one slave controller connected to the master controller via local interconnect network (LIN) communication. The master controller allows the at least one slave controller to enter a sleep mode in a normal situation through a sleep mode message of an unconditional frame provided via the LIN communication and checks a failure state of the at least one slave controller in an abnormal situation.

Abstract: Wearable electronic apparatus providing sensory feedback is provided. The wearable electronic apparatus has master beads that can power slave beads. The beads have electronic circuitry enabling visual, auditory or haptic feedback to be initiated by the master beads. Master beads of one unit of a wearable electronic apparatus communicate with master beads of another unit of another apparatus. In the presence or proximity of an authorized apparatus, the master bead causes the slave beads to provide a user with sensory feedback.

Abstract: A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at least one serial bus interface to interface with a serial bus, and a processing unit that accesses via the at least one serial bus interface, master data propagating from a master device along the serial bus. The processing unit stores, in the storage device, at least one of timing and phase data related to clock pulses associated with the master data, and a phase relationship between the clock pulses and at least one of the master data and return data propagating from a slave device in response to the master data.

Abstract: Disclosed herein is a power supply device including: a position detection signal output section configured to output a position detection signal to a line allowing a current flow in only one direction in response to an order to output the position detection signal from a power supply managing device connected to a bus line including the line; a position detection signal detector configured to detect the position detection signal that is output from another device and flows through the line; and a position detection signal responder configured to respond that the position detection signal is detected to the power supply managing device when the position detection signal is detected by the position detection signal detector.

Abstract: The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication.

Abstract: A system and methodology for effectively managing, without interrupting the overall system, the power and control logic of the system during the removal, insertion and programming of programmable components that control the logic. The system and methodology detect a removal of a first programmable component from its socket and switch at least one control signal from being driven by the first programmable component to being driven by the second programmable component. Upon detecting an insertion of the first programmable component into its socket, the system and methodology switch the at least one control signal from being driven by the second programmable component to being driven by the first programmable component.

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.