Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.

Abstract: A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer topology of a plurality of multiplexers. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer topology via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the endpoints.

Abstract: A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circu

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A semiconductor device capable of executing a plurality of tasks in real time and improving performances is provided. The semiconductor device comprises a plurality of processors and a plurality of DMA controllers as master, a plurality of memory ways as slave, and a real-time schedule unit for controlling the plurality of masters such that the plurality of tasks are executed in real time. The real-time schedule unit RTSD uses the memory access monitor circuit and the data determination register to determine whether or not the input data of the task has been determined, and causes the task determined to have the input data determined to have been determined to be executed preferentially.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: Systems and methods for functionality management of devices are disclosed. Multiple computing devices may be located in the same environment and/or space and at least two of those computing devices may be configured to perform a given functionality. In these and other examples, one of the devices may be identified as a primary device and the other devices may be identified as secondary devices based on, for example, historical usage data, audio-signal data, computer-vision analysis, and/or one or more other criteria. The functionality may be disabled on the secondary devices until the secondary devices are utilized and/or until a triggering event occurs.

Abstract: A logic circuitry package for association with a replaceable print apparatus component comprises: logic and a serial data bus interface, wherein the serial data bus interface is to interface with a serial data bus of a print apparatus, and, wherein the logic is, in response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, the first command including a time period, to generate a low voltage condition on the serial data bus for a duration based on the time period, and, after the duration, return to a default voltage condition on the serial data bus.

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Abstract: A method for identifying bus nodes in a bus system makes it possible to be able to operate bus slaves of two different types in mixed systems. The detection of which bus slave has not yet been allocated an address in an addressing phase is carried out differently depending on a type of the bus slave. In all cases, however, the bus slave connected to the bus line farthest away from the bus master is identified as that bus slave to which an address is to be allocated.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

Abstract: A cluster deployment and management system includes a networking device that is coupled to a network and to each of a plurality of node devices in a cluster system. The networking device discovers then validates using a cluster profile each of the plurality of node devices in the cluster system. The networking device may then configure itself and any other networking devices according to the cluster profile. The networking device may then configure each of the plurality of node devices according to the cluster profile and deploy one or more applications and data to the node devices. The networking device may negotiate which of at least two networking devices present on the network and may perform lifecycle management operations on the at least one of the node. The networking device performs lifecycle management on at least one of the node devices during operation of the cluster system.

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.

Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.

Abstract: To perform communication more definitely and efficiently. In a case of transferring a communication initiative in accordance with a request by a secondary master, a master determines whether or not the secondary master that has performed the request has a group management capability. Then, when it is determined that the secondary master has no group management capability, the master instructs all communication devices connected to a bus to reset a group address, and when it is determined that the secondary master has the group management capability, the master transfers the communication initiative in a state in which the group address is set. The present technology is, for example, applicable to a bus IF.

Abstract: A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

Abstract: Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.

Abstract: Systems, methods, and apparatus for improving addressability of slave devices coupled to a serial bus are described. A method the slave device includes delaying transitions in a control signal received at an input pin of the slave device, enabling a counter after detecting a delayed first transition in the control signal, where the counter is configured to count pulses on a data line of a serial bus, transmitting a first pulse on the data line of the serial bus after enabling the counter, counting the first pulse and one or more additional pulses on the data line of the serial bus, and using an output of the counter to generate a unique identifier used for communicating over the serial bus. Each of a plurality of slave devices may be configured to transmit one of the additional pulses on the serial bus after the first transition occurs in the control signal.

Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.

Abstract: A method for developing TDM data with embedded control data includes obtaining signal data and control data, formatting the signal data and the control data into a plurality of channels of a DIN signal, and transmitting the DIN signal on one line of a 3-bit TDM bus. A multichannel input device includes a control extractor receptive to the three-bit TDM bus and operative to extract CNTL data from the DIN data, a DAI receptive to the 3-bit TDM bus and the channel select input and operative to develop a SIGNAL data output, and a DAC block including a DAC, the DAC block being receptive to the SIGNAL data and the CNTL data.

Abstract: A peripheral device having a connector receptacle capable of identifying a master-slave mode includes a body and a connector module. The connector module includes a processing unit, an energy storage unit, and a connector receptacle. When the connector module is connected to an electronic device through a power positive terminal, a power negative terminal, a signal positive terminal, a signal negative terminal, and a transmission cable, the processing unit transmits a notification signal to the electronic device through the positive terminal of the signal and the negative terminal of the signal to notify the electronic device that the electronic device does not need to provide power to the peripheral device.

Abstract: A system and method for providing network information using a short-range wireless communication path between a communication device and a terminal device is described. In some examples, authentication information is required from the terminal device prior to communication of the network information. In some examples, the short-range wireless communication path is disconnected and reestablished in which one of the terminal device and the communication device changes operation modes of a short-range wireless interface.

Abstract: Method for digital, bidirectional data transmission between a position measuring system (3-7) and a motor control device (1) and/or an evaluation unit based on the transmission of frames (34, 35, 36) of a predefined bit length in chronologically sequential time slots (28-30), wherein a primary master (1) communicates via a two wire bus line (2) with the position measuring system (3-7) and/or the motor unit (11, 14) and/or the evaluation unit with a primary slave (3) disposed there, and that additional sub-slaves (12, 15) can be coupled in parallel to the primary slave (3), which sub-slaves communicate on the same bus line (2), which the primary master (1) uses with the primary slave (3).

Abstract: A device according to various embodiments may comprise: a transceiver unit configured to transmit or receive information; and a control unit operatively coupled to the transceiver unit, wherein the control unit may be configured to receive, from each of a plurality of control devices that transmit a request for data to a storage device, state information of each of the plurality of control devices, to determine a threshold value for an outstanding data request of each of the plurality of control devices on the basis of the received state information, and to transmit the threshold value to at least one other device.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage system is configured to implement a loopback replication process in which one or more source storage objects are replicated to one or more corresponding target storage objects within the storage system. The storage system is further configured to divide a storage space provided by at least portions of the storage devices of the storage system into slices, to subdivide the slices into source slices and target slices, and to replicate a source storage object associated with at least one of the source slices to a target storage object associated with at least one of the target slices. The source storage object may be associated with at least one of the source slices by, for example, storing the source storage object across portions of the storage devices in designated ones of the source slices.

Abstract: A wireless receiving device for a human powered vehicle comprises a receiver having a first mode, and a second mode in which the receiver consumes less electric power than in the first mode. A controller is configured to set the receiver with the second mode if the receiver does not receive the communication signal in a first-mode period during which the receiver operates in the first mode. The controller is configured to count a consecutive number of a plurality of no-communication periods if no-communication periods consecutively occur. The controller is configured to set the receiver with the first mode if the consecutive number of the no-communication periods is less than a count threshold. The controller is configured to control the receiver to continue the second mode until a release condition is satisfied if the consecutive number is more than or equal to the count threshold.

Abstract: A bus system is provided. The bus system includes a master device, a bus, and a plurality of slave devices electrically connected to the master device via the bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. When a first slave device communicates with the master device through the bus, in a first phase of a plurality of phases in each assignment period, the first slave device sets the alert-handshake control line to a first voltage level via the alert handshake pin, wherein the first phase corresponds to the first slave device. In the phases other than the first phase in each assignment period, the alert-handshake control line is at a second voltage level. Each of the phases includes two clock cycles.

Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. A bus IF is constituted by a master having an initiative of communication and a slave that communicates with the master under the control of the master. Additionally, the slave is provided with a detection unit that, when detecting a change in level of a signal line representing a declaration of initiation or end of communication by the master, outputs a detection signal indicating that the change in level of the signal line representing a declaration of initiation or end of communication has been detected, and a false detection avoidance unit that invalidates output of the detection signal during a specific time slot set in advance. The present technology can be applied to, for example, a bus IF that performs communication in conformity with the I3C standard.

Abstract: Electronic devices according to various embodiments of the present invention comprise: a connector for communicating serial data to an external electronic device; a nonvolatile memory; and a processor, wherein the processor is configured to: acquire identification information of the external electronic device via the connector; confirm whether or not a designated mode of the external electronic device is supported at least on the basis of the identification information; based on the identification that the external electronic device supports the designated mode, acquire first additional information associated with the external electronic device; based on the identification that the external electronic device does not support the designated mode, acquire second additional information associated with the external electronic device; and store the identification information or at least a part of the second additional information in the nonvolatile memory.

Abstract: A device includes a general-purpose input/output node, a serial identifier register, and serial identifier reassignment circuitry. The serial identifier register stores a serial identifier associated with the device. The serial identifier reassignment circuitry is coupled to the general-purpose input/output node and the serial identifier register. The serial identifier reassignment circuitry sets a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node. By setting a bit of the serial identifier based on a steady-state voltage on the general-purpose input/output node, the serial identifier may be easily changed using a pull-up or pull-down resistor external to the device.

Abstract: Various embodiments execute a program with improved cache efficiency. In one embodiment, a first subset of operations of a program is performed on a plurality of objects stored in one or more data structures. The first subset of operations has a regular memory access pattern. After each operation in the first subset of operations has been performed, results of the operation are stored in one of the plurality of queues. Each queue in the plurality of queues is associated with a different cacheable region of a memory. A second subset of operations in the program is performed utilizing at least one queue in the plurality of queues. The second subset of operations utilizes results of the operations in the first subset of operations stored in the queue. The second subset of operations has an irregular memory access pattern that is regularized by localizing memory locations accessed by the second subset of operations to the cacheable region of memory associated with the at least one queue.

Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Abstract: The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series. The master element receives the transmission data transmitted from the slave element to be the transmission source via the transmission path, and at least the slave element to be the transmission source includes a data transmission unit that is connected to the transmission path via a second switch and transmits the transmission data.

Abstract: An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

Abstract: Systems, methods, and apparatus for optimizing bus latency using bit-interleaved bidirectional transmission on a serial bus are described. A method performed at a device coupled to a serial bus includes pairing with a second device in a transaction to be conducted over the serial bus, transmitting a first data bit to the second device over a data line of the serial bus in a first part of each cycle in a plurality of cycles of a clock signal transmitted on a clock line of the serial bus, and receiving a second data bit transmitted by the second device on the data line in a second part of each cycle. The serial bus may be operated in accordance with an I3C, RFFE, SPMI, or other protocol.

Abstract: A method can be used for monitoring a processing circuit. The processing circuit generates a response to a request and the response is compared with an expected response. A pass pulse is generated when the response matches the expected response. The causing, comparing and generating steps are repeated a number of times A frequency at which pass pulses occur is evaluated.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide, at most, two integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device (i.e., a master device). At least one of integrated circuits may comprise a first interface and a second interface, wherein the second interface is connected to the host in a manner that is opposite that of the first interface.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.

Abstract: A system comprising an arrangement of multiple processor modules, and an external interconnect for communicating data in the form of packets to outside the arrangement. The interconnect comprises an exchange block configured to provide flow control. One of the processor modules is arranged to send an exchange request message to the exchange block on behalf of others with data to send outside the arrangement. The exchange block sends an exchange-on message to a first of these processor modules, to cause the first module to start sending packets via the interconnect. Then, once this processor module has sent its last data packet, the exchange block sends an exchange-off message to this processor module to cause it to stop sending packets, and sends another exchange-on message to the next processor module with data to send, and so forth.

Abstract: Apparatus and associated methods relate to a networked system having a master and multiple slaves, where each slave stores a unique (actual) slave address and a non-unique (virtual) slave address in memory, such that each slave is configured to respond to request messages addressed to the slave's non-unique slave address if a sensor device associated with the is in an active state when the slave receives the request message. In an illustrative example, the networked system may be a Fieldbus-style network (e.g., a network implementing the Modbus protocol). A sensor device may be a break-beam, capacitive touch, or push-button device, for example. An output indicator/actuator may be associated with a sensor device to indicate the status of the sensor device to a user. A networked system implementing sensor-activated response gating may beneficially expand the number of slave devices on the network while achieving low latency response times.

Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device.

Abstract: An electronic device associates first information and at least a first portion of a first image, and uses a second image that includes a portion corresponding to at least the first portion of the first image to access the associated first information.

Abstract: A system for preventing faulty connection between PoC and PoE. The system includes a signal generating circuit for generating a detection signal of a detection format of a powered device. A signal feedback circuit is configured to receive the detection signal, and to send a feedback signal to a power source equipment. A signal detecting circuit is configured to detect the feedback signal. A first control switch is coupled to the signal detecting circuit. A second control switch is coupled to the signal feedback circuit.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.

Abstract: Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (I2C) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an I2C device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the I2C OBI, an I3C IBI that includes information related to the I2C OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.