Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: Systems and methods relate to a bus adapter for a storage network. The bus adaptor includes a context memory comprising a first storage for uncacheable exchange resource indicators (XRI) and a second storage for cacheable XRI. The bus adapter also includes a host backing store unit configured to provide access to the different tier memories present locally or externally in the host memory extension using several caching sub-units and with the capability of an optional pinning operation for the cacheable XRI based upon at least one of input/output phase, first in line up to a limit, a region of a virtual context address associated with the cacheable XRI indicators, a protocol associated with the cacheable XRI, a size of a transaction, or work queue information.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: A first command is scheduled on a command bus, where the first command requires use of a data bus resource at a first time period after scheduling the first command. Prior to the first time period, a second command is identified according to a scheduling policy. A determination is made whether scheduling the second command on the command bus will cause a conflict in usage of the at least one data bus resource. In response to determining that scheduling the second command will cause the conflict in usage, a third lower-priority command is identified for which scheduling on the command bus will not cause the conflict in usage. The third command is scheduled on the command bus prior to scheduling the second command, even though it has lower priority than the second command.

Abstract: A device includes a first and a second stage round robin arbitrations. The first stage receives request signals and selects a subset the request signals. Each request signal is associated with whether a component is requesting access to a common resource. The second stage receives the selected subset and grants access to the common resource to each request signal of the selected subset that is requesting access, in a round robin fashion. The second stage outputs an enable signal to the first stage when the selected subset is processed. The first stage selects another subset and transmits the selected another subset to the second stage for round robin processing thereof. The process is repeated until all subsets with at least one request signal to access the common resource is processed and granted access in a round robin fashion.

Abstract: For generating 3D audio content from a two-channel stereo signal, the stereo signal (x(t)) is partitioned into overlapping sample blocks and is transformed into time-frequency domain. From the stereo signal directional and ambient signal components are separated, wherein the estimated directions of the directional components are changed by a predetermined factor, wherein, if changes are within a predetermined interval, they are combined in order to form a directional centre channel object signal. For the other directions an encoding to Higher Order Ambisonics HOA is performed. Additional ambient signal channels are generated by de-correlation and rating by gain factors, followed by encoding to HOA. The directional HOA signals and the ambient HOA signals are combined, and the combined HOA signal and the centre channel object signals are transformed to time domain.

Abstract: A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.

Abstract: Systems and methods are disclosed for managing personalized dining checks created by individualized ordering enabled by associating mobile devices of patrons and waiters with table indicia.

Abstract: Embodiments of the present disclosure provide a method and device for storing data. The method comprises: generating a data block corresponding to data to be stored; aligning the data block to a boundary of a tracking unit of a predefined size for validating the data; and storing the aligned data block in at least one storage unit of a storage space, the at least one storage unit having an identical size. The method according to embodiments of the present disclosure can align the data block so as to minimize the waste of storage space and avoid the situation where the rest data cannot be validated due to disappearance of partial data.

Abstract: A method includes receiving feedback information indicative of an overload condition from an arbiter. The method further includes deprioritizing a routing bus based on the received feedback information and selecting a routing bus to use to send a transaction across a system-on-chip (SOC).

Abstract: An inmate facility management system with a shared storage device and a processor configured to receive data and search requests from multiple disparate facility systems. The processor has an interface to translate data from the multiple disparate facility systems and store the data in the shared storage device. The processor executes booking requests, warrant requests and release requests using the shared storage device.

Abstract: Technologies for one-tap connection and synchronization with a device in a non-active state are disclosed. When a user brings a first device enabled for Near Field Communication (NFC) to close proximity of a second NFC-enabled device when the second device is in a non-active state, the second device may be awakened, or placed in an active state, for a period of time to perform one or more operations before returning to the non-active state. These operations include, for example, allowing the first device to access data stored in the second device and synchronizing one or more applications installed on the second device with remote servers.

Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.

Abstract: A scheduling device according to one embodiment includes an access request accepting section and an access request selecting section. The access request accepting section is configured to accept access requests from requesters. The access request selecting section is configured to select a first access request as a reference for access request selection from among the accepted access requests, select an access request transferable in a bank interleave (BI) mode with respect to the first access request, and select an access request transferable in a continuous read/write (CN) mode in response to a determination that there is no access request transferable in the BI mode, or that the preceding access request was in the BI or the CN mode. The access request selecting section is configured to repeat the selections in response to a determination that there is no access request transferable in the BI mode and in the CN mode.

Abstract: A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include defining, by a first computer in communication with a storage system, at least two priority levels for storage management commands to be processed by the storage system, and defining a respective queue for each of the defined priority levels. Upon receiving multiple storage management commands from one or more second computers in communication with the first computer and the storage system, a respective priority is determined for each of the received storage management commands, and the respective queue is identified for each of the received storage management commands based on the respective priority thereof. Each of the received storage management commands is loaded to the respective identified queue thereof, and the received storage management commands stored in the respective queues are processed by the storage system according to the priority levels thereof.

Abstract: Arbitration circuitry is provided to select an output from between multiple inputs each having an associated priority value. A tie-break value is appended to the least significant bits of each of the priority values to form extended priority values before those extended priority values are compared. Thus, if two priority values are equal, then the appended tie-break bits are used to determine which of the two inputs will be selected as having the higher priority.

Abstract: Systems and methods for increasing speed and reducing area for arbitration logic in an integrated circuit (IC) are provided. For example, in one embodiment, a method includes arbitrating at least one master request in a first level of arbitration blocks. A second level of arbitration blocks arbitrates at least two arbitration blocks from the first level. A first level of multiplexers multiplex at least one master payload based at least in part upon the arbitration of the first level of arbitration blocks. A second level of multiplexers multiplex at least two signals propagated from the first level of multiplexers.

Abstract: Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.

Abstract: Systems and methods are described for arbitrating access of a communication bus. In one embodiment, a method includes performing steps on one or more processors. The steps include: receiving an access request from a device of the communication bus; evaluating a bus schedule to determine an importance of the device based on the access request; and selectively granting access of the communication bus to the device based on the importance of the device.

Abstract: Method and structures for performing round robin priority selection receive an input vector into an input port. The methods and structures group the bits of the input vector into groups of bits and supply the groups of bits to round robin priority selectors. Then, the methods and structures simultaneously identify an individual group priority bit within each group of bits based on the starting bit location, using the round robin priority selectors. The methods and structures also choose, using the group selector, a round robin priority selector based on the starting bit location. The methods and structures then output, from the group selector to a multiplexor, the individual group priority bit of the selected round robin priority selector. Following this the method outputs, from the multiplexor, an output vector having a first value (e.g., 1) only in the individual group priority bit output by the group selector.

Abstract: A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).

Abstract: A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers.

Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.

Abstract: The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the I/O control device of the far-end. The I/O control device has a CPU to receive the identification code and judge whether the identification code matches with the predetermined value stored therein; if the identification code matches with the predetermined value, the mobile internet connection between the host and the I/O control device is activated to enable the host to mutually transmit information or signals with a far-end control device from the I/O control device through the mobile internet, and the connection will be disabled after the information or signal transmission is completed.

Abstract: Apparatus includes a plurality of ports and arbitration circuitry. The plurality of ports is configured to connect a memory to a respective plurality of processing units that are configured to access the memory. The arbitration circuitry is configured to grant the processing units access to the memory via the ports in accordance with an arbitration scheme including multiple, alternating priority periods, such that in each priority period a respective processing unit is assigned an absolute priority over others of the processing units and the others of the processing units are assigned predefined relative priorities over one another.

Abstract: Some of the embodiments of the present disclosure provide a method for scheduling processing of packets received from a network, comprising assigning a corresponding queue weight to each of a plurality of queues that are configured to enqueue the packets for processing; for each of the plurality of queues, determining a corresponding multiplication factor (MF) as a function of a number of cycles until a next packet is available from the corresponding queue for processing; and incrementing a plurality of counters, associated with the corresponding plurality of queues, based at least in part on the multiplication factors. Other embodiments are also described and claimed.

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories.

Abstract: A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state.

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract: A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N2).

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: The fast round robin circuit includes AND gates, OR gates, multiplexers and four D flip-flop gates configured to handle requests using linear propagation of a single grant token. In this manner the device avoids wasting clock cycles when some of the arbitrated entities do not have a pending request. The circuit has an R stage and an S stage. The R stage contains the request signal and an R memorization element to memorize the request. The S stage is the arbitration stage where the next active request is selected based on the position of the current request. The selection is then memorized in an S selection bit memorization element. There is one request signal and one pair of R and S Flip-Flops associated to every requesting entity. The selection circuit skips inactive requests to enable the next active request in a polling direction defined by the circuit.

Abstract: An apparatus for controlling access to a resource includes a shared pipeline configured to communicate with the resource, a plurality of command queues configured to form instructions for the shared pipeline and an arbiter coupled between the shared pipeline and the plurality of command queues configured to grant access to the shared pipeline to a one of the plurality of command queues based on a first priority scheme in a first operating mode. The apparatus also includes interface logic coupled to the arbiter and configured to determine that contention for access to the resource exists among the plurality of command queues and to cause the arbiter to grant access to the shared pipeline based on a second priority scheme in second operating mode.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract: Memory access arbitration allowing a shared memory to be used both as a memory for a processor and as a buffer for data flows, including an arbiter unit that makes assignment for access requests to the memory sequentially and transfers blocks of data in one round-robin cycle according to bandwidths required for the data transfers, sets priorities for the transfer blocks so that the bandwidths required for the data transfers are met by alternate transfer of the transfer blocks, and executes an access from the processor with an upper limit set for the number of access times from the processor to the memory in one round-robin cycle so that the access from the processor with the highest priority and with a predetermined transfer length exerts less effect on bandwidths for data flow transfers in predetermined intervals between the transfer blocks.

Abstract: A method of determining request transmission priority subject to request source and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective source and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: Methods are provided for determining a master node on a ring network. According to one embodiment, a first node on the ring network initiates circulation of an arbitration token by (i) determining an arbitration token timeout period has elapsed and (ii) transmitting the arbitration token to a neighboring node. Upon receipt of the arbitration token by a node, it determines its relative priority by comparing its ID to an ID field of the arbitration token, initialized by the first node. If the node is determined to be higher priority, then it overwrites the ID field and retransmits the arbitration token onto the ring network. If the node is determined to be lower priority, then the node retransmits the arbitration token without overwriting the ID field. If the node is determined to be of equal priority and the node is the first node, then it assumes the master node role.

Abstract: A network of nodes caches replicated datasets in which dataset changes are efficiently propagated as a set of changes even under failure conditions. A master node and a plurality of subordinate nodes in the network each maintain a copy of the dataset and a change log storing change events in the dataset in that node. The change log further includes a rename chain having a plurality of linked rename records created in response to a new master gaining control of the dataset. The master node computes and propagates dataset changes to the subordinate nodes as a set of change events. If the master node fails, one of the subordinate nodes becomes temporary master and continues to propagate dataset changes using its dataset and its change log in response to update requests from other nodes where the update request contains information from the change log of the requestor node.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Abstract: A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Abstract: A system comprises a plurality of electronic devices connected to a bus in operational use. For automatic address configuration of the devices, the devices are daisy-chained. In the daisy-chain, a preceding one of the devices transfers its address to a next one of the devices, and the latter determines its own address via an offset with respect to the address received.