Abstract: Various methods and apparatuses are described for an arbitration unit that implements a round robin policy. Each requesting device has an equal chance of accessing a shared resource based upon a current request priority assigned to that requesting device. The arbitration unit includes at least a state block that includes a plurality of state registers. The plurality at least includes a first state register for a first unordered pair of requesting devices, a second state register for a second unordered pair of requesting devices, and a third state register for a third unordered pair of requesting devices.

Abstract: A device includes an M-bit input request for service bus, a MASKGEN component that generates a shifting mask, the MASK component that generates an 2*M-bit enabled request for service bus, a NEGATE component that may perform a negation operation on the MASK 2*M-bit enabled request for service output, and a COMBINE component which receives the MASK 2*M-bit enabled request for service output and 2*M-bit NEGATE output and combines them into M-bit 1-HOT grant output bus. The COMBINE output indicates which request for service is being granted by the device.

Abstract: For every sampling period of a DSP 100, a timing generator 200 requests a CPU 300 to release a bus and provides a DSP 100 access time period to make an external memory 400 access the DSP 100 by occupying the bus released according to the request. In the DSP 100, during the DSP access time period, a memory interface section 11 executes read/write processing in which waveform data read from the external memory 400 is stored in an internal memory 12 and waveform data read from the internal memory 12 is written into the external memory 400 according to the command stored in an access command memory 10. At the same time, an operation section 13 executes operation processing by using the waveform data stored in the internal memory 12 independently of the read/write processing.

Abstract: A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract: An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval.

Abstract: A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the requestors is selected next. The first addend is an N-bit vector where each bit is false if the corresponding requester is requesting access to a shared resource. The second addend is a 1-hot vector indicating the last selected requester. A multithreading microprocessor dispatch scheduler employs the circuit for N concurrent threads each thread having one of P priorities. The dispatch scheduler generates P N-bit 1-hot round-robin bit vectors, and each thread's priority is used to select the appropriate round-robin bit from P vectors for combination with the thread's priority and an issuable bit to create a dispatch level used to select a thread for instruction dispatching.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request signal to request a bus right to the arbitration circuit. A request acknowledge signal receiving section receives a request acknowledge signal transmitted from the arbitration circuit in response to the request signal transmitted to the arbitration circuit. Further, the request signal from the request signal transmitting section is transmitted after lapse of a predetermined time since reception of the request acknowledge signal.

Abstract: Managing data traffic among three or more bus agents configured in a topological ring can include numbering each bus agent sequentially and injecting messages from the bus agents into the ring during cycles of bus agent activity, where the messages include a binary polarity value and a queue entry value. Messages are received from the ring into two or more receive buffers of a receiving bus agent. The value of the binary polarity value is changed after succeeding N cycles of bus ring activity, where N is the number of bus agents connected to the ring. The received messages are ordered for processing by the receiving bus agent based on at least in part on the polarity value of the messages and the queue entry value of the messages.

Abstract: The present invention provides an arbiter and its arbitration method. The master devices in the bus system can be divided into primary master devices and secondary master devices. Said arbiter has first and second stage arbitration modules, wherein the second stage arbitration module can be used for arbitrating bus usage requests sent by secondary master devices, and the first stage arbitration module can be used for arbitrating the arbitrated result of the second stage arbitration module and bus usage requests sent by primary master devices together, so that it can set arbitrating opportunity against different bus usage requests so as to raise arbitration efficiency and bus usage efficiency. The arbiter also provides reverse arbitration ability, which can avoid the conflict among returning data based on improving the bus usage efficiency.

Abstract: A device, a method and a system for portable data storage and transfer through a simplified device interface. The operations of the device are restricted, in order to increase the ease of use of the device, and in order to provide certain core functions. These core functions include reading data, writing data and exchanging data with a similar device and/or with an external computer. The device features a minimal set of hardware components for accomplishing these functions, such as a data processor of some type, a memory storage medium or media, and a data exchange mechanism, which may optionally be an infrared port for example.

Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.

Abstract: An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value specifying which of the N requestors was last selected. A second input receives a second value specifying which of the N requestors is enabled to be selected. A barrel incrementer, coupled to receive the first and second inputs, 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic, coupled to the barrel incrementer, generates a third value specifying which of the N requestors is selected next.

Abstract: A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a plurality of I/O devices, wherein each of the I/O schedulers schedules I/O requests according to a different scheduling method. The method also includes scheduling one of the I/O requests with at least one of the plurality of I/O schedulers. The method also includes determining that a second I/O scheduler replaces an I/O scheduler of the plurality of I/O schedulers, installing the second I/O scheduler, and scheduling one of the I/O requests with the second scheduler.

Abstract: The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a corresponding plurality of processing resources, and an arbitrating interface directing the flow of data from the source channels to the processing resources where the data must flow over a shared data path. The plurality of processing resources may comprise any system of parallel processors where the servicing of input data must be carried out in a manner where there the maximum latency for processing a given data channel is determinable, the arbitration between channels is equal, no input channel may prevent another channel from being serviced, and lower priority processing resources are not prohibited from receiving input data if higher priority processing resources are not currently available or if higher priority data is not currently available.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.

Abstract: A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no more than one request arrives at a slave at any given time. If a request arrives while a slave is processing a previous request, the arriving request is not serviced, and the master that originated the arriving request is asked to retry the request at a later time. Atomic shadow-write operations are supported by including all shadow registers in a dedicated sub-ring of the CAR architecture.

Abstract: A communication switch that includes a multiprocessor control block and a method therefore is presented. The multiprocessor control block includes a centralized resource and routing processor that controls resource allocation and routing functionality within the switch. A plurality of intermediate processors operably coupled to the resource and routing processor perform call processing for corresponding portions of the connections supported by the switch, where such call processing includes issuing resource allocation requests to the resource and routing processor. Each of the intermediate processors further performs functions associated with a signaling layer portion of the protocol stack. The multiprocessor control block also includes a link layer processor operably coupled to the plurality of intermediate processors, where the link layer processor also couples to a switching fabric of the communication switch.

Abstract: Operations in a multi-processor, multi-control block environment are timed u sing timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an operation that needs to be timed, the SCB is queued on one of multiple timing queues based on an elapsed timeout limit (ETL) of the operation. There is an ETL for each operation, and each one the multiple timing queues is associated with an ETL for completing an operation. The SCB may be placed at the bottom of the timing queue, the timing queue ordered from oldest to youngest which allows for quickly checking large numbers of SCBs without having to check every element queue and without having to dequeuing the elements from this queue. Upon receipt of a request to perform a high-priority operation, the SCB may be queued in a high priority instruction queue. The SCB may remain the timing queue to retain its order and be placed on a high priority instruction queue for retrying an operation.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: Embodiments of token hold off techniques for a token based communication interconnect are presented herein.

Abstract: A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of blocks of requests, to select a block having one or more active requests using round robin arbitration, and to generate a first index corresponding to the selected block. The second round robin arbitration module has a second bit width. It is configured to store each request of the selected block, to select each active request of the selected block using round robin arbitration, to generate a second index corresponding to the selected active request, and to generate a first signal for synchronizing operation of the first and second modules. The round robin arbitration system has a bit width that is a product of the first and second bit width.

Abstract: A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.

Abstract: Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality of bus interfaces. Arbitration logic is configured for communication with the plurality of ports. The arbitration logic arbitrates access to the memory circuitry among the plurality of bus interfaces on a time shared basis.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: A computer subsystem of a computer includes a CPU, RAM, display, storage device, input device(s), and a digital-audio generating IC. A CD-ROM subsystem of the computer includes a CD-ROM drive and CD-ROM control buttons for controlling CD-ROM drivers operation while playing audio CDs. An audio-interface IC of the CD-ROM subsystem couples a bus of the computer subsystem to the CD-ROM drive, and to the control buttons. The audio-interface IC, in one operating mode, relays commands and data between the bus and the CD-ROM drive. A second operating mode permits turning the computer subsystem off while the audio-interface IC autonomously responds to the control buttons and transmits commands to the CD-ROM drive for playing an audio CD.

Abstract: A processor is used to evaluate information regarding the number, size, and priority level of data transfer requests sent to a plurality of communication ports. Additional information regarding the number, size, and priority level of data requests received by the communication ports from this and other processors is evaluated as well. This information is applied to a control algorithm that, in turn, determines which of the communication ports will receive subsequent data transfer requests. The behavior of the control algorithm varies based on the current utilization rate of communication port bandwidths, the size of data transfer requests, and the priority level of the these transfer requests.

Abstract: A device, a method and a system for portable data storage and transfer through a simplified device interface. The operations of the device are restricted, in order to increase the ease of use of the device, and in order to provide certain core functions. These core functions include reading data, writing data and exchanging data with a similar device and/or with an external computer. The device features a minimal set of hardware components for accomplishing these functions, such as a data processor of some type, a memory storage medium or media, and a data exchange mechanism, which may optionally be an infrared port for example.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to job requests submitted by processes in the computer system are monitored and analysed. These heuristics may include the number of read and write requests, the ratio of read requests to write requests, input/output throughput, disk utilization and the average time taken for processes to submit subsequent jobs once an initial job completes. The analysed heuristics are compared to the desired sets of heuristics for the plurality of input/output schedulers to select one of the plurality of input/output schedulers.

Abstract: A shared bus system includes a bus, a first circuit which accesses the bus, a second circuit which shares the bus with the first circuit, and accesses the bus, a counter circuit which is provided in the second circuit, and performs a counting operation each time the second circuit accesses the bus, and an arbiter circuit which arbitrates requests for a right to use the bus between the first circuit and the second circuit, wherein the second circuit releases the right to use the bus in response to detection of a predetermined number of counting operations performed by the counter circuit after acquiring the right to use the bus from the arbiter circuit.

Abstract: A master node in a packet ring network periodically sends a packet containing a discovery marker into the packet ring network. As each node in turn receives the packet, each adds its own discovery marker, which contains its topology information, to the packet, saves the topology information of others, and resends the packet to the next node in the ring. Eventually, the master node receives the packet containing a chain of discovery markers for all active nodes terminated by the master's own discovery marker, so the master node then removes its own discovery marker and resends the packet in to the ring network. Each node in turn then removes its own discovery marker. In this way, all nodes in the ring see topology information for every other active node.

Abstract: A master entity is capable of broadcasting commands to slaves which move to another state when they satisfy a primitive condition specified in the command. By moving slaves among three sets, a desired subset of slaves can be isolated in one of the sets. This desired subset of slaves ten can be moved to one of the states that is unaffected by commands that cause the selection of other desirable subsets of slaves. In the incorporated U.S. Pat. Nos. 5,550,547 and 5,673,037, certain subgroups of radio frequency tags are selected for querying, communicating, and/or identifying by commands from a base station.

Abstract: A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Abstract: In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration for ownership of a bus connected to a plurality of bus masters comprises grouping the plurality of bus masters into a plurality of groups and arbitrating the frequency of each bus master's ownership of the bus according to the result of the grouping. It is preferable that each of the plurality of groups has a priority different from the priorities of the others, and in arbitrating the frequency of each bus master owning the bus, arbitration of ownership of the bus by bus masters belonging to the same group is performed according to a round-robin method.

Abstract: A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant one of the remaining requests in accordance with a second arbitration scheme. The first arbitration scheme may be a fast arbitration scheme such as a fixed-priority scheme, and the second arbitration scheme may be a rotating priority-based arbitration scheme or a least-recently-granted arbitration scheme. The first-stage arbiter may operate in a first pipelined stage, and the second-stage arbiter may operate in a second pipelined stage. Two-stage arbitration may help improve access of lower-priority requestors in a pipelined system. In one embodiment, a rotating-priority arbitrator includes a pseudo-random number generator to generate an amount for rotating priorities prior to arbitration. The rotating-priority arbiter may use either a counter or linear-feedback shift register to rotate priorities of requests.

Abstract: A bus arbitration system employs counters respectively provided for an encoding section and an decoding section that are started when there is a request signal from the respective encoding section and decoding section. The counter values are outputted to respective comparators that compare the counter values with predetermined values and the results of the comparisons are fed to an arbitration controller. The arbitration controller in turn determines priority rankings for the encoding section and the decoding section based on the signals inputted from the comparators and outputs an acknowledgement signal to the module that has the highest priority.

Abstract: In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and a grant-reordering unit. In the fixed priority mode or the round-robin mode, the HPRIF rotating unit rotates priority information related to bus masters stored in a predetermined register in a predetermined direction to give the highest priority to a bus master in response to pointer information and outputs changed priority information. When a request signal is received from the bus masters, the request-reordering unit reorders requested priorities of the bus masters to be in accordance with the changed priority information and outputs a request-reordering signal. The request-selecting unit outputs a bus master-selecting signal according to priorities in response to the request-reordering signal.

Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Abstract: A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a plurality of competing entities. Arbitration based on probabilistic control of arbiter nodes' behavior is set forth for alleviating the inherent unfairness of a binary tree arbiter (BTA). In one implementation, BTA flag direction probabilities are computed based on composite weighted functions that assign relative weights or priorities to such factors as queue sizes, queue ages, and service class parameters. Within this general framework, techniques for desynchronizing a binary tree's root node, shuffling techniques for mapping incoming service requests to the BTA's inputs, and multi-level embedded trees are described.

Abstract: A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan registers. The controller is configured to allocate and is configured to reallocate resources among the requestor groups to efficiently manage the computer system. The loan registers account for reallocated resources such that intended preallocation of use of shared resources is closely maintained. Hence, the computer system is able to operate efficiently while preventing any single requestor or group of requestors from monopolizing shared resources.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.