Abstract: A resource circuit board is configured for use by a physical migration system, the resource circuit board including at least one common interface shaped and configured to connect to an interconnect of a base circuit board; and at least one migration-support interface the at least one common interface being different from the at least one migration-support interface, the at least one migration-support interface: shaped to connect to at least one corresponding migration-support interface of the physical migration system; and configured to provide at least one of power and connectivity to the resource circuit board during a physical migration of the resource circuit board.

Abstract: Examples provide a method of communication between a client application and a filesystem server in a virtualized computing system. The client application executes in a virtual machine (VM) and the filesystem server executes in a hypervisor.

Abstract: A method of controlling a read request can include: receiving, in a host device, the read request from a bus master, where the host device is coupled to a memory device by an interface; determining a configuration state of the read request; comparing an attribute of the read request against a predetermined attribute stored in the host device; adjusting the configuration state of the read request when the attribute of the read request matches the predetermined attribute; and sending the read request with the adjusted configuration state from the host device to the memory device via the interface.

Abstract: Apparatus including a network element including an input-output port, the input-output port including an input data lane and an output data lane, wherein the input data lane is in wired connection with a network data source external to the network element, the output data lane is in wired connection with a network data destination external to the network element, and the network data source is distinct from the network data destination. Related apparatus and methods are also described.

Abstract: Systems, devices, and methods are disclosed for exchanging electronic information over a communication network and, more specifically, to authenticating and verifying data integrity between two or more interacting users exchanging information. A client computing device generates a split secret that is transmitted to a server via two distinct communication channels. The split secret is generated based on a public key of a public-private key pair generated by the client computing device based on a unique identifier. Validity of the public key can authenticate source identity.

Abstract: The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Abstract: Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

Abstract: The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing solid state drives. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command.

Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.

Abstract: A set of techniques is described for performing input/output (I/O) between a guest domain and a host domain in a virtualized environment. A pool of memory buffers is reserved for performing virtualized I/O operations. The reserved pool of memory buffers has static mappings that grant access to both the guest domain and the host domain. When a request to perform an I/O operation is received, the system can determine whether the memory buffers allocated to the I/O operation belong to the reserved pool. If the buffers are in the reserved pool, the host domain executes the I/O operation using the buffers without the need to map/unmap the buffers and perform TLB flushes. If the buffers are not in the reserved pool, the system can either copy the data into the reserved pool or perform the mapping and unmapping of the memory buffers to the address space of the host domain.

Abstract: A technique includes delaying bus activity targeting a memory device and indicating a command for the memory device to allow time for the memory device to complete processing the command. The delaying of the bus activity includes selectively generating an error signal on a memory bus.

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract: A method and device for on-chip bus arbitration are disclosed. The method includes: dividing devices into a first level, a second level and a third level from high to low; and in each arbitration period, calculating remaining processing time of each real-time transaction, and upgrading a device making a request required to be processed immediately to the first level in the current arbitration period; monitoring bandwidth usage amount of devices of the first level and the second level respectively, and downgrading a device whose bandwidth usage amount exceeds a preset bandwidth threshold value to the third level in the current arbitration period; and in devices making requests for a bus use right, if a device of the highest level is the device of the first level, authorizing the device of the first level; and if it is not the device of the first level, authorizing a device making continuous requests.

Abstract: There are provided a method, a system and a computer program product for minimizing data transfer latency between redundant storage controllers in a network-based storage controller system that utilizes adaptive data throttling. Each corresponding redundant storage controller calculates average time latency for round trip communications between the corresponding redundant storage controller and the other redundant storage controllers during a fixed monitoring period. The corresponding redundant storage controller, at the end of each fixed monitoring period, compares the average time latency to a fixed latency. The corresponding redundant storage controller selectively throttles data transfer between the corresponding redundant storage controller and a server and data transfer between the corresponding redundant storage controller and a back-end storage, based on the comparison.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus and to confirm a trigger condition. A module is configured to send a message over the communication bus when the trigger condition is confirmed.

Abstract: A communication interface (e.g., a memory interface) includes a data processing channel adapted to be coupled to a data source and having multiple data processing stages. A bypass network or pipeline is coupled to the data processing channel and configurable to bypass at least one stage in the data processing channel. A controller is coupled to the bypass network for configuring the bypass network to bypass at least one stage of the data processing channel based on performance criteria. In some embodiments or modes of operation, the bypass network is configured to bypass at least one stage of the data processing channel to reduce idle latency after an idle period. In an alternative embodiment or mode of operation, the bypass channel is configured to include at least one stage of the data processing channel to increase data throughput.

Abstract: A method is described and presented for creation of an optimized schedule for execution of a functionality by means of a time-controlled distributed computer system, in which the distributed computer system and the functionality have a set of (especially structural and functional) elements of at least one element class and the elements are at least partially in a dependence. The method according to the invention, in which the task is solved, is initially and essentially characterized by the fact that the dependences between the elements are recognized, classified and the elements are assigned to corresponding dependence classes, and that optimization of schedule occurs by coordination of elements of at least one dependence class.

Abstract: Mechanisms for reducing the idle time of a computing device due to delays in transmitting/receiving acknowledgement packets are provided. A first data amount corresponding to a window size for a communication connection is determined. A second data amount, in excess of the first data amount, which may be transmitted with the first data amount, is calculated. The first and second data amounts are then transmitted from the sender to the receiver. The first data amount is provided to the receiver in a receive buffer of the receiver. The second data amount is maintained in a switch port buffer of a switch port without being provided to the receive buffer. The second data amount is transmitted from the switch port buffer to the receive buffer in response to the switch port detecting an acknowledgement packet from the receiver.

Abstract: Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.

Abstract: A system, apparatus and method for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock functions utilized in the system. The system comprises at least one of a plurality of modules that further comprise at least one actual clock. The at least one module further comprises a scheduler coupled to the at least one clock, wherein the scheduler is configured to receive a virtual schedule comprising a time slot for sending a message to the communication bus. The scheduler is further configured to determine an actual time for sending a message in relation to the virtual schedule and according to time kept in the at least one actual clock. The module is configured to send a message according to the actual time, wherein the module starts transmission of the message according to the actual time.

Abstract: An apparatus and method for operating many applications between a portable storage device and a digital device are provided. The method includes opening at least two logical channels from the digital device to the portable storage device through a physical channel, transmitting and receiving data between a plurality of applications of the digital device and a plurality of applications of the portable storage device through the opened logical channels, and closing the logical channels after finishing the transmitting and receiving of the data.

Abstract: A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal.

Abstract: A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved.

Abstract: Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.

Abstract: A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issued to recipient elements, and a communication channel shared amongst those processing elements over which the messages are routed. Arbitration circuitry performs an arbitration process to arbitrate between multiple messages routed over the communication channel. Each processing element issues progress data for the process executing on that processing element, the progress data indicating latency implications for the process. Arbitration control circuitry is then responsive to the progress data from each processing element to perform a priority ordering process taking into account the latency implications of each process as indicated by the progress data in order to generate priority ordering data.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

Abstract: In a CAN system, an arrangement is incorporated for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock functions utilized in the system. The system operates with communication on the bus connection that is in accordance with rules set up in the system and constitutes a combination of event-driven and time-controlled communication functions. The said functions are, together with a rule change in the time-controlled communication function, arranged to achieve the said making more efficient and/or reduction. The rule change is arranged to bring about deliberate collisions between messages appearing on the bus connection. In this way, the bandwidth utilization, the clock function and the system's general construction and function can be simplified according to the requirements imposed.

Abstract: A method of detecting master/slave response time-out under continuous packet format communications protocol, which calculates the time required for the slave device to respond to a Modbus request subject to Modbus TCP/UDP protocol. The method is to continuously send Modbus requests to a slave device through a detection device and to record each Modbus request sent time, and to have the slave device provide to the detection device a response for each Modbus request. By means of calculating the precise response time-out from the response time-outs which are gotten from the slave device responds to a predetermined number of Modbus requests, the user or manager can determine the response time-out required for the slave device precisely so as to give an EXECUTE instruction or command at the accurate time point.

Abstract: An arbitrator circuit for accessing a bus comprises a logic gate arrangement (406), one input of which is coupled to a first bus line. The circuit comprises a switching arrangement (404, 405, 407). As a response to a control signal the switching arrangement disconnects a first half (402) of the first bus line from a second half (403), and couples the second half (403) to a first fixed potential. A second bus line (401) is decoupled from the logic gate arrangement (406), which is coupled to receive a second fixed potential. The second bus line is coupled to the first fixed potential. Two sources are available for providing the control signal to the switching arrangement (404, 405, 407). One of them is the output of the logic gate arrangement (406).

Abstract: Requestors issue access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a threshold, a free pass (FP) is granted to specified requesters. When issuing access requests, requesters request and acquire tokens before issuing the access requests if they have no FP granted. If the requesters have an FP, they simply issue the access requests.

Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: The invention relates to a method for data transmission in a serial bus system comprising a control unit and bus users. The method comprises steps: receiving a first data telegram by a bus user from the control unit, wherein the data telegram has a data field containing output data; reading out the data field intended for the bus user from the first data telegram; preparing input data as a response to the read out data field; checking whether a predefined criterion is met, wherein if the criterion is met a second data telegram is newly generated and the input data is attached to the second data telegram and if the criterion is not met, the input data is attached to a data telegram previously received from another bus user; and transmitting the input data to the control unit by the second data telegram.

Abstract: A method that enables testing any point (target point) within a core, including a point within a combinatorial circuit of a core, permits testing of points that are not otherwise unobservable in normal debugging processes. Such a target point is tested by identifying a fanout cone from that point to observable outputs, and by performing one or more tests, where each test sensitizes one or more paths that extend the signal of the target point, or its complement, to one or more of the observable outputs, and ascertains the values at those observable outputs. By having more than one observable output at which the signal of target point (or its complement) is tested significantly increases the level of confidence in the test when the observable points concur in the signal value of the target point.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract: The present invention improves bus transfer efficiency in bus communication that uses a shared memory. A communication origin master 101 selectively uses an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.

Abstract: A method (100) is disclosed for communicating data over a data communication bus (310) comprising a first conductor (312) and a set of further conductors (314). The method (300) comprises providing the first conductor (312) with a first signal transition (210) for signalling the start of a first data communication period (T1); and providing a further conductor (314), after a predefined delay with respect to the provision of the first signal transition (210), with a delayed signal transition (220), the predefined delay defining a first data value. Consequently, the method of the present invention provides a data encoding technique for data communication over a bus that requires less switching activity than other encoding techniques such as pulse width modulation encoding. The present invention further discloses a data communication device (400), a data reception device (500) and a system (300) including these devices, all implementing various aspects of the aforementioned method.

Abstract: A method for determining a remote timeout parameter in a network comprising a link between a first bus and a third bus. The link is implemented through a first and a second bridge portal connected respectively to the first and the third bus, and is modelized as a second bus connected to the first bus and the third bus through bridges. Upon solicitation to provide its contribution to a timeout for a request subaction, the first bridge portal adds to the timeout contribution the first bridge portal's maximum request subaction processing time and either the link's maximum transmission time of half of the link's maximum transmission time, depending on the location of the destination node of the request subaction.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.

Abstract: A circuit arrangement, program product and method for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter grants access to a first group of devices according to a predetermined sequence. The arbiter then automatically alters the sequence for a second group of devices, granting access to the bus for the second group according to the altered sequence. These features allow the order in which the arbiter sequences through the groups to be automatically varied with respect to each other, diminishing the likelihood of lockout.

Abstract: In a bus system, in accordance with reservations of transfers of isochronous blocks of data and with requests by the node devices for transfers of ones of the isochronous blocks of data and regular blocks of data, a bus manager generates a schedule of the operating rate of a bus channel, the frequency of assignment of the bus channel, and the size of a continuously transferred piece of data on the bus channel for each of the blocks of data, so that the piece of data is transferred at the operating rate of the bus channel as low as possible in each transfer cycle.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to an IDLE state after the electronic device generates error information representing an error of the access wait signal or performs access to the I/O device according to a transition of the access wait signal to a state for determining a delay of access to the I/O device. Therefore, with the method, even when the access wait signal transmitted from the I/O device to the electronic device erroneously maintains a signal state for delaying access to the I/O device, the electronic device can be released automatically from an access delayed state after a predetermined time period.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.