Centralized Bus Arbitration Patents (Class 710/113)
  • Patent number: 10324870
    Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 18, 2019
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10318453
    Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 11, 2019
    Assignee: Marvell World Trade Ltd.
    Inventor: Jerry Hongming Zheng
  • Patent number: 10321464
    Abstract: A management method and apparatus for supporting multiple SIM cards to share an RF processor. The method includes: after receiving a resource request sent by a first baseband communications processor, determining whether the RF processor is authorized be used by a second baseband communications processor in at least a part of a time period required for using the RF processor by the first baseband communications processor; if yes, comparing whether a priority of a type of a first communications service that needs to be performed by the first baseband communications processor is higher than a priority of a type of a second communications service performed by the second baseband communications processor; and if yes, sending an authorization message to the first baseband communications processor and instructing the second baseband communications processor to stop performing the second communications service.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 11, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Wen, Ning Dong, Ning Zhang
  • Patent number: 10310926
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 4, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 10303624
    Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 28, 2019
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Peter Andrew Riocreux, Alessandro Grande
  • Patent number: 10296419
    Abstract: In one aspect, a method includes powering down a target virtual machine (VM), removing the target VM from an inventory of virtual machine hosts after powering down the virtual VM, configuring a shadow VM by assigning an ID to the shadow VM to be the same as the target VM and by attaching a target VMDK to the shadow VM, adding the shadow VM to the inventory and powering up the shadow VM to run no more than a BIOS and to enable access of the target VMDK.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 21, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jehuda Shemer, Assaf Natanzon, Saar Cohen, Ron Cooper, Jonathan Grey
  • Patent number: 10274926
    Abstract: A control system, a safety system, etc., within a process plant may each use one or more state machine function blocks that can be easily integrated into a function block diagram programming environment. Such a state machine function block may include one or more inputs, which may cause a state machine implemented by the state machine function block to identify a next state as well as one or more transition actions to perform in accordance with transitioning from a current state to the next state. Configuration data associated with the transition actions may be retrieved from a database based on the current and next states of the state machine and at least one of the inputs. The state machine function block may also include one or more outputs that are generated based on the state transition.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: April 30, 2019
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Gary K. Law, Godfrey R. Sherriff
  • Patent number: 10255103
    Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 9, 2019
    Assignee: ARM Limited
    Inventors: Chiranjeev Acharya, Arthur Brian Laughton, Sean James Salisbury
  • Patent number: 10243758
    Abstract: An apparatus and method are provided for filtering transactions performed between a master device and a slave device, where each transaction comprises one or more transfers. The apparatus has a first interface for coupling to the master device and a second interface for coupling to the slave device. Routing circuitry is used to route, between the first interface and the second interface, signals representing each transfer. Filtering decision generation circuitry is arranged to perform a combinatorial operation to generate a filtering decision dependent on current values of one or more received input variables. The routing circuitry is then responsive to the filtering decision indicating a block condition for a current transfer, to block the current transfer by preventing one or more of the signals representing that current transfer from being passed between the first interface and the second interface in either direction.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 26, 2019
    Assignee: ARM Limited
    Inventors: Péter Vári, Péter Czakó
  • Patent number: 10241880
    Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 10223312
    Abstract: In an example, there is disclosed a computing apparatus, having: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is higher in order than the first ordinal QoS profile; a slave; a multiplexed interconnect to communicatively couple the first master and second master to the slave with a priority according to the ordinal QoS profiles; and one or more logic elements, including at least one hardware logic element, providing a QoS engine to: determine that the first master has initiated a slave operation via the interconnect; determine that completing the slave operation according to a QoS criterion provided by the second master requires elevated QoS; and promote the first master to a third ordinal QoS profile having an order higher than the second ordinal QoS profile.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 5, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Kaushal Sanghai, Robert E. Peloquin, Thomas C. Ajamian
  • Patent number: 10223308
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Patent number: 10223307
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Patent number: 10223121
    Abstract: A processor includes a decoder, a data return buffer, and an execution unit. The decoder is to decode an instruction for a non-posted load into a decoded instruction for loading data from memory mapped input/output. The execution unit is for executing the decoded instruction. The execution is to start a timer, determine whether the timer exceeds a timeout threshold, allocate an entry in the data return buffer for the load, and determine whether an event arrived. The timer is to measure an amount of time taken to return the non-posted load instruction. The determination whether an event arrived is made in response to at least one of the allocation of the entry for the load, or a determination that the timer exceeds the timeout threshold.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Raanan Sade, Jacob Doweck
  • Patent number: 10204072
    Abstract: In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the address allocation via a query message that is arranged for all bus users. Slave bus users which have already been assigned an address respond to this query message by transmitting a message at their assigned address. Slave bus users which have not yet been assigned an address take measures in response to this query message to be able to transmit on the bus without collisions, and transmit their serial number to the master bus user using these measures. At least the slave bus users which have not yet been assigned an address are assigned a suitable address by the master after receipt of the serial number, and use this address for further communication on the bus.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 12, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ralph Schmidt, Eko-Bono Suprijadi, Eckart Schlottmann, Christian Astor
  • Patent number: 10198360
    Abstract: There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: February 5, 2019
    Assignee: ARM Limited
    Inventor: Alex James Waugh
  • Patent number: 10157625
    Abstract: The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 18, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John A. Tardif, Brian Lloyd Schmidt, Sunil Kumar Vemula, Robert N. Heitkamp
  • Patent number: 10152437
    Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 11, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 10108584
    Abstract: A host apparatus which controls screen capture using a web capture application or a capture application, and a screen capture control method thereof. The host apparatus shares capture areas or saved files using a web capture application through which a screen of a web browser is captured and is compatibly saved or using a capture application through which a desktop screen is captured and is compatibly saved.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: October 23, 2018
    Assignee: S-PRINTING SOLUTION CO., LTD.
    Inventors: Mi Sook Song, Dong Chae Park, Hyung Jong Kang
  • Patent number: 10108456
    Abstract: A method, system, and apparatus are provided for accelerated atomic resource allocation on a multiprocessor platform. In particular, a resource allocation engine (RAE) performs the following: counting available units for each of the one or more resources; parsing a multi-resource ticket (MRT) for a processor, wherein the parsing identifies one or more requested resource types, each resource type being paired with a requested resource units; comparing the multi-resource ticket to one or more resource queues for the requested resource types, wherein the comparing determines an availability status of at least one the requested resource types; and based on the availability status, calculating whether or not all of the requested resource types can be allocated for the processor, wherein the calculating is completed before allocating a next requested resource for a next processor.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 23, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Harsh Jain, Abdulnour Toukmaji
  • Patent number: 10088914
    Abstract: In some examples, input received from an input device, such as a keyboard, is modified by a component associated with an operating system before the input is delivered to an application. For instance, a component associated with the operating system may become registered for modifying input. In some situations, the input is modified based at least in part on metadata associated with the input device. For example, a location of a fingertip on a touch-sensitive display may be used to modify the input before delivery to an application.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 2, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Abzarian, Hirofumi Yamamoto, Youlian Simidjiyski, Alex G Snitkovskiy, Ramachandran Gurumoorthy, Rouella J. Mendonca, Kelli Marie Zielinski, Alice Tang
  • Patent number: 10079049
    Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Taihei Shido
  • Patent number: 10069704
    Abstract: A system for network monitoring and network traffic analysis includes a plurality of network devices and a management station. Each of the plurality of network devices is associated with corresponding ones of a plurality of ports. Each of the plurality of network devices is configured to determine network traffic analysis data associated with a characteristic of network data traversing each of the plurality of ports. The management station is configured to determine a ranking of the plurality of ports based on the network traffic analysis data in response to a search request implicating the characteristic, and is configured to display the plurality of ports based on the ranking.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 4, 2018
    Assignee: CPACKET NETWORKS INC.
    Inventor: Rony Kay
  • Patent number: 10049691
    Abstract: In a disk drive apparatus, a first time period is determined, during which a first head driven by a first actuator will be performing a first disk access operation. A second time period is determined, during which a second head driven by a second actuator will be performing a second disk access operation. The first and second actuators are independently movable such that the first and second disk access operations are capable of being performed in parallel. If it is determined that the second disk access operation will impact servo control of the first disk access operation, at least one of the first and second disk access operations is changed to reduce the impact to the servo control of the first disk access operation.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Vidur Fnu Parkash, Evgeny Kharisov, Josiah Natan Wernow
  • Patent number: 10049052
    Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 14, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ray Charles Marshall, Joachim Fader, Stephan Herrmann
  • Patent number: 10025649
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 17, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 9990229
    Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 5, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dongrui Fan, Xiaochun Ye, Da Wang, Hao Zhang
  • Patent number: 9984014
    Abstract: The present invention provides a technique for further improving the processing efficiency in a semiconductor device that arbitrates data transfer between a plurality of bus masters and a plurality of bus slaves. A bus control circuit controls data transfer in an address bus and a data bus between a plurality of bus masters and a plurality of bus slaves. The bus control circuit obtains access information representing the bus slave that each of the bus masters accesses on the basis of address signals output from the bus masters. The bus control circuit obtains busy information representing whether or not each bus slave is in a busy state. In the case where the bus masters compete with each other when accessing a bus slave, the bus control circuit arbitrates access from each bus master to the bus slave that is not in a busy state in accordance with the priority set for each bus master on the basis of the access information and the busy information.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 29, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Naoshi Ishikawa
  • Patent number: 9965273
    Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 8, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Yamasaki, Hideyuki Noda, Kan Murata
  • Patent number: 9910807
    Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
  • Patent number: 9847952
    Abstract: Systems and methods for automatic purchasing, reserving and/or provisioning of a wavelength bandwidth block are disclosed. A user may access a web page, such as an interactive web-portal, to provide bandwidth data and corresponding ordering information for reserving a particular amount of bandwidth capacity on a telecommunications network. Subsequently, the customer's may access and the bandwidth blocks to increase/decrease and/or activate/deactivate portions of the reserved bandwidth capacity as needed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 19, 2017
    Assignee: Level 3 Communications, LLC
    Inventors: Kelly R. Crosby, Benjamin W. Garrard, Jeff King, Scott A. Nusz, Monisha Merchant
  • Patent number: 9842056
    Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Patent number: 9800738
    Abstract: A system for monitoring a building having one or more microphones coupled to a telephone includes a detector configured to detect a triggering event within the building and transmit an activating signal when the triggering event is detected, and a control module configured to receive the activating signal from the detector. The control module is programmed to activate at least one of the one or more microphones to monitor sound when the activating signal is received.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: October 24, 2017
    Inventors: Edward S. Boyden, Jesse R. Cheatham, III, William D. Duncan, Bran Ferren, Roderick A. Hyde, Muriel Y. Ishikawa, Jordin T. Kare, Stephen L. Malaska, Nathan P. Myhrvold, David B. Tuckerman, Lowell L. Wood, Jr.
  • Patent number: 9741450
    Abstract: A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: August 22, 2017
    Assignee: INSIDE SECURE
    Inventor: Salwa Bouzekri Alami
  • Patent number: 9733694
    Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Krishna V. S. S. S. R. Vanka, Sravan Kumar Ambapuram, Shirish Kumar Agarwal, Shih-Hsin Jason Hu
  • Patent number: 9703710
    Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dharmesh Parikh, Gopikrishnan Viswanadhan
  • Patent number: 9703354
    Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 11, 2017
    Assignee: Apple Inc.
    Inventors: Jong-Suk Lee, Daniel C. Murray, Wei-Han Lien
  • Patent number: 9703711
    Abstract: A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dharmesh Parikh, Gopikrishnan Viswanadhan
  • Patent number: 9639490
    Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
  • Patent number: 9612929
    Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 9594696
    Abstract: Various systems and methods to generate automatically a procedure operative to distributively process a plurality of data sets stored on a plurality of memory modules. Under the instruction of the automatically generated procedure, compute elements request data sets relevant to a particular task, such data sets are fetched from memory modules by data interfaces which provide such data sets to the requesting compute elements, and the compute elements then process the received data sets until the task is completed. Relevant data sets are fetched and processed asynchronously, which means that the relevant data sets need not be fetched and processed in any particular order.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 14, 2017
    Assignee: Parallel Machines Ltd.
    Inventors: Avner Braverman, Michael Adda, Lior Amar, Lior Khermosh, Eli Finer, Gal Zuckerman
  • Patent number: 9563579
    Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Ravishankar Iyer, Quang T. Le, Ravi Kolagotla, Ioannis T. Schoinas, Jose S. Niell
  • Patent number: 9535860
    Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Blaise Fanning, Ramadass Nagarajan, Jose S. Niell, Debra Bernstein, Deepak Limaye, Ioannis T. Schoinas, Ravishankar Iyer
  • Patent number: 9477624
    Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: October 25, 2016
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Sundeep Chandhoke
  • Patent number: 9460036
    Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: October 4, 2016
    Assignee: National Instruments Corporation
    Inventor: Sundeep Chandhoke
  • Patent number: 9405715
    Abstract: In a method for managing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to an SAS expander storage system through a redundant array of independent disks (RAID) card. The SAS expander storage system includes a first switch device, a first SAS expander, a second SAS expander, a second switch, a flash memory, and hard disk drives. The method controls the first switch device to switch the RAID card from the first SAS expander to the second SAS expander when the first SAS expander fails to function, controls the second switch device to switch the flash memory from the first SAS expander to the second SAS expander, and controls the first switch device to connect each of the hard disk drives to the second SAS expander.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 2, 2016
    Assignee: Zijilai Innovative Services Co., Ltd.
    Inventor: Chih-Huang Wu
  • Patent number: 9398080
    Abstract: Provided is an information processing device constituting at least a part of a communication system. The information processing device includes a master unit connected to a first communication line, and at least one slave unit connected to the master unit via a second communication line. The master unit includes: a first communication unit for transmitting/receiving data with another device via the first communication line in every predetermined cycle; a second communication unit for transmitting/receiving data with the slave unit via the second communication line in a time period shorter than the cycle; and an update unit for, after preceding data is received via the first communication line, updating data with the slave unit via the second communication line before arrival of subsequent data corresponding to the next cycle.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 19, 2016
    Assignee: OMRON Corporation
    Inventor: Seiji Mizutani
  • Patent number: 9367499
    Abstract: A system on chip (SOC) include at least one slave device, a plurality of master devices, a plurality of service controllers and an interconnect device. The master devices generate requests to demand services from the slave device, respectively. The service controllers generate urgent information signals and priority information signals for each of the master devices. The interconnect device is coupled to the slave device and the master devices through respective channels. The interconnect device performs an arbitrating operation on the requests based on the priority information signals and controls request flows between the slave device and the master devices based on the urgent information signals.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Geun Yun, Bub-Chul Jeong, Lingling Liao
  • Patent number: 9348645
    Abstract: A method and an apparatus for priority donations among different processes are described. A first process running with a first priority may receive a request from a second process running with a second priority to perform a data processing task for the second process. A dependency relationship may be identified between the first process and a third process running with a third priority performing separate data processing task. The dependency relationship may indicate that the data processing task is to be performed via the first process subsequent to completion of the separate data processing task via the third process. The third process may be updated with the second priority to complete the separate data processing task. The first process may perform the data processing task with the second priority for the second process.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 24, 2016
    Assignee: Apple Inc.
    Inventors: James Michael Magee, Russell A. Blaine, Daniel A. Chimene, James McIlree, Vishal Patel, Daniel Andreas Steffen, Kevin James Van Vechten
  • Patent number: 9323702
    Abstract: In the verification of an integrated circuit design having arbitration logic which controls access from a plurality of requesters to a shared resource, an arbitration stall simulation mechanism selects one or more of the requesters for an extended stall procedure, and when a global counter expires, applies stalls having controlled durations to the selected requesters. The controlled durations can be randomly generated time periods within a preset range. The number of requesters subjected to the extended stall procedure can be randomly selected based on a predetermined percentage of requesters to stall. Local (requester-specific) code can perform the stalls for respective requesters using a stall duration inputs. The requester-specific codes can carry out the stalls using application program interface calls to override respective arbiter inputs from the requesters.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: David W. Cummings, Jonathan R. Jackson, Guy L. Guthrie