Abstract: The device described herein, which provides an interface between a plurality of master devices and a slave device, includes: a first timer configured to begin timing when a first access request is received from a first master device via a bus, and to be reset when a semaphore is allocated to the first master device; a second timer configured to begin timing when a second access request is received from a second master device via the bus, and to be reset when a semaphore is allocated to the second master device; and a controller configured to provide a first message to the first master device via the bus when a first expiration interval is measured by the first timer.

Abstract: A cache usage indicator calculation apparatus (1) includes: a memory for reading and writing data; a cache that can be accessed more rapidly than the memory; a central processing unit configured to read and write from and to the memory and the cache and execute processing; a usage state measurement unit configured to measure a usage state of the cache used by an application (11a, 11b) executed by the central processing unit; a performance measurement unit configured to measure a cache sensitivity and/or a cache pollutivity relating to an application (11a, 11b); and an indicator calculation unit configured to, based on a performance deterioration of a pre-selected plurality of applications and the usage state of the cache, calculate an indicator for the cache sensitivity and/or an indicator for the cache pollutivity of each application.

Abstract: Worker threads allocate at least some recycled cache slots of a local portion of a shared memory to the compute node to which the memory portion is local. More specifically, the recycled cache slots are allocated prior to receipt of the IO that the recycled cache slot will be used to service. The allocated recycled cache slots are added to primary queues of each compute node. If a primary queue is full then the worker thread adds the recycled cache slot, unallocated, to a secondary queue. Cache slots in the secondary queue can be claimed by any compute node associated with the shared memory. Cache slots in the primary queue can be used by the local compute node without sending test and set messages via the fabric that interconnects the compute nodes, thereby improving IO latency.

Abstract: An electronic device with a connector supporting multiple connection standards includes the connector, a first multiplexer circuit, a processor and a controller. The connector includes a detection pin and at least one signal pin. The first multiplexer circuit is coupled to the at least one signal pin. The processor is coupled to the first multiplexer circuit. The controller monitors the detection pin. The first multiplexer circuit electrically connects the at least one signal pin to the controller. Upon detecting a hot-plug signal occurring at the detection pin, the controller issues a confirmation command via the first multiplexer circuit and the at least one signal pin to request a reply of a device signal. Upon receiving the device signal, the controller controls the first multiplexer circuit according to the device signal to electrically connect the at least one signal pin to the processor or the controller.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.

Abstract: A bus arbitration circuit includes a first bus port, a second bus port, a first output circuit connected to the first bus port, a second output circuit connected to the second bus port, a control circuit, and a switch circuit. The control circuit includes a first input port, a second input port, a control signal output port, and an output port. The first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port to an input port of the first output circuit. The switch circuit has an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of a host bus is outputted to an input port of the second output circuit.

Abstract: Channel availability information associated with data traffic between a Master and a Slave within an interconnection network (“ICN”) in a System-on-Chip (“SoC”) is monitored by a channel performance monitor in order to improve the performance of the ICN. The channel availability information is fed back to certain Masters to control their data traffic into the ICN. The channel performance monitor monitors and evaluates the data traffic handled by switches within the ICN that can potentially interfere with communication paths between particular Masters and Slaves, and control the initiation of data traffic from predetermined Masters.

Abstract: The present disclosure relates to a bidirectional communication circuit for bidirectional communication between a first differential wired network and a second differential wired network and a related method of operating the bidirectional communication circuit. In particular, the present disclosure relates to a bidirectional communication circuit designed to prevent timing glitches and simultaneous transmission of data from the first network to the second network and from the second network to the first network.

Abstract: Arobot controlling method, system and warehouse-transport robot, which relates to the field of robot control. The method comprises: receiving, by a chassis controller, an information synchronization instruction sent by a main controller; performing, by the chassis controller, information synchronization with a rotation controller according to the information synchronization instruction; sending, by the chassis controller, a synchronous rotation instruction to the rotation controller, and controlling a chassis motor to drive a robot chassis to rotate at a predetermined angular velocity relative to the ground; controlling, by the rotation controller, a rotation motor to drive a robot rotation mechanism to synchronously rotate at an angular velocity relative to the rotating the robot chassis according to the synchronous rotation instruction.

Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.

Abstract: A bridge chip with a function of expanding external devices and an associated expansion method are provided, wherein the bridge chip may include at least one transmission interface, a bridge control unit and a connecting port. The transmission interface may be configured to make at least one external device outside the bridge chip couple to the bridge chip; the bridge control unit is coupled to the transmission interface, and may be configured to control priority of the external device for performing data transmission; and the connecting port is coupled to the bridge control unit, and may be configured to make the bridge chip couple to a host device, to allow the host device to perform data transmission with the external device. More particularly, a number of the external device is expandable.

Abstract: A method may include determining a set of parameters of a first wireless network that includes a first radio configured to communicate according to a first communication protocol on a plurality of overlapping channels. The method may also include determining one or more operating parameters of a second radio based on the set of parameters of the first wireless network, the second radio included in a second wireless network, co-located with the first radio, and configured to communicate according to a second communication protocol on the plurality of overlapping channels. The method may also include operating the second radio in the second wireless network according to the one or more operating parameters.

Abstract: The present invention discloses a method for managing priority-arbitrated access to a set of one or more computational engines of a physical computing device. The method includes providing a multiplexer module and a network bus in the physical computing device, wherein the multiplexer module is connected to the network bus. The method further includes receiving, by the multiplexer module, a first data processing request from a driver and inferring, by the multiplexer module, a first priority class from the first data processing request according to at least one property of the first data processing request. The method further includes manipulating, by the multiplexer module, a priority according to which the physical computing device handles data associated with the first data processing request in relation to data associated with other data processing requests, wherein the priority is determined by the first priority class.

Abstract: An apparatus includes a first memory, processing units that access the first memory, and a counter that, for each period of a sequence of periods, holds an indication of accesses to the first memory during the period; and control logic that, for each period of the sequence of periods, monitors the indication to determine whether it exceeds the threshold and, if so, stalls the processing units from accessing the first memory for a remaining portion of the period.

Abstract: A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.

Abstract: A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

Abstract: A method, an electronic device, and computer readable medium is provided. The method includes identifying a plurality of virtual objects for output to a display of the electronic device, including a priority level for each of the plurality of virtual objects. The method also includes comparing the priority level of an object of the plurality of virtual objects to the priority level associated with another object of the plurality of virtual objects to determine whether to modify an appearance of either object. In response to determining to modify the appearance of either object, the method further includes modifying the appearance of either. The method additionally includes rendering the plurality of virtual objects on the display of the electronic device.

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

Abstract: A method for bandwidth allocation includes receiving requests for bus channel access from two or more master devices. Next, the method selects one of priority-based allocation or credit-based allocation. Upon selecting the priority-based allocation, the method grants bus channel access based on pre-assigned priorities for bus channel access. Upon selecting credit-based allocation, the method grants bus channel access based on pre-allocated credits for bus channel access, and the method decrements the credit from the master device that has been granted bus channel access.

Abstract: A system for sharing a data handling resource among a plurality of data producers. In some embodiments, the system includes: a data-handling resource, a first data generator, a first data connection, from the first data generator to the data-handling resource, a second data generator, a second data connection, from the second data generator to the first data generator, and a token-forwarding connection between the first data generator and the second data generator. The token-forwarding connection may be configured to transfer a token between the first data generator and the second data generator. The first data generator may be configured: to generate a first data stream, to receive a second data stream from the second data generator through the second data connection, and to send data selected from the first data stream and the second data stream.

Abstract: Techniques and systems are disclosed for allocating resources between two or more resource pools in a computing resource environment. Allocation may be realized by identifying a first resource in the first resource pool; creating a second resource based on at least a portion of the identified first resource; adding the created second resource to the second resource pool; identifying at least a portion of the added second resource as unused with respect to the second resource pool; creating a third resource based on the identified portion of the second resource; and adding the created third resource to a resource pool other than the second resource pool.

Abstract: A data access system has host computers having front-end controllers nFE_SAN connected via a bus or network interconnect to back-end storage controllers nBE_SAN, and physical disk drives connected via network interconnect to the nBE_SANs to provide a distributed, high performance, policy based or dynamically reconfigurable, centrally managed, data storage acceleration system. The hardware and software architectural solutions eliminate BE_SAN controller bottlenecks and improve performance and scalability. In an embodiment, the nBE_SAN (BE_SAN) firmware recognize controller overload conditions, informs Distributed Resource Manager (DRM), and, based on the DRM provided optimal topology information, delegates part of its workload to additional controllers. The nFE_SAN firmware and additional hardware using functionally independent and redundant CPUs and memory that mitigate single points of failure and accelerates write performance.

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.

Abstract: A USB management system using a USB relay device includes a management terminal having a management database for recording management information of a USB client registered in advance. The USB relay device has a connection switching unit for switching a connection state between a first connector portion to which the USB client is connected and a second connector portion which is connected to a USB host controller. When the USB client is connected to the first connector portion, the USB relay device reads management information of the USB client and transmits the management information to the management terminal, and the management terminal inquires of the management database about the management information of the USB client transmitted from the USB relay device, compares the management information with the management information of the USB client registered in advance, and determines the connection state by the connection switching unit.

Abstract: A device to detect a select state and initiate a function based on detecting the select state. The device receives a signal sent over a bus to be used to communicate between one component of one unit and another component of another unit. The bus is defined based on a selected protocol, and the device is configured to communicate with the other component of the other unit. A determination is made as to whether the signal represents a select state, the select state being an unintended state of the bus. Based on determining that the signal represents the select state, a function is initiated.

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: Upon receiving a request (203) in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device (200) allocates, to the ordered request, entries in a first ordered queue (e.g., 211) and a first static queue (e.g., 213) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g., 217) and a second static queue (e.g., 218) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue (211) for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.

Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.

Abstract: System and method for aggressive credit waiting in a high performance computing environment. In accordance with an embodiment, systems and methods can provide for an indexed matrix of credit wait policies between ports within a single switch. In addition, systems and methods can provide for an array of credit wait polices at an egress port from a switch, the array being indexed by virtual lane.

Abstract: Disclosed herein is an apparatus for controlling an embedded device, through which the embedded device may be controlled in a host computer in real time. The apparatus for controlling an embedded device includes a host computer connected with a monitor, a mouse, and a keyboard; an embedded device; and a connection module for connecting the host computer with the embedded device such that a first task window for controlling the host computer and a second task window for controlling the embedded device are displayed on the monitor.

Abstract: A method for processing a token at a local device in a distributed arbitration system includes: receiving a first signal from first device indicating a request for access to a shared resource; receiving an indicator from a processing component of the local device indicating whether the processing component requires access to the shared resource; receiving a second signal from the local device, where a component of second signal indicates whether the local device has greater priority than another device in the set of one or more devices to access the shared resource; receiving a token from the chain network, the token granting a device access to the shared resource; determining a disposition of the token using the first signal and the second signal; disposing the token to allocate the shared resource to a device in response to the determined disposition; and updating the second signal in response to the determining.

Abstract: A computer system and a bus arbitration method are provided. The computer system includes a bus, a plurality of master devices, and a slave device. The master devices and the slave device are coupled to the bus. Each of the master devices determines the number of the operating master devices through the bus. When a first master device intends to access the slave device, the first master device performs a bus arbitration on the slave device and attempts to access the slave device. If the slave device is accessed successfully, the first master device does not participate in N number of times of subsequent bus arbitrations. If the slave device is accessed unsuccessfully, the first master device determines whether the slave device is released. If the slave device is released, the first master device performs a next bus arbitration and attempts to access the slave device continuously.

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. A controller is configured to receive a storage command on a first port of a storage device. A controller is configured to queue a received storage command as an entry in a command queue. An entry in a command queue indicates a type of a received storage command. A controller is configured to service a received storage command from a command queue on a second port of a storage device based on a type of the received storage command indicated by an entry in the command queue associated with the received storage command.

Abstract: A network on a chip (NoC) testing interface (NTI) includes a plurality of switches whose ports are coupled to respective endpoints. In one embodiment, the ports and endpoints are coupled to a shared bus that starts and terminates at a root device. The endpoints are assigned unique address which the NTI uses to select one of the endpoints so that test data is forwarded to a device under test (DUT) coupled to the endpoint. In one embodiment, the endpoints include selection logic for determining whether the endpoint has been selected, and if so, forwarding test data to the DUT. For example, if the endpoint receives a data vector on the bus which has an address that matches the unique address of the endpoint, the selection logic forwards the test data contained in subsequently received data vectors to the DUT until a different address is received.

Abstract: A bus control circuit includes: a plurality of queues that each include a plurality of entries for storing data, a first read pointer, and a check pointer set to indicate a same entry as an entry indicated by the first read pointer, and each store data on a First in, First out basis; a plurality of first arbitration circuits that receive, in a divided manner, arbitration participation signals from the plurality of queues, each arbitrate the received plurality of arbitration participation signals, and each output one of the plurality of arbitration participation signals; a plurality of buffers that each store, on the First in, First out basis, the arbitration participation signals output from the respective first arbitration circuits; and a second arbitration circuit that arbitrates the arbitration participation signals output from the plurality of buffers and outputs an arbitration result signal corresponding to one of the plurality of queues.

Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.

Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.

Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.

Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.

Abstract: A management method and apparatus for supporting multiple SIM cards to share an RF processor. The method includes: after receiving a resource request sent by a first baseband communications processor, determining whether the RF processor is authorized be used by a second baseband communications processor in at least a part of a time period required for using the RF processor by the first baseband communications processor; if yes, comparing whether a priority of a type of a first communications service that needs to be performed by the first baseband communications processor is higher than a priority of a type of a second communications service performed by the second baseband communications processor; and if yes, sending an authorization message to the first baseband communications processor and instructing the second baseband communications processor to stop performing the second communications service.

Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to

Abstract: In one aspect, a method includes powering down a target virtual machine (VM), removing the target VM from an inventory of virtual machine hosts after powering down the virtual VM, configuring a shadow VM by assigning an ID to the shadow VM to be the same as the target VM and by attaching a target VMDK to the shadow VM, adding the shadow VM to the inventory and powering up the shadow VM to run no more than a BIOS and to enable access of the target VMDK.

Abstract: A control system, a safety system, etc., within a process plant may each use one or more state machine function blocks that can be easily integrated into a function block diagram programming environment. Such a state machine function block may include one or more inputs, which may cause a state machine implemented by the state machine function block to identify a next state as well as one or more transition actions to perform in accordance with transitioning from a current state to the next state. Configuration data associated with the transition actions may be retrieved from a database based on the current and next states of the state machine and at least one of the inputs. The state machine function block may also include one or more outputs that are generated based on the state transition.