Centralized Bus Arbitration Patents (Class 710/113)
  • Patent number: 10853304
    Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-yeon Jeon, Jae-Gon Lee, Youn-Sik Choi, Min-joung Lee, Jin-ook Song
  • Patent number: 10810039
    Abstract: An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 20, 2020
    Assignee: ARM Limited
    Inventors: Stephan Diestelhorst, Matthew James Horsnell
  • Patent number: 10789117
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 29, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 10747649
    Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 18, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Matthias Fromme, Jochen Sauer, Matthias Schmitz
  • Patent number: 10719468
    Abstract: A USB management system using a USB relay device includes a management terminal having a management database for recording management information of a USB client registered in advance. The USB relay device has a connection switching unit for switching a connection state between a first connector portion to which the USB client is connected and a second connector portion which is connected to a USB host controller. When the USB client is connected to the first connector portion, the USB relay device reads management information of the USB client and transmits the management information to the management terminal, and the management terminal inquires of the management database about the management information of the USB client transmitted from the USB relay device, compares the management information with the management information of the USB client registered in advance, and determines the connection state by the connection switching unit.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: July 21, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kei Takezawa, Takuma Nishimura, Hideki Tonooka
  • Patent number: 10649933
    Abstract: A device to detect a select state and initiate a function based on detecting the select state. The device receives a signal sent over a bus to be used to communicate between one component of one unit and another component of another unit. The bus is defined based on a selected protocol, and the device is configured to communicate with the other component of the other unit. A determination is made as to whether the signal represents a select state, the select state being an unintended state of the bus. Based on determining that the signal represents the select state, a function is initiated.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark L. DeMarie, Robert B. Schlak, David Fratzke
  • Patent number: 10628340
    Abstract: Upon receiving a request (203) in an initiator interface protocol identifying information to be returned in-order, an integrated circuit protocol bridge circuit device (200) allocates, to the ordered request, entries in a first ordered queue (e.g., 211) and a first static queue (e.g., 213) for the initiator interface protocol, generates a plurality of split target requests in a target interface protocol from the ordered request, and allocates the plurality of split target requests to entries in a second ordered queue (e.g., 217) and a second static queue (e.g., 218) for the target interface protocol, so that, upon receiving a plurality of out-of-order target responses, an allocated entry in the first ordered queue (211) for the first ordered initiator request is deleted only after a plurality of counter fields in the first static queue indicate that target responses have been received for all of the plurality of split target requests.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Prakashkumar G. Makwana, Gus P. Ikonomopoulos
  • Patent number: 10628360
    Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Manabu Koike
  • Patent number: 10621132
    Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Ian A. Swarbrick, Kin Yip Sit
  • Patent number: 10616118
    Abstract: System and method for aggressive credit waiting in a high performance computing environment. In accordance with an embodiment, systems and methods can provide for an indexed matrix of credit wait policies between ports within a single switch. In addition, systems and methods can provide for an array of credit wait polices at an egress port from a switch, the array being indexed by virtual lane.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: April 7, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Bjørn Dag Johnsen, Arvind Srinivasan, Shimon Muller
  • Patent number: 10585495
    Abstract: Disclosed herein is an apparatus for controlling an embedded device, through which the embedded device may be controlled in a host computer in real time. The apparatus for controlling an embedded device includes a host computer connected with a monitor, a mouse, and a keyboard; an embedded device; and a connection module for connecting the host computer with the embedded device such that a first task window for controlling the host computer and a second task window for controlling the embedded device are displayed on the monitor.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 10, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seok-Jin Yoon, Do-Hyung Kim, Cheol Ryu, Jae-Ho Lee, Hyung-Seok Lee, Hyun-Woo Cho, Kyung-Hee Lee
  • Patent number: 10579428
    Abstract: A method for processing a token at a local device in a distributed arbitration system includes: receiving a first signal from first device indicating a request for access to a shared resource; receiving an indicator from a processing component of the local device indicating whether the processing component requires access to the shared resource; receiving a second signal from the local device, where a component of second signal indicates whether the local device has greater priority than another device in the set of one or more devices to access the shared resource; receiving a token from the chain network, the token granting a device access to the shared resource; determining a disposition of the token using the first signal and the second signal; disposing the token to allocate the shared resource to a device in response to the determined disposition; and updating the second signal in response to the determining.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Howe, Harrison MinHo McCreary
  • Patent number: 10581973
    Abstract: A computer system and a bus arbitration method are provided. The computer system includes a bus, a plurality of master devices, and a slave device. The master devices and the slave device are coupled to the bus. Each of the master devices determines the number of the operating master devices through the bus. When a first master device intends to access the slave device, the first master device performs a bus arbitration on the slave device and attempts to access the slave device. If the slave device is accessed successfully, the first master device does not participate in N number of times of subsequent bus arbitrations. If the slave device is accessed unsuccessfully, the first master device determines whether the slave device is released. If the slave device is released, the first master device performs a next bus arbitration and attempts to access the slave device continuously.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: March 3, 2020
    Assignee: Wiwynn Corporation
    Inventors: Cheng-Kuang Hsieh, Chung-Fu Huang
  • Patent number: 10572390
    Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 25, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
  • Patent number: 10528267
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queueing commands for storage operations. An apparatus includes a command queue configured to queue storage commands received at a storage device and a controller for the storage device. A controller is configured to receive a storage command on a first port of a storage device. A controller is configured to queue a received storage command as an entry in a command queue. An entry in a command queue indicates a type of a received storage command. A controller is configured to service a received storage command from a command queue on a second port of a storage device based on a type of the received storage command indicated by an entry in the command queue associated with the received storage command.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nidhi Batra, Ravindra Arjun Madpur, Amandeep Kaur
  • Patent number: 10502785
    Abstract: A network on a chip (NoC) testing interface (NTI) includes a plurality of switches whose ports are coupled to respective endpoints. In one embodiment, the ports and endpoints are coupled to a shared bus that starts and terminates at a root device. The endpoints are assigned unique address which the NTI uses to select one of the endpoints so that test data is forwarded to a device under test (DUT) coupled to the endpoint. In one embodiment, the endpoints include selection logic for determining whether the endpoint has been selected, and if so, forwarding test data to the DUT. For example, if the endpoint receives a data vector on the bus which has an address that matches the unique address of the endpoint, the selection logic forwards the test data contained in subsequently received data vectors to the DUT until a different address is received.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 10, 2019
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10496564
    Abstract: A bus control circuit includes: a plurality of queues that each include a plurality of entries for storing data, a first read pointer, and a check pointer set to indicate a same entry as an entry indicated by the first read pointer, and each store data on a First in, First out basis; a plurality of first arbitration circuits that receive, in a divided manner, arbitration participation signals from the plurality of queues, each arbitrate the received plurality of arbitration participation signals, and each output one of the plurality of arbitration participation signals; a plurality of buffers that each store, on the First in, First out basis, the arbitration participation signals output from the respective first arbitration circuits; and a second arbitration circuit that arbitrates the arbitration participation signals output from the plurality of buffers and outputs an arbitration result signal corresponding to one of the plurality of queues.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 3, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Takashi Nakao
  • Patent number: 10475501
    Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Yeon Jeon, Ah Chan Kim, Min Joung Lee, Youn-Sik Choi
  • Patent number: 10446200
    Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 10324870
    Abstract: A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 18, 2019
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10321464
    Abstract: A management method and apparatus for supporting multiple SIM cards to share an RF processor. The method includes: after receiving a resource request sent by a first baseband communications processor, determining whether the RF processor is authorized be used by a second baseband communications processor in at least a part of a time period required for using the RF processor by the first baseband communications processor; if yes, comparing whether a priority of a type of a first communications service that needs to be performed by the first baseband communications processor is higher than a priority of a type of a second communications service performed by the second baseband communications processor; and if yes, sending an authorization message to the first baseband communications processor and instructing the second baseband communications processor to stop performing the second communications service.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 11, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Wen, Ning Dong, Ning Zhang
  • Patent number: 10318453
    Abstract: Systems and methods for transmitting a group of interrupts across nodes are provided. A first interrupt signal, comprising a first group of interrupts, is received, with a first node, from a second node. A second interrupt signal, comprising a second group of interrupts, is received, from storage circuitry of the first node, the second interrupt signal represents an interrupt signal received prior to the first interrupt signal. The first interrupt signal is combined with the second interrupt signal using a function to generate a combined interrupt signal. The second interrupt signal is compared to the combined interrupt signal to detect a change in a first bit position of the second interrupt signal. In response to detecting that the first bit position has changed to become asserted, an interrupt process corresponding to the first bit position is performed. The combined signal is stored in place of the second interrupt signal.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 11, 2019
    Assignee: Marvell World Trade Ltd.
    Inventor: Jerry Hongming Zheng
  • Patent number: 10310926
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 4, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 10303624
    Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 28, 2019
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Peter Andrew Riocreux, Alessandro Grande
  • Patent number: 10296419
    Abstract: In one aspect, a method includes powering down a target virtual machine (VM), removing the target VM from an inventory of virtual machine hosts after powering down the virtual VM, configuring a shadow VM by assigning an ID to the shadow VM to be the same as the target VM and by attaching a target VMDK to the shadow VM, adding the shadow VM to the inventory and powering up the shadow VM to run no more than a BIOS and to enable access of the target VMDK.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 21, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jehuda Shemer, Assaf Natanzon, Saar Cohen, Ron Cooper, Jonathan Grey
  • Patent number: 10274926
    Abstract: A control system, a safety system, etc., within a process plant may each use one or more state machine function blocks that can be easily integrated into a function block diagram programming environment. Such a state machine function block may include one or more inputs, which may cause a state machine implemented by the state machine function block to identify a next state as well as one or more transition actions to perform in accordance with transitioning from a current state to the next state. Configuration data associated with the transition actions may be retrieved from a database based on the current and next states of the state machine and at least one of the inputs. The state machine function block may also include one or more outputs that are generated based on the state transition.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: April 30, 2019
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Gary K. Law, Godfrey R. Sherriff
  • Patent number: 10255103
    Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 9, 2019
    Assignee: ARM Limited
    Inventors: Chiranjeev Acharya, Arthur Brian Laughton, Sean James Salisbury
  • Patent number: 10243758
    Abstract: An apparatus and method are provided for filtering transactions performed between a master device and a slave device, where each transaction comprises one or more transfers. The apparatus has a first interface for coupling to the master device and a second interface for coupling to the slave device. Routing circuitry is used to route, between the first interface and the second interface, signals representing each transfer. Filtering decision generation circuitry is arranged to perform a combinatorial operation to generate a filtering decision dependent on current values of one or more received input variables. The routing circuitry is then responsive to the filtering decision indicating a block condition for a current transfer, to block the current transfer by preventing one or more of the signals representing that current transfer from being passed between the first interface and the second interface in either direction.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 26, 2019
    Assignee: ARM Limited
    Inventors: Péter Vári, Péter Czakó
  • Patent number: 10241880
    Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor
  • Patent number: 10223312
    Abstract: In an example, there is disclosed a computing apparatus, having: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is higher in order than the first ordinal QoS profile; a slave; a multiplexed interconnect to communicatively couple the first master and second master to the slave with a priority according to the ordinal QoS profiles; and one or more logic elements, including at least one hardware logic element, providing a QoS engine to: determine that the first master has initiated a slave operation via the interconnect; determine that completing the slave operation according to a QoS criterion provided by the second master requires elevated QoS; and promote the first master to a third ordinal QoS profile having an order higher than the second ordinal QoS profile.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 5, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Kaushal Sanghai, Robert E. Peloquin, Thomas C. Ajamian
  • Patent number: 10223308
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Patent number: 10223307
    Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Sascha Junghans, Matthias Klein, Eric N. Lais
  • Patent number: 10223121
    Abstract: A processor includes a decoder, a data return buffer, and an execution unit. The decoder is to decode an instruction for a non-posted load into a decoded instruction for loading data from memory mapped input/output. The execution unit is for executing the decoded instruction. The execution is to start a timer, determine whether the timer exceeds a timeout threshold, allocate an entry in the data return buffer for the load, and determine whether an event arrived. The timer is to measure an amount of time taken to return the non-posted load instruction. The determination whether an event arrived is made in response to at least one of the allocation of the entry for the load, or a determination that the timer exceeds the timeout threshold.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Ido Ouziel, Raanan Sade, Jacob Doweck
  • Patent number: 10204072
    Abstract: In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the address allocation via a query message that is arranged for all bus users. Slave bus users which have already been assigned an address respond to this query message by transmitting a message at their assigned address. Slave bus users which have not yet been assigned an address take measures in response to this query message to be able to transmit on the bus without collisions, and transmit their serial number to the master bus user using these measures. At least the slave bus users which have not yet been assigned an address are assigned a suitable address by the master after receipt of the serial number, and use this address for further communication on the bus.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 12, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ralph Schmidt, Eko-Bono Suprijadi, Eckart Schlottmann, Christian Astor
  • Patent number: 10198360
    Abstract: There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: February 5, 2019
    Assignee: ARM Limited
    Inventor: Alex James Waugh
  • Patent number: 10157625
    Abstract: The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 18, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John A. Tardif, Brian Lloyd Schmidt, Sunil Kumar Vemula, Robert N. Heitkamp
  • Patent number: 10152437
    Abstract: A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: December 11, 2018
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Patent number: 10108584
    Abstract: A host apparatus which controls screen capture using a web capture application or a capture application, and a screen capture control method thereof. The host apparatus shares capture areas or saved files using a web capture application through which a screen of a web browser is captured and is compatibly saved or using a capture application through which a desktop screen is captured and is compatibly saved.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: October 23, 2018
    Assignee: S-PRINTING SOLUTION CO., LTD.
    Inventors: Mi Sook Song, Dong Chae Park, Hyung Jong Kang
  • Patent number: 10108456
    Abstract: A method, system, and apparatus are provided for accelerated atomic resource allocation on a multiprocessor platform. In particular, a resource allocation engine (RAE) performs the following: counting available units for each of the one or more resources; parsing a multi-resource ticket (MRT) for a processor, wherein the parsing identifies one or more requested resource types, each resource type being paired with a requested resource units; comparing the multi-resource ticket to one or more resource queues for the requested resource types, wherein the comparing determines an availability status of at least one the requested resource types; and based on the availability status, calculating whether or not all of the requested resource types can be allocated for the processor, wherein the calculating is completed before allocating a next requested resource for a next processor.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 23, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Harsh Jain, Abdulnour Toukmaji
  • Patent number: 10088914
    Abstract: In some examples, input received from an input device, such as a keyboard, is modified by a component associated with an operating system before the input is delivered to an application. For instance, a component associated with the operating system may become registered for modifying input. In some situations, the input is modified based at least in part on metadata associated with the input device. For example, a location of a fingertip on a touch-sensitive display may be used to modify the input before delivery to an application.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: October 2, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Abzarian, Hirofumi Yamamoto, Youlian Simidjiyski, Alex G Snitkovskiy, Ramachandran Gurumoorthy, Rouella J. Mendonca, Kelli Marie Zielinski, Alice Tang
  • Patent number: 10079049
    Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 18, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Taihei Shido
  • Patent number: 10069704
    Abstract: A system for network monitoring and network traffic analysis includes a plurality of network devices and a management station. Each of the plurality of network devices is associated with corresponding ones of a plurality of ports. Each of the plurality of network devices is configured to determine network traffic analysis data associated with a characteristic of network data traversing each of the plurality of ports. The management station is configured to determine a ranking of the plurality of ports based on the network traffic analysis data in response to a search request implicating the characteristic, and is configured to display the plurality of ports based on the ranking.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: September 4, 2018
    Assignee: CPACKET NETWORKS INC.
    Inventor: Rony Kay
  • Patent number: 10049691
    Abstract: In a disk drive apparatus, a first time period is determined, during which a first head driven by a first actuator will be performing a first disk access operation. A second time period is determined, during which a second head driven by a second actuator will be performing a second disk access operation. The first and second actuators are independently movable such that the first and second disk access operations are capable of being performed in parallel. If it is determined that the second disk access operation will impact servo control of the first disk access operation, at least one of the first and second disk access operations is changed to reduce the impact to the servo control of the first disk access operation.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 14, 2018
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Vidur Fnu Parkash, Evgeny Kharisov, Josiah Natan Wernow
  • Patent number: 10049052
    Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 14, 2018
    Assignee: NXP USA, Inc.
    Inventors: Ray Charles Marshall, Joachim Fader, Stephan Herrmann
  • Patent number: 10025649
    Abstract: Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 17, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bryan Kelly, Mallik Bulusu, Tom Nguyen
  • Patent number: 9990229
    Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 5, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dongrui Fan, Xiaochun Ye, Da Wang, Hao Zhang
  • Patent number: 9984014
    Abstract: The present invention provides a technique for further improving the processing efficiency in a semiconductor device that arbitrates data transfer between a plurality of bus masters and a plurality of bus slaves. A bus control circuit controls data transfer in an address bus and a data bus between a plurality of bus masters and a plurality of bus slaves. The bus control circuit obtains access information representing the bus slave that each of the bus masters accesses on the basis of address signals output from the bus masters. The bus control circuit obtains busy information representing whether or not each bus slave is in a busy state. In the case where the bus masters compete with each other when accessing a bus slave, the bus control circuit arbitrates access from each bus master to the bus slave that is not in a busy state in accordance with the priority set for each bus master on the basis of the access information and the busy information.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: May 29, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Naoshi Ishikawa
  • Patent number: 9965273
    Abstract: Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 8, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Yamasaki, Hideyuki Noda, Kan Murata
  • Patent number: 9910807
    Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
  • Patent number: 9847952
    Abstract: Systems and methods for automatic purchasing, reserving and/or provisioning of a wavelength bandwidth block are disclosed. A user may access a web page, such as an interactive web-portal, to provide bandwidth data and corresponding ordering information for reserving a particular amount of bandwidth capacity on a telecommunications network. Subsequently, the customer's may access and the bandwidth blocks to increase/decrease and/or activate/deactivate portions of the reserved bandwidth capacity as needed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 19, 2017
    Assignee: Level 3 Communications, LLC
    Inventors: Kelly R. Crosby, Benjamin W. Garrard, Jeff King, Scott A. Nusz, Monisha Merchant