Abstract: Systems, apparatuses, and methods for implementing priority adjustment forwarding are disclosed. A system includes at least one or more processing units, a memory, and a communication fabric coupled to the processing unit(s) and the memory. The communication fabric includes a plurality of arbitration points. When a client determines that its bandwidth requirements are not being met, the client generates and sends an in-band priority adjustment request to the nearest arbitration point. This arbitration point receives the in-band priority adjustment request and then identifies any pending requests which are buffered at the arbitration point which meet the criteria specified by the in-band priority adjustment request. The arbitration point adjusts the priority of any identified requests, and then the arbitration point forwards the in-band priority adjustment request on the fabric to the next upstream arbitration point which processes the in-band priority adjustment request in the same manner.

Abstract: A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.

Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A bus control device includes a plurality of bus masters classified into a plurality of groups according to a priority level, a plurality of group buses each group bus being connected to a corresponding group of bus masters and assigned with a priority level determined according to the priority levels of the corresponding group of bus masters, an upper priority bus that arbitrates a plurality of bus obtaining requests received from the plurality of bus maters via the plurality of group buses, a plurality of masks respectively provided for the plurality of bus masters to mask the bus obtaining request addressed to the corresponding group bus from the corresponding bus master, and a plurality of mask controllers respectively provided for the plurality of group buses to output at least one mask signal that controls operation of at least one corresponding mask connected to the corresponding group bus.

Abstract: Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.

Abstract: A bus arbiter (101) is provided to a bus (107). The bus (107) is connected to a plurality of bus masters, such as a CPU (410) and a serial I/F (413), to each of which a priority is given. The bus arbiter (101) changes the priorities of the plurality of bus masters at cycles determined in advance. The bus arbiter (101) receives a request signal for making a request for use of the bus (107) from at least one bus master. Based on the priorities of the respective bus masters at a time when the request signal is received, the bus arbiter (101) identifies one bus master given the highest priority among the at least one bus master that has transmitted the request signal. The bus arbiter (101) transmits a grant signal for permitting the use of the bus (107) to the identified one bus master.

Abstract: A certain ECU transmits a reference message for requiring the other ECUs to transmit data. After transmission of the reference message, each of all the ECUs transmits priority information of its transmit message onto a communication bus, and then detects whether some priority information transmitted from the other ECUs has a higher priority than its own transmitted priority information. If there is detected no priority information of a higher priority than its own transmitted priority information, it transmits a message associated therewith, and then is prohibited to transmit data of the same priority until receiving a next reference message.

Abstract: The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request.

Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).

Abstract: A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

Abstract: Certain exemplary embodiments comprise a wizard, which enables a user to configure and program an intelligent module by answering a series of questions about a specific application. The output of the wizard includes two distinct components. The wizard generates a parameter configuration for an intelligent module, reflecting the choices specified by a user for a specific application. The wizard also generates a set of customized instructions for use in a program. These instructions are specific to the choices that the user input into the wizard, and can be used in the same manner as standard instructions. Certain exemplary embodiments of the application, program, and instructions apply to a Program Logic Controller (PLC).

Abstract: Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.

Abstract: Systems and methods are provided for modularly constructing a software defined radio (“SDR”). Given an SDR kernel (i.e., a potentially platform-neutral definition of digital signal processing functionality and control operations necessary to implement the core portion of a software defined radio implementing a particular radio standard), an optional description of governmental regulations for a particular locality, and an interface harness providing the necessary components for interfacing to specific communication channels and devices (including SDR hardware components), an SDR factory component performs a process of constructing an SDR software component for implementing a particular radio standard on a particular host. The SDR software component may additionally construct components which restrict the operation of the resulting SDR software component.

Abstract: One embodiment of the present invention is a process tool optimization system that includes: (a) a data mining engine that analyzes end-of-line yield data to identify one or more process tools associated with low yield; and (b) in response to output from the analysis, analyzes process tool data from the one or more process tools to identify one or more process tool parameters associated with the low yield.

Abstract: The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus masters. It sequentially arbitrates a first hierarchy bus master of which requests are urgent, a second hierarchy bus master that requests data processing in real time, and a third hierarchy bus master that is neither a first hierarchy bus master nor a second hierarchy bus master sequentially.

Abstract: A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Abstract: Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.

Abstract: A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core, for automatically transmitting an acknowledge message. The method includes the steps of receiving a frame of a multi-frame fragmented message, and automatically transmitting an acknowledgment message without requiring any intervention of the processor core, in response to the receiving step. The automatically transmitting step is preferably performed by hardware external to the processor core, e.g., a CAN/CAL module of the CAN device.

Abstract: A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

Abstract: A CAN microcontroller that supports a plurality of message objects, and that includes a CAN processor core, a plurality of message buffers associated with respective ones of the message objects, a CAN/CAL module that processes incoming messages that include a plurality of frames and a plurality of message object registers, including at least one buffer size register that contains a message buffer size value, and at least one buffer location register that contains an address pointer. The CAN/CAL module includes a message handling function that transfers successive frames of the current incoming message to the message buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message an address pointer increment function.

Abstract: A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the first interface to a fault detection unit. A fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Abstract: A yield enhancement system organizes defect classification and attribute information into a global classification scheme. The global classes are used to identify defect sources and to generate inspection and review plans. The system accumulates defect information in a database and continually refines the information to improve the accuracy of the classification assignments and the identification of the defect sources.

Abstract: An arbitration system which allows communication between a plurality of competing processing modules over a shared communication bus. The system comprises an arbitration line coupled to a controller located on each processing module. When a processing module desires access to the communication bus, each controller, executing the same arbitration protocol, shifts its respective module address onto the arbitration line and monitors the arbitration line to detect for collisions.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.

Abstract: Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a “fair share” of the bus bandwidth. This share is defined as a number of bytes per a unit of time such as a time period. The shares together total a fraction of the total bus bandwidth, with a margin of bus bandwidth left unassigned. To prevent initiator starvation, each initiator monitors its bus requests to determine if it is being prevented by higher-priority initiators from using its assigned share of the bandwidth. If not, the initiator periodically pings each higher-priority initiator to indicate that it is not being starved. So long as a higher-priority initiator continues to receive pings from all lower-priority initiators, the higher-priority initiator can continue to use as much bandwidth as it needs.

Abstract: Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is included in a bridge device for interfacing the two computer buses and controlling when the peripheral device may access the main memory. When the peripheral device attempts to read data from the main memory that is duplicated in the cache and that has become stale, the bridge device initiates a write back operation to update specific data portions of the main memory corresponding to the read request. The bridge device uses look-ahead techniques such as bursting or pipelining to streamline the data coming from the cache to the main memory and to the peripheral device.