Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.

Abstract: Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons.

Abstract: A quality of service (QoS) arbitration method for an on-chip bus is disclosed. The bus arbitration method includes steps of classifying each of a plurality of requestors into one of a plurality of first QoS types; classifying the each of the plurality of requestors into one of a plurality of second QoS types corresponding to a plurality of service priorities according to a due date or a data rate of the each of the plurality of requestors and the one of the plurality of first QoS types; and choosing a requestor with a highest service priority among the plurality of requestors to service.

Abstract: A computer motherboard includes a printed circuit board which includes a central processing unit (CPU) socket and a group of memory slots. The group of memory slots includes an in-line type memory slot and a surface mounted device (SMD) type memory slot. The in-line type memory slot includes a number of plated through holes. The SMD type memory slot is set between the in-line type memory slot and the CPU socket. The through holes of the in-line type memory slot are connected to the CPU socket through traces, pads of the SMD type memory slot are connected to corresponding through holes of the in-line type memory slot having the same pin definition.

Abstract: A method and system for controlling transmission and execution of commands in an integrated circuit (IC) device provide transmission of commands and acknowledgements in an order of their priorities. Priority levels of the commands and acknowledgements are defined based on pre-assigned levels of precedence of the respective master and slave devices. In one application, the invention is used to increase performance of IC devices employing an Advanced eXtensible Interface (AXI).

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus masters. It sequentially arbitrates a first hierarchy bus master of which requests are urgent, a second hierarchy bus master that requests data processing in real time, and a third hierarchy bus master that is neither a first hierarchy bus master nor a second hierarchy bus master sequentially.

Abstract: An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching stage coupled to the bus and configured to select a first route configuration if two processors are coupled to the bus. The switching stage is also configured to select a second route configuration if more that two processors are coupled to the bus. The switching stage determines if two or more processors are coupled to the bus. A logic block may be used to determine the required configuration based on the detected processor population.

Abstract: Methods and apparatus associated with a plurality of serial devices designed to communicate with a bus master in either a daisy chain or a normal configuration are provided. One method includes the step of serially providing a command sequence having a channel identifier to a given device of a plurality of daisy chained devices. The channel identifier is modified as it passes thru each daisy chained device. A specific device is identified or enabled when the channel identifier it receives matches a pre-determined value.

Abstract: A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitration cycles, including a current cycle and a most recent cycle preceding the current cycle. Each processor receives memory access requests from all of the data ports, wherein each memory access request is associated with one of the memory banks. Each processor selectively grants the data port associated with that processor access to the memory for the current cycle based on the banks associated with the memory access requests of each data port, the data port that was granted access to the memory during the preceding cycle, and the memory bank that was accessed during the preceding cycle.

Abstract: A priority decision circuit decides priorities of a plurality of slots on the basis of access frequencies or the like. In conformity with these priorities, a bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to the upper hierarchical bus whereas it performs mapping allowing a slot having a lower priority to be connected to the lower hierarchical bus.

Abstract: Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: One aspect of the invention relates to a method for arbitrating simultaneous bus requests in a multiprocessor system having a plurality of devices which are coupled to a shared bus. In one version of the invention, the method includes the steps of receiving a plurality of bus requests from the devices; determining a device having the highest priority; determining whether the device having the highest priority is requesting the bus; granting bus access to the device having the highest priority if the device having the highest priority is requesting the bus; sequentially searching, beginning from the device logically adjacent to the device having the highest priority, for a next requesting device, and granting bus access to the next requesting device if the device having the highest priority is not requesting the bus; and assigning the highest priority to the device logically adjacent to the next requesting device.