Concurrent Input/output Processing And Data Transfer Patents (Class 710/20)
  • Patent number: 10235270
    Abstract: In testing a component-set whole process which includes a plurality of components and in which the order of execution of the plurality of components is defined, a computer system exports, to a storage resource, an input package for at least one component to be executed. Each of the plurality of components is a module of a significant process as a set of one or more processing steps and independent of any other components. Each input package includes an input value of a component that corresponds to the input package. The computer system imports an exported input package of a component to be debugged into the component to be debugged in order to execute the component to be debugged, without executing a component the order of which precedes the order N (where N is a natural number) of the component to be debugged.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 19, 2019
    Assignee: HITACHI LTD.
    Inventors: Hiroyuki Yamada, Hirokazu Taniyama, Masashi Nakaoka, Masatoshi Yoshida, Yuki Shimizu
  • Patent number: 10223155
    Abstract: Embodiments are provided that include the use of a cancellable command application programming interface (API) framework that provides cooperative multitasking for synchronous and asynchronous operations based in part on a command timing sequence and a cancellable command API definition. A method of an embodiment enables a user or programmer to use a cancellable command API definition as part of implementing a responsive application interface using a command timing sequence to control execution of active tasks. A cancellable command API framework of an embodiment includes a command block including a command function, a task engine to monitor the command function, and a timer component to control execution of asynchronous and synchronous tasks based in part on first and second control timing intervals associated with a command timing sequence. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: March 5, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Arye Gittelman, Petru Mihai Moldovanu, Sterling John Crockett
  • Patent number: 10169177
    Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 1, 2019
    Assignee: XILINX, INC.
    Inventors: Banadappa V Shivaray, Pranjal Chauhan, Pramod Surathkal, Alex S. Warshofsky, Tomai Knopp, Soumitra Kumar Bhowmick, Ahmad R. Ansari
  • Patent number: 10169073
    Abstract: Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Tracy G. Drysdale, James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, James T. Kukunas
  • Patent number: 10134473
    Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Vexata, Inc.
    Inventors: Surya P. Varanasi, Shailendra Jha
  • Patent number: 10120802
    Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10122576
    Abstract: Embodiments described herein are directed to mechanisms that enable roles (e.g., host vs. function, power provider vs. power consumer, master vs. slave, server vs. client, source vs. sink, upstream vs. downstream) to be dynamically assigned between two interconnected dual-role devices in an intelligent and deterministic manner based on the available context on each device.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: November 6, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Firdosh K. Bhesania, Anthony Y. Chen, Vivek Gupta, Andrea A. Keating, Randall E. Aull, Rahul Ramadas, Robert E. Harris, Jr., Jayson L. Kastens, Philip A. Froese, Cong Yang
  • Patent number: 10120803
    Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10089185
    Abstract: Systems and methods of utilizing multiple threads to facilitate parallel data copying to reduce an amount of time associated with backing up data. A request to copy application is received that indicates a number of available threads. A first available thread is used to select files from the application for backup. Selecting a file includes adding files to a work queue and creating backup work items associated with the work queue files. The files in the work queue are processed by a multiple threads in parallel such that an amount of time associated with backup up the application is reduced.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: October 2, 2018
    Assignee: Actifio, Inc.
    Inventors: Uday Tekade, Brian Groose
  • Patent number: 10048884
    Abstract: This disclosure is directed to systems, apparatuses, and methods of storing a data entity using at least two sectors of a memory device based at least in part on context information of the data entity. For example, the context information may differentiate between large sequential operations and small random operations, and may further improve multitasking support. The context information may further improve operations to erase data in the memory device. For example, a method may include storing a data entity using at least two sectors of a memory device, the at least two sectors associated with the same data entity, and maintaining, at a memory controller, context information of the data entity comprising a pointer to at least one of the at least two sectors of the memory device. The method may further include erasing the at least two sectors of the memory device using the context information.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 14, 2018
    Assignee: Memory Technologies LLC
    Inventor: Kimmo Mylly
  • Patent number: 10013367
    Abstract: An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing system. The I/O processing system further includes a channel subsystem module configured to output an interrogation command signal while the I/O device executes an I/O request. The I/O device returns an I/O status signal indicating a status of an ongoing I/O request, and the operating system is configured to dynamically determine a timeout event of the I/O request based on the status of the ongoing I/O request.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10007485
    Abstract: A compression first in, first out (cFIFO) that includes at least two FIFOs is described. A first FIFO is used to store instances of higher words in data entries, and a second FIFO is used to store corresponding instances of lower words in the data entries. If an instance of the higher word for a data entry has a different value than an immediately preceding stored instance of the higher word associated with at least an immediately preceding data entry which is stored in the second FIFO, memory pointers are incremented so that a subsequent instance of the higher word will be stored in the second FIFO without overwriting the instance of the higher word. Otherwise, the memory pointers are unchanged, which associates the instance of the lower word with the immediately preceding stored instance of the higher word.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Oracle International Corporation
    Inventors: Hagen W. Peters, Hans Eberle
  • Patent number: 9998895
    Abstract: A device, system and method for sharing sensor data is provided. A request to access sensor data is received at a receiver device, from a requestor device, the sensor data acquired by sensors associated with the receiver device. The receiver device determines a status of the receiver device. The receiver device determines, from the status of the receiver device, a subset of the sensor data to share with the requestor device. The receiver device determines one or more override contextual conditions associated with one or more of the requestor device and the receiver device. When the one or more override contextual conditions meets one or more override threshold conditions, the receiver device causes the subset of the sensor data to be shared with the requestor device.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 12, 2018
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Francesca Schuler, Katrin Reitsma, Adam C. Lewis
  • Patent number: 9998901
    Abstract: Disclosed herein are techniques to enable discovery of P2P capable devices and associated network connection information. In some embodiments, an information element is included in a transmitted request to indicate a request for network connection information from another wireless device. The device may respond with indications of the requested network connection information. Network connectivity capability determined from the network connection information may be used to decide whether to setup a Wi-Fi Direct link or a Tunneled Direct Link Setup (TDLS), or whether to use an AP infrastructure link with the other device.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Emily H. Qi, Ganesh Venkatesan, Carlos Cordeiro, David J. McCall
  • Patent number: 9996382
    Abstract: A method, system and computer program product are provided for implementing dynamic cost calculation for a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) in cloud environments. A management function periodically queries the SRIOV adapter for activity statistics for each assigned virtual function. The management function builds a usage heuristic based on the resource usage statistics. The management function calculates dynamic cost for the SRIOV VF based on the resource usage statistics. Calculated dynamic costs for the SRIOV VF are provided to a virtual function user and users are enabled to scale their VF resources. The VF resources are selectively scaled-up and scaled-down responsive to user input based upon VF resource usage.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manu Anand, Charles S. Graham, Timothy J. Schimke
  • Patent number: 9910678
    Abstract: A method for installation of a native OS on a host using non-native utilities. A native OS image is deployed on a native target client system using a non-native distribution server. The OS image is converted and packaged into a non-native format and provided to the target client. The OS image is unpacked and de-converted back to a native format and deployed on the target client. The client agent runs System Imaging Utility to acquire the OS image from the reference partition. The created OS image is pushed to the non-native file sharing system, and then the SCCM Proxy is asked to create an OS image package and a task sequence in the SCCM for this package. When the OS image is placed into the SCCM, the client agent reboots back to the reference partition.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 6, 2018
    Assignee: Parallels IP Holdings GmbH
    Inventors: Timofey Furyaev, Nikolay N. Dobrovolskiy, Evgeny Smirnov
  • Patent number: 9893972
    Abstract: Systems and methods are described providing detailed input/output (I/O) metric information that is collected and gathered by an agent of the storage volume. An I/O request is received by a storage volume, and the agent associates primary and secondary identifiers with that I/O request. For example, a trace may be associated with that I/O request. The agent may store this I/O metric information in a ring buffer. Further, after collection and aggregation, statistics may be published by an I/O metric service that further processes the data provided by the agent. Advantageously, interdependent relationships associated with the I/O request or I/O operations of that request may be included in those statistics. This may allow an operator to evaluate the performance of I/O requests for a network.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: February 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Marc Stephen Olson, Jeevan Shankar, James Michael Thompson, Danny Wei, John Robert Smiley, John Luther Guthrie, II, Nachiappan Arumugam, Benjamin Arthur Hawks
  • Patent number: 9880612
    Abstract: An execution control apparatus detects a character process of a character variable included in a program. The character variable allocates a first memory region capable of storing a character code of a specific length to each of one, two, or more characters. When detecting a character process of a character variable, the execution control apparatus allocates a second memory region corresponding to the first memory region to each character. The execution control apparatus processes a character expressed by a second character code that is longer than the specific length, using the first and second memory regions.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 30, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Takamasa Uramoto
  • Patent number: 9858084
    Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers. Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: January 2, 2018
    Assignee: BITMICRO Networks, Inc.
    Inventors: Alvin Anonuevo Manlapat, Ian Victor Pasion Beleno
  • Patent number: 9824041
    Abstract: Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected to the backend interface of the storage controller. Memory of the PCIe memory controller is memory mapped to controller memory of the storage controller. The PCIe connection allows the storage controller to access the memory of the PCIe memory controller with latencies similar to that of the controller memory.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 21, 2017
    Assignee: DATADIRECT NETWORKS, INC.
    Inventor: Bret S Weber
  • Patent number: 9772776
    Abstract: Systems and methods are disclosed for swapping a memory page from memory to a swap device. An example system for swapping a memory page from memory to a swap device includes a memory to store one or more memory pages. The system also includes a swap device selector that receives an indication to swap out a memory page from memory to a swap device. The swap device selector identifies a memory group to which the memory page belongs and selects a swap device from a plurality of swap devices assigned to the identified memory group. The memory group identifies a plurality of applications having a common property. The system further includes a swap module that copies the memory page into the selected swap device.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 26, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9754562
    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 9753887
    Abstract: A communications apparatus is provided having a first line driver transmitting data at a first end of a serial bus to a second line receiver at a second end of the serial bus. A first line receiver receives data at the first end of the serial bus from a second line driver at the second end of the serial bus. The first line receiver has a selectable input parameter that controls a physical layer quality of data received at the first end of the serial bus. Programming instructions stored in memory cause the second line driver to transmit a training signal that is not a COMWAKE signal to the first line receiver in response to the first line driver transmitting a COMWAKE signal to the second line receiver. A controller compares a received physical layer quality of the training signal at the first line receiver to a desired physical layer quality and computes a value for the input parameter to obtain a desired physical layer quality.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: September 5, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Anthony Leigh Priborsky, Marc Stephen Hildebrant
  • Patent number: 9740997
    Abstract: A method for input driven process flow management includes receiving a request, each request having an input and an output, identifying tasks for a process fit for the request type, receiving inputs; generating, based on the inputs and the process, a process flow step, and executing the process flow step to generate results (outputs). The method further includes receiving a second set of inputs, different than the first set of inputs, generating, based on the second set of inputs and the process, a second process flow step different than the first process flow, and executing the second process flow step to generate a second set of results, and so on, until all tasks are executed, or a termination task has been reached.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 22, 2017
    Assignee: Schedule 1 Inc.
    Inventors: Jacob Katz, Kevin Ellison
  • Patent number: 9729692
    Abstract: A cable for providing electric power from a power source to a mobile device, the cable having a first connector at a first end of the cable for connecting the cable to a mobile device and with a second connector at a second end for connecting the cable to the power source, wherein the cable comprises a memory module for backup and bidirectional transfer of data to and from the mobile device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: August 8, 2017
    Assignee: MEEM Memory Limited
    Inventor: Anil Goel
  • Patent number: 9703714
    Abstract: Systems and methods for managing cache configurations are disclosed. In accordance with a method, a system management control module may receive access rights of a host to a logical storage unit and may also receive a desired caching policy for caching data associated with the logical storage unit and the host. The system management control module may determine an allowable caching policy indicator for the logical storage unit. The allowable caching policy indicator may indicate whether caching is permitted for data associated with input/output operations between the host and the logical storage unit. The system management control module may further set a caching policy for data associated with input/output operations between the host and the logical storage unit, based on at least one of the desired caching policy and the allowable caching policy indicator. The system management control module may also communicate the caching policy to the host.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: July 11, 2017
    Assignee: Dell Products L.P.
    Inventor: William Price Dawkins
  • Patent number: 9697152
    Abstract: An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing system. The I/O processing system further includes a channel subsystem module configured to output an interrogation command signal while the I/O device executes an I/O request. The I/O device returns an I/O status signal indicating a status of an ongoing I/O request, and the operating system is configured to dynamically determine a timeout event of the I/O request based on the status of the ongoing I/O request.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 9690585
    Abstract: A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
  • Patent number: 9690660
    Abstract: Embodiments are directed to techniques for techniques for selecting a proper set of spare sections to use in a given failure scenario. These embodiments use a set of rules to define which spare sections are eligible to serve as spares for reconstruction of the RAID members on a disk that had failed. In addition, the set of rules may include weighted rules to allow optimization in the spare selection process.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: June 27, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Edward S. Robins, Evgeny Malkevich
  • Patent number: 9665372
    Abstract: A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
  • Patent number: 9626139
    Abstract: A network printing system includes user devices, printing devices, a print server, and a logon server. The print server includes a print queue arranged to store print jobs received from the user devices and to send stored print jobs to the printing devices. The logon server is arranged to store logon details for users of the user devices and to store printer information for the users. The print server is arranged to select a printing device to which to send a print job stored in the queue based on the printer information stored in the logon server for the user of the user device from which the print job originated.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 18, 2017
    Assignee: CANON EUROPA N.V.
    Inventors: Dirk Tiemeyer, Karsten Huster
  • Patent number: 9614910
    Abstract: Provided are a method, a system, and a computer program that use a Fibre Connection (FICON) protocol, in which a first device that is coupled to a second device receives an outbound exchange from the second device, wherein one or more Fibre Channel frames of the outbound exchange have a priority indicated by the second device. The first device responds to the second device with an inbound exchange, wherein one or more Fibre Channel frames of the inbound exchange have an identical priority to the priority indicated by the second device in the outbound exchange. In additional embodiments, priority is maintained across related exchange pairs.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger G. Hathorn, Bret W. Holley, Harry M. Yudenfriend
  • Patent number: 9582388
    Abstract: An integrated circuit device comprises multiple cores each comprising one or more separate input and output interfaces, the multiple cores integrated within the integrated circuit device to function as a single computer system. Internal inter-chip connection links are disposed on the integrated circuit device for connecting one or more cores with at least one other core via the one or more separate input and output interfaces. One or more bidirectional access ports are communicatively connected in each path of the inter-chip connection links to enable a separate external access point to each of the one or more separate input and output interfaces of the cores, wherein each of the one or more bidirectional access ports is dynamically selectable as each of an external input interface of the integrated circuit device and an external output interface of the integrated circuit device.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 28, 2017
    Assignee: GlobalFoundries Inc.
    Inventors: Zhi G. Liu, Megan P. Nguyen, Bill N. On, Suksoon Yong
  • Patent number: 9542830
    Abstract: Embodiments of the invention provide systems and methods for distributing urgent public information. Merely by way of example, urgent public information, such as an alert message, may be received by, inter alia, an alert gateway device. The alert message may then be distributed to a subscriber in any of a variety of ways, including by telephone, by data message (e.g., to a computer), by video message (e.g., via a television), by display on an alert notification device. In some embodiments, the alert gateway device may process the alert message and/or may determine how to provide the alert message to the subscriber.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 10, 2017
    Assignee: Qwest Communications International Inc.
    Inventors: Steven M. Casey, Bruce A. Phillips
  • Patent number: 9471242
    Abstract: A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: October 18, 2016
    Assignees: Western Digital Technologies, Inc., Skyera, LLC
    Inventors: Justin Jones, Andrew J. Tomlin, Rodney N. Mullendore, Radoslav Danilak
  • Patent number: 9405826
    Abstract: Systems and methods are provided for audio processing. A system includes: a component manager and a pipeline manager. The component manager is configured to communicate with a host system and manage one or more components for processing an audio stream. A component is associated with one or more audio processing functions. The pipeline manager is configured to manage one or more connections among the components. The connections indicate a processing flow involving the components.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 2, 2016
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xueming Zhao, Fu Zhen, Nenghua Cao
  • Patent number: 9379778
    Abstract: The near field communication (NFC) circuit includes an NFC reader circuit configured to communicate with an outside through an antenna, a resonant and matching circuit connected between the NFC reader circuit and the antenna, an NFC card circuit connected to nodes and configured to communicate with the outside through the antenna, and a processor configured to output a plurality of control signals when the NFC reader circuit is enabled, wherein the NFC card circuit is configured to control a resonant frequency of the antenna in response to the plurality of control signals.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Hwan Roh, Il Jong Song, Chol Su Yoon
  • Patent number: 9274987
    Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 1, 2016
    Assignee: Intel Corporation
    Inventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
  • Patent number: 9141311
    Abstract: The present invention relates to multi-use adapters, specifically for adding functionality to a computing system via a Thunderboltâ„¢ connector or other high speed connector. In addition, the present invention relates to RAID storage modules built upon the multi-use adapters of the present invention. Further, RAID storage systems consisting of multiple RAID storage modules are provided. Methods of making and using the same are further provided.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 22, 2015
    Assignee: New Concepts Development Corp.
    Inventor: Christopher T. Haeffner
  • Patent number: 9075784
    Abstract: There is provided a communication device which communicates with a target communication device, including: a communication controller, a general-purpose processing unit, a data transfer processing unit and a starting unit. The general-purpose processing unit communicates with the target communication device via the communication controller. The data transfer processing unit receives data from the target communication device via the communication controller. The starting unit starts up the data transfer processing unit. The general-purpose processing unit receives a data transfer start request from the target communication device. The starting unit starts up the data transfer processing unit when the general-purpose processing unit receives the data transfer start request. The general-purpose processing unit or the data transfer processing unit notifies a data transfer start response to the target communication device after the data transfer processing unit is started up.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuta Kobayashi, Nobuhiko Sugasawa, Masataka Goto, Shinya Murai
  • Patent number: 9036173
    Abstract: The present specification discloses systems and methods for enabling users to troubleshoot multifunction devices using handheld devices, such as mobile phones. In one embodiment, software executing on the handheld device receives data indicative of an error state in a multifunction device, causes the handheld device to obtain and display an image representative of an area of the multifunction device which would need to be serviced to address the error state, determines instructions for addressing the error state, and causes the handheld device to display the instructions in relation to the image representative of an area of the multifunction device.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 19, 2015
    Assignee: Xerox Corporation
    Inventors: David Andrew Thomas, Martin Richard Walsh
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Patent number: 9026689
    Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Greg A. Dyck, Tan Lu, Kenneth J. Oakes, Dale F. Riedy, Jr., William J. Rooney, John S. Trotter, Leslie W. Wyman, Harry M. Yudenfriend
  • Patent number: 9021155
    Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Carl A. Bender, Clinton E. Bubb, Daniel F. Casper, John R. Flanagan
  • Patent number: 9015367
    Abstract: A fieldbus gateway using a virtual serial fieldbus port and a data transmission method thereof are provided. By receiving a fieldbus frame containing target data through a virtual serial fieldbus port connected to a source device or a target device via a fieldbus gateway and sending another fieldbus frame containing the target data via other fieldbus port to target devices or source devices, the system and the method can provide two or more remote devices to control one controlled device at the same time. The invention also achieves the effect of using one virtual serial fieldbus port to transmit data between multiple source devices and target devices concurrently.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Moxa Inc.
    Inventors: Bo Er Wei, Chun Fu Chuang
  • Patent number: 9009371
    Abstract: A device is described for establishing communication between a first device and a second device. In one implementation, a first internal interface of the first device couples to a first external interface of the second device while a second internal interface of the first device couples to a second external interface of the second device. A first unidirectional data channel may be opened for incoming data using the first internal interface. A second unidirectional data channel may be opened for outgoing data using the second internal interface. The pair of unidirectional data channels is established, allowing data transfer between the devices. These channels allow for asynchronous-like transmission of data, in that transmission and corresponding receipt of data may take place at irregular intervals.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 14, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Richard William Mincher
  • Patent number: 8996734
    Abstract: Described herein is a system (102) having a virtualization and switching system configured to virtualize I/O devices (108) and perform switching of the I/O devices (108) and I/O requests. The virtualization and switching system (102) includes a peripheral virtualization controller (PVC) (204), at least one device control module (206) connected to the PVC (204), and at least one command parser (210). The PVC (204) is configured to manage I/O virtualization and I/O command access of different I/O devices (108). The device control module (206) is configured to store configuration and I/O device registers, implemented by the PVC (204) to enable virtualization of I/O devices (108). The device control module (206) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors (104).
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 31, 2015
    Assignee: Ineda Systems Pvt. Ltd
    Inventors: Balaji Kanigicherla, Siva Raghu Ram Voleti, Krishna Mohan Tandaboina
  • Patent number: 8996764
    Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: March 31, 2015
    Assignee: Marvell International Ltd.
    Inventor: Martin White
  • Patent number: 8990444
    Abstract: A fieldbus gateway using a virtual serial fieldbus port and a data transmission method thereof are provided. By receiving a fieldbus frame containing target data through a virtual serial fieldbus port connected to a source device or a target device via a fieldbus gateway and sending another fieldbus frame containing the target data via other fieldbus port to target devices or source devices, the system and the method can provide two or more remote devices to control one controlled device at the same time. The invention also achieves the effect of using one virtual serial fieldbus port to transmit data between multiple source devices and target devices concurrently.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: March 24, 2015
    Assignee: Moxa Inc.
    Inventors: Bo Er Wei, Chun Fu Chuang
  • Patent number: 8990445
    Abstract: A control chip includes a configurable pin and a control logic. The configurable pin is arranged for coupling a first pin and a second pin of a high-definition multimedia interface (HDMI) connector. The control logic is arranged for controlling the configurable pin to switch between a first operation mode and a second operation mode. The configurable pin serves as an input pin when operating in the first operation mode, and the configurable pin serves as an output pin when operating in the second operation mode. For example, the input pin is arranged for receiving a power supply signal derived from a +5V power signal received by the first pin, and the output pin is arranged for outputting a control signal for controlling hot plug detection (HPD).
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 24, 2015
    Assignee: Mediatek Inc.
    Inventors: Ching-Gu Pan, Huai-Yuan Feng