Abstract: Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Abstract: A method may include receiving a communication from a device at an artificial intelligence controller including state information for a software application component running on the device, the state information including information corresponding to at least one potential state change available to the software application component, and metrics associated with at least one end condition, interpreting the state information using the artificial intelligence controller, and selecting an artificial intelligence algorithm from a plurality of artificial intelligence algorithms for use by the software application component based on the interpreted state information; and transmitting, to the device, an artificial intelligence algorithm communication, the artificial intelligence algorithm communication indicating the selected artificial intelligence algorithm for use in the software application component on the device.

Abstract: Systems and methods described include receiving traffic associated with a multi-access edge computing (MEC) application hosted at a MEC network; determining an Internet Protocol (IP) address associated with the MEC application, wherein the IP address indicates a priority of the traffic associated with the MEC application; modifying a header of the traffic to include the IP address associated with the MEC application; transmitting the traffic to a wireless station; and routing the traffic based on the priority associated with the MEC application.

Abstract: Techniques are described herein for executing queries on distinct portions of a database object that has been separate into chunks and distributed across the volatile memories of a plurality of nodes in a clustered database system. The techniques involve redistributing the in-memory database object portions on changes to the clustered database system. Each node may maintain a mapping indicating which nodes in the clustered database system store which chunks, and timestamps indicating when each mapping entry was created or updated. A query coordinator may use the timestamps to select a database server instance with local in memory access to data required by a portion of a query to process that portion of the query.

Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.

Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.

Abstract: Disk access event control for mapped nodes of a cluster storage system supporting a redundant array of independent nodes (mapped RAIN) system is disclosed. A mapped RAIN cluster can be allocated on top of one or more real data clusters. In an embodiment, disk access events can be routed via a storage service instance supporting a mapped node. In another embodiment, disk access events can be routed via another storage service instance that does not support the mapped node. Routing the disk access event via another storage service instance that does not support the mapped node can reduce the use of computing resources. Further, the routing of the disk access event can be according to a proportional disk operation value determined based on historical disk access event characteristics.

Abstract: A memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory, in response to a command from at least one host. The controller performs command fetching by calculating for each of a plurality of queues, a remaining processing amount, which is an amount of processing remaining for one or more commands previously fetched therefrom, selecting a queue based on the remaining processing amounts calculated for the plurality of queues, and fetching a new command from the selected queue.

Abstract: A cloud native global file system is augmented to include a “file accelerator” that is configured to speed up data propagation with respect to updates on a shared volume and, in particular by performing real-time analysis on audit event data to coordinate pushes and pulls across multiple edge appliances, effectively replacing static snapshot and synchronization schedules. A “push” refers to a snapshot on the volume that occurs at a particular filer, and a “pull” refers to a synchronization (sync) operation initiated by a particular filer to obtain whatever is in the cloud (and that is the subject of the pull). The file accelerator operates in several modes of “triggered” operation based on user activity, and under the control of a cloud-based controller.

Abstract: An electronic device is provided. The electronic device includes an ultra-wideband (UWB) communication circuit, a processor operatively connected to the UWB communication circuit, and a memory operatively connected to the processor. The memory stores instructions, and when the instructions are executed, the instructions, when executed, further cause the processor to establish a wireless communication channel with an external electronic device using the UWB communication circuit, perform positioning communication with the external electronic device based on a predetermined period, via the wireless communication channel, recognize a distance between the electronic device and the external electronic device, and a changing trend of the distance, based at least on the positioning communication, and change the positioning communication period based on the recognized distance and the changing trend.

Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.

Abstract: A method of prefetching data in a dynamically adjustable amount is executed by: determining a specified number of data blocks according to an averaged data transmission rate and a predetermined fetching index; sending out a data request command to obtain a requested data, wherein the requested data is included in a specified data and consists of the same number of data blocks as the specified number; and receiving and storing the requested data as a prefetch data consisting of the same number of data blocks for prefetch as the specified number. when the specified number is equal to or greater than two, one of the data blocks for prefetch is designated as a launch block for prefetch, and when the launch block for prefetch is read, the fetching index is optionally adjusted according to a predetermined rule.

Abstract: A method includes transmitting an ECC encoded first data and an ECC encoded second data from a memory to a logic circuit, and generating an ECC encoded output data by executing an ECC-Space operation using the ECC encoded first data as a first operand and the ECC encoded second data as a second operand. The ECC encoded first data and the ECC encoded second data are the corresponding results of encoding a first data and a second data with an ECC algorithm. The ECC-Space operation is translated from a two operands operation that is operative to transform the first data and the second data into a third data. The ECC encoded output data is identical to a result of encoding the third data with the ECC algorithm if the third data is encoded with the ECC algorithm.

Abstract: A process for prioritizing content responses executed by a first server in a distributed cloud platform. The first server including processor, and a non-transitory machine-readable storage medium that provides instructions that, when executed by the processor, causes the first server to perform operations including to receive a request for a plurality of content items from a client device, where the proxy server is in a distributed cloud computing platform, receive a first content item of the plurality of content items from an origin server or a cache, determine a priority scheme for ordering the plurality of content items, where the priority scheme is specific to the plurality of content items and is derived from analysis of a first content item from the plurality of content items, and send a response including the plurality of content items to the client device in an order according to the determined priority scheme.

Abstract: Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.

Abstract: A data storage device includes a memory device configured to store data; and a memory controller configured to control the memory device in response to a request of the host. The memory controller may include: a device information storage configured to store device information including share function information indicating whether the storage device is capable of sharing the data with another storage device and a monitor configured to receive from the host an initialization message determining, based on the share function information, a kind of information output from the storage device, and generate any one of normal status information and extended status information indicative of a current status of the storage device, in response to the initialization message.

Abstract: A method and apparatus configured for updating vehicle software using over-the-air (OTA) may include extracting first format difference data and second format difference data, corresponding to a first format and a second format of an update target software image, respectively, comparing the first format difference data and the second format difference data, determining a format of difference data as a transmission target, based on the comparison result, and transmitting the determined format of difference data to an update target vehicle terminal through a wireless network. Accordingly, it is advantageous to minimize the amount of transmitted data while vehicle software is updated using OTA.

Abstract: Limitations on memory access decrease the computing capability of related-art semiconductor devices during convolution processing in a convolutional neural network. A semiconductor device according to an aspect of the present invention includes an accelerator section that performs computation on a plurality of intermediate layers included in a convolutional neural network by using a memory having a plurality of banks capable of changing the read/write status on an individual bank basis. The accelerator section includes a network layer control section that controls a memory control section in such a manner as to change the read/write status assigned to the banks storing input data or output data of the intermediate layers in accordance with the transfer amounts and transfer rates of the input data and output data of the intermediate layers included in the convolutional neural network.

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.

Abstract: A tape drive-implemented method for encrypting metadata on a magnetic tape, the tape drive-implemented method, according to one embodiment, includes: writing an index to a magnetic tape. The index includes: metadata corresponding to a file stored on the magnetic tape, and metadata corresponding to a directory structure of the file. The tape drive-implemented method additionally includes: using a first key to encrypt a first portion of the metadata in the index corresponding to the file, and using a second key to encrypt a first portion of the metadata in the index corresponding to the directory structure of the file. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

Abstract: The present invention relates to an auxiliary stream transmission method based on a video conference system. The method integrates an auxiliary stream function into an auxiliary stream peripheral, a computer is connected to a master server of the video conference system through the auxiliary stream peripheral, and the master server and the auxiliary stream peripheral are connected through a network cable. In the present invention, the auxiliary stream peripheral and the master server are connected through a network cable, to improve flexibility of system deployment, and costs of the network cable are low, to correspondingly reduce deployment costs of the system.

Abstract: An electronic apparatus and a detection method using the same are provided. The electronic apparatus includes a processor, a platform controller, and an auxiliary controller. The processor includes a first bus compatible with a first standard. The platform controller is coupled to the processor, and the processor is connected to peripheral devices of the electronic apparatus through the platform controller or the first bus according to the first standard. The auxiliary controller is coupled to the processor through the first bus, and the processor controls the auxiliary controller through a second bus and the platform controller. The auxiliary controller receives a detection signal to detect the processor, the platform controller, or at least one of the peripheral devices in the electronic apparatus through the first bus compatible with the first standard according to the detection signal.

Abstract: Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

Abstract: Exemplary method, system, and computer program embodiments for facilitating information between at least one host and a storage controller operational in a data storage subsystem are provided. In one embodiment, a pseudo-volume, mappable to the at least one host and mountable as a filesystem, is initialized. The pseudo-volume is adapted for performing at least one of providing diagnostic and statistical data representative of the data storage subsystem to the at least one host, and facilitating control of at least one parameter of the storage controller.

Abstract: An image processing apparatus connected to an image display apparatus that displays visual information including handwritten data superimposed on a display image is provided. The image processing apparatus displays a plurality of screens, including a first screen and a second screen that is different from the first screen, and causes the image display apparatus to display a screen selected from among the first screen and the second screen. The image processing apparatus selects the screen from among the first screen and the second screen to generate the display image of the selected screen, based on a graphical user interface that accepts input of an operation of selecting the screen from among the first screen and the second screen or an operation of instructing generation of the display image.

Abstract: A method, according to one embodiment, includes: establishing a wireless connection between a wireless receiver in a solid state drive and a mobile device, receiving configuration instructions from the mobile device via the wireless connection, sending the received configuration instructions to a processor in a second device via a physical electrical connection coupling the second device to the solid state drive, receiving data from the second device via the physical electrical connection coupling the second device to the solid state drive, and storing the data in a memory of the solid state drive according to the received configuration instructions. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A method of operating a storage device includes receiving, from a host, a first packet containing a buffer address indicating a location of a data buffer selected from among a plurality of data buffers in the host, parsing the buffer address from the first packet, and transmitting a second packet containing the buffer address to the host in response to the first packet.

Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

Abstract: A network module is specified for controlling an automation process via a data network with superordinate and subordinate data paths. The network module is configured to successively receive, during a communication cycle, via the superordinate data path, a first portion of a sum total of first output data transmitted to signal units connected to a first subordinate data path, a first portion of a sum total of second output data transmitted to signal units connected to a second subordinate data path, a second portion of the first output data and a second portion of the second output data. The network module is configured to send the first and second portions of the first output data immediately subsequently to one another via the first subordinate data path and the first and second portions of the second output data immediately subsequently to one another via the second subordinate data path.

Abstract: Systems, methods, and apparatuses are disclosed herein for discovering unknown chips and chip components of a MoChi system. To this end, a first System-on-Chip (“SoC”) may transmit a first discovery packet from a downlink MoChi port the first SoC to an uplink MoChi port of a second SoC. The first SoC may receive, at the downlink MoChi port of the first SoC, from the uplink MoChi port of the second SoC, a first reply packet. The first SoC may determine whether the reply packet indicates that the second SoC is a known SoC or an unknown SoC. In response to determining that the second SoC is an unknown SoC, the first SoC may assign a first address mask to the first SoC that identifies that the second SoC can be reached by way of the first SoC.

Abstract: Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.

Abstract: Methods, systems, and computer readable media for aggregating completion entries in a nonvolatile storage device are disclosed. On method is implemented in a data storage device including a controller and a memory. The method includes receiving a request to post a completion entry that indicates an execution of a command by a data storage device and determining whether the completion entry is to be aggregated with one or more completion entries prior to being sent by the data storage device to a host device memory. The method further includes, in response to determining that the completion entry is to be aggregated, aggregating the completion entry with at least one other completion entry within an aggregation data store per predefined aggregation criteria and sending an aggregation of the completion entry and the at least one other completion entry to the host memory device in response to a trigger event.

Abstract: A High Speed Link System providing network and data transfer capabilities, implemented via standard input/output (I/O) device controllers, protocols, cables and components, to connect one or more Host computing systems, comprising a System, Apparatus and Method is claimed; and described in one or more embodiments. An illustrative embodiment of the invention connects two or more Host systems via USB 3.0 ports and cables, establishing Network, Control, Data Exchange, and Power management required to route and transfer data at high speeds, as well as resource sharing. A Link System established using USB 3.0 operates at the full 4.8 Gbps, eliminating losses inherent when translating to, or encapsulating within, a network protocol, such as the Internet Protocol. Method claimed herein describes how two or more connected Host systems, detect one another, and establish separate communication and data exchange bridges, wherein control sequences from the Hosts' application direct the operation of the Apparatus.

Abstract: A method, apparatus and system testing a plurality of semiconductor chips in a distributed memory buffer system is provided. Embodiments of the present invention recognize improvements to testing signals through the chip substrate and motherboard. This invention overloads the shared broadcast bus by using it for test purposes rather than its normal mainline function. One of the main components of this invention is the A/C chip. In test mode, the AC chip converts JTAG commands into an internal test format and sends test data over the shared broadcast bus. Each data chip determines whether the scan data is for itself or if it should ignore it. The corresponding data chip then processes the data, and if necessary sends return data back to the address and command chip, where it is converted back into JTAG format and can be seen by the tester.

Abstract: In testing a component-set whole process which includes a plurality of components and in which the order of execution of the plurality of components is defined, a computer system exports, to a storage resource, an input package for at least one component to be executed. Each of the plurality of components is a module of a significant process as a set of one or more processing steps and independent of any other components. Each input package includes an input value of a component that corresponds to the input package. The computer system imports an exported input package of a component to be debugged into the component to be debugged in order to execute the component to be debugged, without executing a component the order of which precedes the order N (where N is a natural number) of the component to be debugged.

Abstract: Embodiments are provided that include the use of a cancellable command application programming interface (API) framework that provides cooperative multitasking for synchronous and asynchronous operations based in part on a command timing sequence and a cancellable command API definition. A method of an embodiment enables a user or programmer to use a cancellable command API definition as part of implementing a responsive application interface using a command timing sequence to control execution of active tasks. A cancellable command API framework of an embodiment includes a command block including a command function, a task engine to monitor the command function, and a timer component to control execution of asynchronous and synchronous tasks based in part on first and second control timing intervals associated with a command timing sequence. Other embodiments are also disclosed.

Abstract: Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

Abstract: Described is a write scheduling scheme for a SSD that significantly increases read performance, in certain embodiments by about 50% compared to a conventional standard write scheduling schemes, for mixed read-write workloads while maintaining the write bandwidth.

Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: Embodiments described herein are directed to mechanisms that enable roles (e.g., host vs. function, power provider vs. power consumer, master vs. slave, server vs. client, source vs. sink, upstream vs. downstream) to be dynamically assigned between two interconnected dual-role devices in an intelligent and deterministic manner based on the available context on each device.

Abstract: Systems and methods of utilizing multiple threads to facilitate parallel data copying to reduce an amount of time associated with backing up data. A request to copy application is received that indicates a number of available threads. A first available thread is used to select files from the application for backup. Selecting a file includes adding files to a work queue and creating backup work items associated with the work queue files. The files in the work queue are processed by a multiple threads in parallel such that an amount of time associated with backup up the application is reduced.

Abstract: This disclosure is directed to systems, apparatuses, and methods of storing a data entity using at least two sectors of a memory device based at least in part on context information of the data entity. For example, the context information may differentiate between large sequential operations and small random operations, and may further improve multitasking support. The context information may further improve operations to erase data in the memory device. For example, a method may include storing a data entity using at least two sectors of a memory device, the at least two sectors associated with the same data entity, and maintaining, at a memory controller, context information of the data entity comprising a pointer to at least one of the at least two sectors of the memory device. The method may further include erasing the at least two sectors of the memory device using the context information.

Abstract: An I/O processing system includes an operating system configured to control an input/output (I/O) device, which executes an I/O operation in the I/O processing system. The I/O processing system further includes a channel subsystem module configured to output an interrogation command signal while the I/O device executes an I/O request. The I/O device returns an I/O status signal indicating a status of an ongoing I/O request, and the operating system is configured to dynamically determine a timeout event of the I/O request based on the status of the ongoing I/O request.

Abstract: A compression first in, first out (cFIFO) that includes at least two FIFOs is described. A first FIFO is used to store instances of higher words in data entries, and a second FIFO is used to store corresponding instances of lower words in the data entries. If an instance of the higher word for a data entry has a different value than an immediately preceding stored instance of the higher word associated with at least an immediately preceding data entry which is stored in the second FIFO, memory pointers are incremented so that a subsequent instance of the higher word will be stored in the second FIFO without overwriting the instance of the higher word. Otherwise, the memory pointers are unchanged, which associates the instance of the lower word with the immediately preceding stored instance of the higher word.

Abstract: A device, system and method for sharing sensor data is provided. A request to access sensor data is received at a receiver device, from a requestor device, the sensor data acquired by sensors associated with the receiver device. The receiver device determines a status of the receiver device. The receiver device determines, from the status of the receiver device, a subset of the sensor data to share with the requestor device. The receiver device determines one or more override contextual conditions associated with one or more of the requestor device and the receiver device. When the one or more override contextual conditions meets one or more override threshold conditions, the receiver device causes the subset of the sensor data to be shared with the requestor device.

Abstract: Disclosed herein are techniques to enable discovery of P2P capable devices and associated network connection information. In some embodiments, an information element is included in a transmitted request to indicate a request for network connection information from another wireless device. The device may respond with indications of the requested network connection information. Network connectivity capability determined from the network connection information may be used to decide whether to setup a Wi-Fi Direct link or a Tunneled Direct Link Setup (TDLS), or whether to use an AP infrastructure link with the other device.

Abstract: A method, system and computer program product are provided for implementing dynamic cost calculation for a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) in cloud environments. A management function periodically queries the SRIOV adapter for activity statistics for each assigned virtual function. The management function builds a usage heuristic based on the resource usage statistics. The management function calculates dynamic cost for the SRIOV VF based on the resource usage statistics. Calculated dynamic costs for the SRIOV VF are provided to a virtual function user and users are enabled to scale their VF resources. The VF resources are selectively scaled-up and scaled-down responsive to user input based upon VF resource usage.