Concurrent Input/output Processing And Data Transfer Patents (Class 710/20)
  • Patent number: 8316163
    Abstract: In a presentation system, a source device provides uncompressed presentation content in an HDMI format. A first conversion device converts the uncompressed presentation content to an uncompressed second format and entirely transmits the uncompressed presentation content in the second format along an electrically conductive member. A second conversion device receives the uncompressed presentation content in the second format from the conductive member and converts the uncompressed presentation content to the HDMI format. For example, the conductive member may be that of a coaxial cable.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: November 20, 2012
    Assignee: John Mezzalingua Associates, Inc.
    Inventors: Stephen J. Skeels, Steven K. Shafer
  • Patent number: 8312470
    Abstract: A process thread locking operations includes defining a lock structure having data fields that include a process thread identifier and a shared object identifier that uniquely identifies a shared object subject to lock operations and using the lock structure to build a lock table. The lock table includes lock structures for each process thread in the process and is searchable in response to a request for a shared object from a calling thread. The method also includes determining a lock status of the shared object. The lock status indicates whether the shared object is currently locked by the calling process thread. In response to the lock status, the method includes obtaining a lock on the shared object when the request is for a lock, and releasing a lock on the shared object when the request is to unlock the shared object.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lisa D. Banks, Jason A. Keenaghan
  • Patent number: 8312469
    Abstract: The present invention relates to the field of network portals and in particular to a method and system for exchanging data between components of one or more composite applications implemented on a portal server, wherein the components are programmed independently from each other. An embodiment of the invention includes: automatically intercepting I/O data being input or output respectively to or from the components or a browser; extracting data objects from the I/O data; determining for a source component, which of the data objects match input requirements of which other potential target components; selecting matching data objects for a matching target component; and transferring the matching data objects to the matching target component.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Oliver Koeth, Hendrik Haddorp, Stefan Hepper, Stefan Liesche, Michael Marks
  • Patent number: 8301821
    Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: October 30, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Markus Ihle, Tobias Lorenz, Jan Taube
  • Patent number: 8289539
    Abstract: An MFP which holds resources stores resource information about the held resources. Whether or not a resource holding request has been added to a resource downloading request from an SFP is discriminated. If a resource holding request has been added, a holding priority to decide a holding state of the held resources is set. The holding state of the held resources is controlled based on the holding priority.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: October 16, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuhiro Koga
  • Patent number: 8285890
    Abstract: A host device, a point of deployment (POD), and a method for recognizing an operation mode are disclosed. The host device interfaces with a point of deployment (POD), and includes an interface unit and a controller. The interface unit includes CD1#, CD2#, VS1#, VS2#, VPP1, VPP2, and IPDET ports. The controller outputs a mode confirmation signal to the POD via the IPDET port, and identifies that the POD supports an Internet Protocol (IP) Card M-Mode when the mode confirmation signal has been applied to the VS1# and VS2# ports.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: October 9, 2012
    Assignee: LG Electronics Inc.
    Inventors: Sang Hoon Cha, Kwang Hun Kwon, Sung Ho Hwang
  • Patent number: 8285891
    Abstract: A host device, POD (point of deployment) and a method of identifying an operation mode are disclosed, by which data received via internet can be processed. The present invention includes an interface unit including CD#1, CD#2 , VS1#, VS2#, VPP1, VPP2 and IPDET ports and a controller controlling a mode confirmation signal to be outputted to the POD via the IPDET port, the controller recognizing that the POD supports an IP (internet protocol) card M-mode if the outputted mode confirmation signal is inputted to the VS1# port.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: October 9, 2012
    Assignee: LG Electronics Inc.
    Inventors: Sang Hoon Cha, Kwang Hun Kwon, Sung Ho Hwang
  • Patent number: 8281042
    Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Young Son, Gyu Sang Choi, Jae Don Lee, Choong Hun Lee
  • Patent number: 8260978
    Abstract: A service device that comprises a storage drive, where the storage drive includes an installer program, a device driver, and a mass storage interface. The mass storage interface is configured to enumerate the storage drive to a client device when the service device is coupled to the client device for a first time. The client device auto-launches the installer program in response to the service device being enumerated to the client device for the first time. The installer program installs the device driver in the client device in response to being auto-launched.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: September 4, 2012
    Assignee: Marvell International Ltd.
    Inventors: Kevin Thompson, Eric J. Luttmann, David Watkins
  • Patent number: 8260983
    Abstract: A recording and/or reproducing apparatus includes a plurality of devices in which a first device has a connecting unit connected with a host device to perform a data transfer with the host device, a second device shares a temporarily recording area with the first device to perform the data transfer between the first and second devices via the temporarily recording area, and the data transfer is performed by using the temporarily recording area shared with the first device and using the connecting unit of the first device when the second device performs the data transfer with the host device, in this way, a power consumption is reduced.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 4, 2012
    Assignees: Hitachi Consumer Electronics Co., Ltd., Hitachi-LG Data Storage, Inc.
    Inventors: Hisahiro Hayashi, Toshihiro Kato, Manabu Katsuki, Mitsuo Kurokawa, Atsushi Fuchiwaki
  • Patent number: 8255590
    Abstract: Even if a write operation onto a storage media on an external storage device is interrupted, consistency of management information on the storage media is improved. An image file transfer device includes a transferor which transfers an image file stored on a storage media to an external device, a retriever which obtains management information in relation to a file system from a storage media included in the external device, before the transfer of the image file by the transferor, a non-volatile storage which stores the management information obtained by the retriever, and a deleter which deletes the management information stored in the non-volatile storage in response to a completion of the transfer of the image file by the transferor.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: August 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomikura, Masafumi Nosaka, Ryohei Wakai, Ryohei Kinugawa
  • Patent number: 8250250
    Abstract: In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: August 21, 2012
    Assignee: Apple Inc.
    Inventors: Maziar H. Moallem, Richard F. Avra
  • Patent number: 8250267
    Abstract: Various embodiments of systems, methods, computer systems and computer software are disclosed for implementing a control I/O offload feature in a split-path storage virtualization system. One embodiment is a method for providing split-path storage services to a plurality of hosts via a storage area network.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: August 21, 2012
    Assignee: Netapp, Inc.
    Inventor: John Gifford Logan
  • Patent number: 8244929
    Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Ryohei Higuchi
  • Patent number: 8244994
    Abstract: A memory controller mechanism is operable in a first mode and a second mode. In the first mode, a first memory controller portion of the mechanism can use a first set of data terminals to perform a first external bus access operation (EBAO) and a second memory controller portion of the mechanism can use a second set of data terminals to perform a second EBAO. The first and second EBAO operations may be narrow accesses that occur simultaneously. In the second mode, one of the controllers can use both the first and second sets of data terminals to perform a wider third EBAO. The memory controller mechanism can dynamically switch between first mode and second mode operations. In situations in which one of the sets of data terminals would not otherwise be used, performing wide accesses in the second mode using the one set of data terminals improves bus utilization.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 14, 2012
    Assignee: IXYS CH GmbH
    Inventor: Gyle D. Yearsley
  • Patent number: 8244935
    Abstract: A computer readable storage medium comprising software instructions, which when executed by a processor, perform a method, the method including obtaining a first non-optional Input/Output (I/O) request from an I/O queue, determining that a second non-optional I/O request and an optional I/O request are adjacent to the first non-optional I/O request, generating a new data payload using a first data payload from the first non-optional I/O request, a second data payload for the second non-optional I/O request, and a third data payload corresponding to the optional I/O request, wherein the third data payload is interposed between the first data payload and the second data payload, generating a new non-optional I/O request comprising the new data payload, and issuing the new non-optional I/O request to a storage pool, wherein the new data payload is written to a contiguous storage location in the storage pool.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: August 14, 2012
    Assignee: Oracle International Corporation
    Inventors: Adam H. Leventhal, Jeffrey S. Bonwick
  • Patent number: 8239636
    Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. Alternatively, an acquired data stream includes an association with an inversion bit. The inversion bit is acquired and stored separately from the data stream. As the data stream is transferred, if the inversion bit is set then the stream is inverted during the transfer of the stream to a target.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Anthony Moschopoulos
  • Patent number: 8230110
    Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 24, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Srihari Vegesna, Sarin Thomas
  • Patent number: 8224182
    Abstract: Reduction in power consumption at low costs is realized by a system with apparatuses connected with each other. A switch device comprises transmission/reception unit each connected to each of apparatuses through a communication cable for transmitting/receiving a signal to/from each apparatus, and a connection switching unit for switching connection between the apparatuses by switching connection between the transmission/reception unit. Further provided are a reception state monitoring unit for monitoring a signal reception state of the transmission/reception unit, and a transmission stopping unit for executing signal transmission stopping processing according to a monitoring result obtained by the reception state monitoring unit with respect to other transmission/reception unit to which connected through that communication cable is other apparatus having a connection relationship with the apparatus to which the transmission/reception unit is connected through the communication cable.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: July 17, 2012
    Assignee: NEC Corporation
    Inventor: Shuhei Kondo
  • Patent number: 8219742
    Abstract: The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: July 10, 2012
    Assignee: TDk Corporation
    Inventor: Yukio Terasaki
  • Patent number: 8209703
    Abstract: A computer readable storage medium includes executable instructions to assess system cache resources, inter-process communication requirements and staging requirements to divide an extract, transform, load (ETL) dataflow task into a plurality of sub-tasks. The sub-tasks are then executed in parallel on distributed resources.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: June 26, 2012
    Assignee: SAP France S.A.
    Inventors: Monfor Yee, Wu Cao, Hui Xu, Anil Kumar Samudrala, Balaji Gadhiraju, Kurinchi Kumaran, David Kung
  • Patent number: 8209711
    Abstract: A system and method are provided for managing reader and writer threads in a caching proxy server. In general, a caching proxy server operates as an intermediary between a web server and a number of client devices. The clients send requests for digital assets hosted by the web server to the caching proxy server. For each request, or more particularly for each group of concurrent requests, for a particular digital asset, the caching proxy server operates in either a decoupled writer mode of operation or a reader/writer mode operation. In addition, while serving the requests, the proxy server may switch between the decoupled writer and the reader/writer modes of operation depending on one or more criteria.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: June 26, 2012
    Assignee: Qurio Holdings, Inc.
    Inventors: Richard J. Walsh, Alfredo C. Issa, James Evans
  • Patent number: 8200890
    Abstract: First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 12, 2012
    Assignee: TDK Corporation
    Inventors: Yukio Terasaki, Takeshi Kamono
  • Patent number: 8200799
    Abstract: A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: June 12, 2012
    Assignee: QST Holdings LLC
    Inventors: W. James Scheuermann, Eugene B. Hogenauer
  • Patent number: 8195844
    Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 5, 2012
    Assignee: Siemens Aktiengesellschaft
    Inventors: Temple L. Fulton, Steven M. Hausman, William K. Bryant
  • Patent number: 8190699
    Abstract: In a particular embodiment, a multi-path bridge circuit includes a backplane input/output (I/O) interface to couple to a local backplane having at least one communication path to a processing node and includes at least one host interface adapted to couple to a corresponding at least one processor. The multi-path bridge circuit further includes logic adapted to identify two or more communication paths through the backplane interface to a destination memory, to divide a data block stored at a source memory into data block portions, and to transfer the data block portions in parallel from the source memory to the destination node via the identified two or more communication paths.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 29, 2012
    Assignee: Crossfield Technology LLC
    Inventors: Brett McMillian, Gary McMillian, Dennis Ferguson
  • Patent number: 8185671
    Abstract: A plurality of registers may function as both the control and status registers. Each bit location of the registers is writable to set a value on a control signal and readable to read a current value on a status signal. A multiplexer provides readability of the current value of each of the registers.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventor: Nathan C. Chrisman
  • Patent number: 8185668
    Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Souta Kusachi, Go Sugizaki, Satoshi Nakagawa
  • Patent number: 8180935
    Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: May 15, 2012
    Assignee: LSI Corporation
    Inventors: William K. Petty, Brian A. Day, Timothy E. Hoglund
  • Patent number: 8176219
    Abstract: A network device is described that concurrently executing more than one instance of an operating system on a single processor. Each of the instances of the operating system executes completely independent of the other instances. In this way, disparate instances may exist for the same operating system or for different operating systems. The techniques allow the processor to concurrently execute, for example, an instance of the operating system may emulate a routing engine and an instance of the operating system may emulate an interface controller. A hyper scheduler performs context switches between the operating systems to enable the processor to concurrently execute the instances of the operating system. The techniques may provide a low cost alternative to employing multiple processors within a network device, such as a router, to execute multiple independent operating systems.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: May 8, 2012
    Assignee: Juniper Networks, Inc.
    Inventor: John Sullivan
  • Patent number: 8176217
    Abstract: The present invention is a system for implementing a storage protocol with initiator controlled data transfer including a host device, a target device and an intermediate device, the intermediate device for communicatively coupling the host device and the target device. The intermediate device is configured to control a data transfer phase of an input/output (I/O) between said intermediate device and said target device.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventor: Russell J. Henry
  • Patent number: 8176218
    Abstract: Apparatus and methods for real-time routing of received frames in a split-path architecture storage controller. In one exemplary embodiment, a split-path storage controller comprises a soft-path I/O processor for processing of any received frames and comprises a fast-path I/O processor for efficient processing of common read and write command. A content parsing circuit of the storage controller parses each frame substantially concurrent with reception of the frame and selects an I/O processor for processing of an initial frame and subsequent related frames. Received frames are then routed concurrently as they are received for processing by the selected I/O processor of the multiple I/O processors of the split-path storage controller.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventors: Howard Young, Dante Cinco, Thomas P. Anderson
  • Patent number: 8171185
    Abstract: This invention provides an electronic device that can suppress the undesired influence of signals flowing on the bus as interference on devices connected to the bus. The electronic device has two ports connected to the bus with corresponding physical layer processing means. The physical layer processing means may optionally be connected together permitting separate connection to separate busses. Thus a bus reset on first bus will not interfere with processing on the second bus.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 1, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Toru Nakamura
  • Patent number: 8171178
    Abstract: A command is issued to a first data storage system for addressing a set of data and at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system. The at least one of a first referral response is accessed. A command is issued to the second data storage system for addressing the set of data and a second referral response including a referral to at least one of the first data storage system and a third data storage system, the second data storage system including at least a second subset of the set of data. The second subset of the set of data and the second referral response including the referral to the at least one of the first data storage system or the third data storage system is accessed.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: May 1, 2012
    Assignee: LSI Corporation
    Inventors: Ross E. Zwisler, Andrew J. Spry, Gerald J. Fredin, Kenneth J. Gibson
  • Patent number: 8166217
    Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
  • Publication number: 20120096193
    Abstract: In a communication apparatus data is inputted to an input section. A priority determination section determines priority of the data inputted by the input section. If the priority of the data determined by the priority determination section is higher than a determined value, then a speed control section sets a transmission speed of the data outputted from an output section to a high value. On the other hand, if the priority of the data determined by the priority determination section is lower than the determined value, then the speed control section sets the transmission speed of the data outputted from the output section to a low value. The output section outputs the data at the set transmission speed.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 19, 2012
    Inventor: Naozumi ANZAI
  • Publication number: 20120096192
    Abstract: The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. 14).
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: HITACHI, LTD.
    Inventors: Katsuya Tanaka, Masanori Takada
  • Patent number: 8161212
    Abstract: An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request and a first memory coupled to the interface. The first memory can be configured to store a data unit specified by the source request. The system can include an I/O device controller coupled to the interface. The I/O device controller can be configured to correlate the source request with a plurality of I/O device requests and initiate sending of the plurality of I/O device requests to the plurality of non-volatile I/O devices in parallel. The system also can include a decoder coupled to the first memory and the I/O device controller. The decoder can be configured to receive data from the plurality of non-volatile I/O devices in parallel.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: April 17, 2012
    Assignee: Xilinx, Inc.
    Inventors: Ting Lu, Kam-Wing Li, Bradley L. Taylor
  • Patent number: 8156252
    Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: April 10, 2012
    Assignee: SMART Modular Technologies, Inc.
    Inventor: Ryan McDaniel
  • Patent number: 8151015
    Abstract: Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 3, 2012
    Assignee: Sony Corporation
    Inventors: Tsuyoshi Kano, Mitsuki Hinosugi, Masato Kajimoto, Yoichi Mizutani
  • Patent number: 8151012
    Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Changkyu Kim, Albert Lin, Christopher J. Hughes, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Zeshan A. Chishti, Bryan K. Casper
  • Patent number: 8145803
    Abstract: Disclosed is provided an apparatus and a method for operating a macro command and inputting a macro command, wherein the apparatus including a storing unit storing control signals received from a control device for selecting of a menu item of a host device, a creating unit creating the macro command combined with the control signals, and an executing unit reading the macro command and executing functions corresponding to the respective menu item of the host device according to a combination sequence of the control signals included in the read macro command.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-chul Hwang, Eun Namgung
  • Patent number: 8144635
    Abstract: A first device comprising: a pin interface having a plurality of pins; a data signal transmitter configured to respectively transmit, to a second device, a first plurality of data signals over a first set of pins of the plurality of pins of the pin interface; an encoder configured to generate a first encoded control signal based on having encoded a first plurality of control signals; and a control signal transmitter configured to transmit, to the second device, the first encoded control signal over a first pin of the plurality of pins of the pin interface, wherein the first pin is not of the first set of pins.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: March 27, 2012
    Assignee: Marvell International Ltd.
    Inventor: William Lo
  • Patent number: 8145802
    Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Scott M Carlson, Greg A Dyck, Tan Lu, Kenneth J Oakes, Dale F Riedy, Jr., William J Rooney, John S Trotter, Leslie W Wyman, Harry M Yudenfriend
  • Patent number: 8130194
    Abstract: Method and system for generating and processing multiple independent input data streams based on a high priority OS message framework such as an OS provided framework for processing mouse-messages. Multiple input devices generate motion that is sensed by motion sensors located on one or more motion sources, quantify the sensed motion, and provide resulting input data to a computer via one or more communication ports. One or more software subroutines process the provided data, separating them into multiple independent input streams according to their sources, and sending the streams to listening applications. The subroutines are preferably integrated at a low level of the OS architecture, thereby enabling low-latency, fully-functional high priority processing of the input data.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: March 6, 2012
    Assignee: IMI Innovations, Inc.
    Inventors: James R. Fairs, Lee A. Mitchell, Vlad Zarney, Michael J. Borch
  • Patent number: 8127051
    Abstract: An apparatus and method for sharing a bus in a mobile telecommunication handset are provided. In one embodiment, a mobile telecommunication handset comprises a first device, a second device, a shared bus, a memory configured to store a reference clock frequency, and a controller configured to simultaneously receive first data from the first device and transmit second data to the second device via the shared bus based on a clock signal of the reference clock frequency. The first device is configured to forward the first data received by the controller, and the second device is configured to receive the second data transmitted by the controller.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: February 28, 2012
    Assignee: LG Electronics Inc.
    Inventor: Sang-Rae Lee
  • Patent number: 8127047
    Abstract: Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command including random IO processing and the reception of commands is complete, it determines whether the valid extents prescribed in seek parameters attached to an LOC command overlap, and executes extent exclusive wait processing which causes access to the logical volume to enter a wait state or access processing to the logical volume based on the determination result. If the reception of commands is incomplete, the controller determines whether the access ranges (extents) designated in a DX command overlap, and executes extent exclusive wait processing or access processing to the logical volume based on the determination result.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: February 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ran Ogata, Akihiro Mori, Junichi Muto, Kazue Jindo
  • Patent number: 8127052
    Abstract: A data transfer control device includes a control component (DMA controller 5) which acquires a data transfer instruction including, as its parameters, start memory addresses or start input/output addresses and data transfer size of the peripheral devices to be used as the transfer source and transfer destination when carrying out data transfer from a first peripheral device (peripheral (A)) to a second peripheral device (peripheral (B)); which reads out target data from the first peripheral device in accordance with the parameters; and which processes the target data and then transfers to the second peripheral device.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Keisuke Yoshioka
  • Patent number: 8122204
    Abstract: Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for receiving the command signal and the address signal from the memory controller, where the first memory device comprises a first command judging circuit for receiving and forwarding the data signal and for decoding the command signal. The memory system further comprises a second memory device for receiving the command signal and the address signal from the memory controller, where the second memory device comprises a second command judging circuit for receiving and generating the data signal and for decoding the command signal. The command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: February 21, 2012
    Assignee: Spansion LLC
    Inventors: Mitsuhiro Nagao, Kenji Shibata, Satoru Kawmoto
  • Patent number: 8117345
    Abstract: A signal processing device is a predetermined signal processing device among signal processing devices which perform signal processing on an input signal that is input to any one of the signal processing devices in such a manner that the signal processing devices share signal processing. The signal processing device includes a signal processing section that performs signal processing on a first-bandwidth signal, which is included in the input signal, in accordance with a processing capability of the signal processing device to generate a first output signal; and a signal integration section that integrates a second output signal with the first output signal, and that outputs the integrated signal to a second different signal processing device, the second output signal being generated in a first different signal processing device by performing signal processing on a second-bandwidth signal, which is included in the input signal.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 14, 2012
    Assignee: Sony Corporation
    Inventors: Masaaki Hattori, Tetsujiro Kondo