Abstract: A computing system includes a host processor, a plurality of accelerators that communicate with the host processor based on a communication interface, and a plurality of memory nodes that are connected with the plurality of accelerators through an interconnection network. A first data link is established between a first accelerator of the plurality of accelerators and a first memory node of the plurality of memory nodes, and a second data link is established between the first accelerator and a second memory node of the plurality of memory nodes.

Abstract: Methods and systems for executing an application data flow graph on a set of computational nodes are disclosed. The computational nodes can each include a programmable controller from a set of programmable controllers, a memory from a set of memories, a network interface unit from a set of network interface units, and an endpoint from a set of endpoints. A disclosed method comprises configuring the programmable controllers with instructions. The method also comprises independently and asynchronously executing the instructions using the set of programmable controllers in response to a set of events exchanged between the programmable controllers themselves, between the programmable controllers and the network interface units, and between the programmable controllers and the set of endpoints. The method also comprises transitioning data in the set of memories on the computational nodes in accordance with the application data flow graph and in response to the execution of the instructions.

Abstract: A circuit for coupling a field bus and a local bus. A field bus controller is equipped to send and receive process data over the field bus. A local bus controller is equipped to send and receive the process data over the local bus. A data management unit is connected to the field bus controller and the local bus controller. The data management unit is equipped to transfer the process data between field bus controller and local bus controller. A memory area connected to the data management unit for copying and storing the process data. A processor connected to the data management unit and connected to the memory area. The processor is equipped to set up the data management unit to copy the process data into the memory area and the processor is equipped to read out the process data copied in the memory area.

Abstract: Memory controllers and decoders of memory systems and methods for operating the same, which employ smart scheduling of commands to be processed to reduce overall execution time. A metric function is applied to determine or update the priority of each of the multiple commands in multiple queues based on expected execution time and expected wait time such that the smart scheduling scheme provides significant improvement in terms of quality-of-service (QoS) of the memory system.

Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

Abstract: A microcontroller system comprising a master microcontroller unit, a further module and a general purpose input/output. In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.

Abstract: The present invention relates to a VCRM data transmission optimizing method and an apparatus therefor, and a method of transmitting VCRM data in a vehicle terminal may include generating at least one data slot buffer, determining whether to perform buffer flush according to whether data is changed, and whether a buffer max size is reached, when new data is entered, and flushing data recorded in a corresponding data slot buffer according to the determination for performing the buffer flush to be transmitted to a server over a wireless network.

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

Abstract: A content retrieval system uses a graph neural network architecture to determine images relevant to an image designated in a query. The graph neural network learns a new descriptor space that can be used to map images in the repository to image descriptors and the query image to a query descriptor. The image descriptors characterize the images in the repository as vectors in the descriptor space, and the query descriptor characterizes the query image as a vector in the descriptor space. The content retrieval system obtains the query result by identifying a set of relevant images associated with image descriptors having above a similarity threshold with the query descriptor.

Abstract: This invention relates to computer engineering and operating system components, in particular, it discloses a new method of building a hierarchal file system, which provides new functionality and flexibility, including: unlimited maximum possible file system size (number of elements), unlimited size of a single element, unlimited types of data, that can be represented as a file. In addition, the disclosed file system allows for user-defined types of data and can be used as a registry for OS system components, saving space important for resource-restricted embedded systems. The minimum file system size is 2 Bytes only. File system supports empty or non-unique files naming and natively provides built-in security using specification-based nodes header encoding. This result is achieved by using file systems nodes metadata comprising: the unique identifier (ID), an ASN.1 header with PER encoding, and a doubly linked list of logical blocks of its data.

Abstract: An example operation may include one or more of receiving an event from a node, extracting an identifier from the event, determining whether the event is authorized, and generating a notification of the event when the identifier is authorized, wherein the identifier includes a hashed value of an event counter and wherein the identifier is authorized when the hashed value matches a hashed value of the event counter stored in a storage area of or coupled to the client.

Abstract: Provided are a computer program product, system, and method for processing request directed through a channel subsystem to a storage server. In one embodiment, a pattern search request is embedded in a Device Command Word (DCW) which allows the storage server to do all or substantially all of the search and comparison work in response to as few as a single DCW from the host. In addition, I/O processing can be enhanced to use the target record of interest of a successful embedded pattern search request as the starting point for read/write I/O processing, all in response to as few as a single DCW. Still further, orientation rules can also be relaxed such that once a target record is found, any and all fields of the record can be accessed and utilized in execution of subsequent commands of the initial or subsequent DCWs of the chain.

Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.

Abstract: A storage system is provided. The storage system includes a storage device including a plurality of nonvolatile memories configured to transmit storage throughput information, and a host device configured to change connection configurations for the storage device based on the storage throughput information, wherein the host device changes the connection configurations by changing configurations for transmitter and receiver paths between the storage device and the host device independently.

Abstract: A data driven workflow solution that normalizes business communications by systematically recording related business communications from disparate communications channels in a common format such that the related business communications are automatically integrated into the associated business processes and which flow solution is flexible for capturing additional data elements or to adapt to changing tasks associated with the business processes is disclosed.

Abstract: A content retrieval system uses a graph neural network architecture to determine images relevant to an image designated in a query. The graph neural network learns a new descriptor space that can be used to map images in the repository to image descriptors and the query image to a query descriptor. The image descriptors characterize the images in the repository as vectors in the descriptor space, and the query descriptor characterizes the query image as a vector in the descriptor space. The content retrieval system obtains the query result by identifying a set of relevant images associated with image descriptors having above a similarity threshold with the query descriptor.

Abstract: A method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to a RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array, but will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of any missing data of the second strides from the RAID array into the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method destages, from the cache, the second strides from the cache to the RAID array. A corresponding system and computer program product are also disclosed.

Abstract: Disclosed herein are techniques for scheduling and executing multi-layer neural network computations for multiple contexts. In one embodiment, a method comprises determining a set of computation tasks to be executed, the set of computation tasks including a first computation task and a second computation task, as well as a third computation task and a fourth computation task to provide input data for the first and second computation tasks; determining a first execution batch comprising the first and second computation tasks; determining a second execution batch comprising at least the third computation task to be executed before the first execution batch; determining whether to include the fourth computation task in the second execution batch based on whether the memory device has sufficient capacity to hold input data and output data of both of the third and fourth computation; executing the second execution batch followed by the first execution batch.

Abstract: A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.

Abstract: A DMA (Direct Memory Access) transfer apparatus acquires information including a transfer source address and a transfer destination address based on a received transfer instruction, selects whether to perform first checksum calculation for data from an area of a memory corresponding to the transfer source address or perform second checksum calculation different from the first checksum calculation, and transfers data obtained via the checksum calculation selected in the selecting to an area of the memory corresponding to the transfer destination address.

Abstract: A processing system includes a set of queues to store command buffers prior to execution in a corresponding plurality of pipelines. The processing system also includes one or more first doorbells and a second doorbell. The first doorbells map to one or more queues in the set of queues on a one-to-one basis. The second doorbell maps to a subset of the set of queues on a one-to-many basis. A doorbell monitor generates an interrupt in response to an empty queue in the subset becoming a non-empty queue. A scheduler polls the subset in response to the interrupt. The scheduler schedules a command buffer from the non-empty queue for execution or adds the command buffer to a pool for subsequent execution.

Abstract: A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

Abstract: A computing device comprises a main memory, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU may receive an upstream IO write request to the main memory from the IO device, and bypass caching the write request if the write request is within a first memory region of the main memory associated with a non-volatile memory. The IOMMU may cache the write request if the write request is within a second memory region of the main memory associated with a volatile memory.

Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.

Abstract: An access control method includes: determining a number of a plurality of commands to be continuously transferred; transferring to a storage device, a transfer preparation completion command indicating that preparation for transfer of the plurality of commands is completed, when it is determined that the number is greater than or equal to a threshold value; transferring, in sequence, to the storage device, the plurality of commands when it is determined that the number is less than the threshold value; when a command transferred from the host device is the transfer preparation completion command, issuing a direct memory access request to the host device based on the transfer preparation completion command and receiving the plurality of commands transferred from the host device by a direct memory access method based on the direct memory access request; and accessing the storage, based on each of the plurality of commands received.

Abstract: Technologies for zero-copy inter-virtual-machine communication include a computing device with extended page table support. A sender virtual machine stores data in a shared memory block and enables access to protected code without generating a virtual machine exit, for example by executing a specialized processor instruction. From the protected code, the sender virtual machine sets a permission in an extended page table associated with the shared memory block and notifies a receiver virtual machine. When the permission is set, the sender virtual machine is prohibited from writing or executing the contents of the shared memory block. The receiver virtual machine reads data from the shared memory block and then enables access to protected code without generating a virtual machine exit. From the protected code, the receiver virtual machine clears the permission and notifies the sender virtual machine that reading is complete. Other embodiments are described and claimed.

Abstract: The invention is directed a method for transferring at least one datum between a real-time task producing a datum and a real-time task consuming said datum. The method may include, in response to initiation of a transfer of a datum by a current instance of an initiating task: creating at least one DMA descriptor describing the DMA transfer expected for said datum; inserting DMA descriptors into a list of descriptors awaiting processing by a DMA controller, said DMA descriptors being inserted in a manner sorted based on a sorting criterion relating to a visibility date of the data and/or a temporal behavior of the tasks; processing the descriptors on the list of DMA descriptors by executing DMA requests; and executing the following instance of the initiating task based on termination of the processing a predefined set of DMA descriptors on the list of descriptors.

Abstract: A data storage system that implements identifying data store requests for asynchronous processing. A request may be received at a frontend task engine that processes requests for a network-based data store. The frontend task engine may evaluate the request to determine whether the request should be processed asynchronously. For a request identified for asynchronous processing, the task engine may initiate processing of the request at backend task engines for the network-based data store. Resources for processing the request at the frontend task engine may be reclaimed for processing other requests. A task sweeper that collects data for the network-based data store may detect that processing of the request has completed. The task sweeper may also provide an indication of the completion of the request.

Abstract: Embodiments of the present invention disclose an Ethernet data processing method, an Ethernet physical layer chip, and Ethernet equipment. Applicable to data processing at a transmit end, the method includes: performing line coding on data from a media access control layer, so as to obtain serial data code blocks; performing forward error correction FEC coding on the serial data code blocks, so as to obtain FEC frames, which specifically includes: inserting Y check bits every X consecutive data bits, where the Y check bits are generated when FEC coding is performed on the X consecutive data bits; and distributing, at a distribution granularity of a bits, the FEC frames successively to N virtual channels, where a and N are both positive integers, and a is less than a quantity of bits included in one FEC frame.

Abstract: The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location.

Abstract: Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.

Abstract: A method for controlling access to a memory of a computer system configured with at least one logical partition may include receiving a first request to map a first page of the memory, the request identifying a first requester. A first logical partition associated with the first page may be determined. It may be determined that an attribute of the first logical partition limits access to individual pages of the first logical partition to a single requester, and that the first page is available to be mapped to a requester. The first page may be mapped to the first requester and a flag indicating that the first page is unavailable for an additional mapping may be set. The first request may be from a device driver on behalf of an input/output adapter, as the first requester, to use the first page in a direct memory access transfer.

Abstract: A system for collaborative decision-making and more efficient disaster management, in which multiple geobrowsers can communicate over local networks and/or the Internet to create a real collaborative experience when dealing with geospatial information, distributed using Open Geospatial Consortium (OGC) compliant KML/KMZ formats, WMS (Web Mapping Service), or and geospatial data files. All manipulation functions (dataset loading, layer stacking, layer visibility changes, Point of View (POV) changes, map extent changes, looping and animation settings, geospatial file creation and annotation drawing, and other functions) are replicated across all connected geobrowsers to create a true collaborative geospatial Common Operating Picture (COP). The leadership role can be handed over to other users if desired to build upon all the datasets and annotations sent by previous leads.

Abstract: A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.

Abstract: Improved clustered storage systems make use of a software toggle switch stored in a shared persistent configuration database, which allows a peer node to be rebooted into a FIPS 140 mode defined by the switch and then to take over as master while the original master node reboots into the new FIPS 140 mode as defined by the switch. Advantageously, system availability is maintained as the nodes are rebooted sequentially while a master is always available. The persistent switch allows for synchronization, while also allowing persistence of state even in the event of a system crash.

Abstract: A two-level paging mechanism. The first level gathers data from reclaimable memory locations for a process and compacts the data into a single container. The second level sends the compact container's contents to a swap file and may use optimal I/O operations to the target memory device. On-demand paging is made possible by having a first pager locate the requested data in the compact container and then having a second pager retrieve the corresponding data from the swap file.

Abstract: A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.

Abstract: A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.

Abstract: In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

Abstract: According to one embodiment, an electronic device includes an execution module, and an execution controller. The execution controller is configured to, when a key operation is entered while demonstration data is being executed, move an execution position in the demonstration data in units of blocks correspondingly to the key operation. The executing module is configured to start the execution of the demonstration data from the moved execution position.

Abstract: Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a set of transaction control registers to receive a sequence of transaction control sets that collectively describe a data transfer to be processed by the DMA controller. A bus controller reads and writes to memory while the DMA controller executes a first transaction control set to accomplish part of the data transfer described in the sequence of transaction control sets. An integrity checker determines an actual error detection code based on data or an address actually processed by the DMA controller during execution of the first transaction control set. The integrity checker also selectively flags an error based on whether the actual error detection code is the same as an expected error detection code contained in a second transaction control set of the sequence of transaction control sets.

Abstract: An apparatus includes an array of universal digital blocks (UDBs) and a central processing unit (CPU) coupled to the array of UDBs via a bus. The UDBs may be coupled together to perform tasks, operations or functions that may be offloaded from the CPU to the array of UDBs.

Abstract: Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation. The search context may be maintained in a manner that obviates overflow of the search context and obviating stalling of the push or pop operations to increase match performance.

Abstract: A storage device of a storage system includes a device Direct Memory Access (DMA) configured to calculate a data transfer amount based on size information of data provided to a DMA queue; a command manager configured to receive the data transfer amount from the device DMA and to calculate a transfer speed using a speed mode table; and a device interface configured to transfer the transfer speed to a host.

Abstract: A system includes a serial interface, a peripheral device coupled to the serial interface, non-volatile memory, and a DMA controller including multiple linked channels. The various channels can be configured in different modes to facilitate the DMA controller performing various operations, such as data transfer, with respect to the non-volatile memory or the peripheral device.

Abstract: The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal and receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal.