Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

Abstract: A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention.

Abstract: A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.

Abstract: A robotic tape library which queues two or more move instructions is described. Generally, the robotic system receives a first move instruction which commands a first robot to move a first tape cartridge from a shelf to a first tape drive to be loaded therein. Though the first move has not actually taken place, the library replies to the host computer that the first tape drive has been loaded with the first tape cartridge, at least to an acceptable level of engagement, at which point, the first move instruction is queued. After receiving a second move instruction from the host to move a second tape cartridge from the shelf to a second tape drive, the library reorganizes and physically carries out the move instructions with potentially different hardware in a preferred order.

Abstract: A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Direct Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.

Abstract: In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.

Abstract: APIs discussed herein promote efficient and timely interoperability between hardware and software components within the media processing pipelines of media content players. A PhysMemDataStructure API facilitates a hardware component's direct access to information within a memory used by a software component, to enable the hardware component to use direct memory access techniques to obtain the contents of the memory, instead of using processor cycles to execute copy commands. The PhysMemDataStructure API exposes one or more fields of data structures associated with units of media content stored in a memory used by a software component, and the exposed fields store information about the physical properties of the memory locations of the units of media content. SyncHelper APIs are used for obtaining information from, and passing information to, hardware components, which information is used to adjust the hardware components' timing for preparing media samples of synchronously-presentable media content streams.

Abstract: Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions.

Abstract: An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: The present invention concerns a control device (1) provided for smart card readers (SCR), a smart card reading activation device (2) and associated products including a set-top box and a daisy chain. The control device comprises means for communicating (11) with at least two smart card reading devices (SCR3, SCR4, SCR5), means for processing (12) information received from those reading devices and means for activating (13) at least one of those reading devices for a current communication. The activating means are intended to send selection data (SD) towards all those reading devices, those selection data enabling each of the reading devices to determine if it is selected or not for the current communication.

Abstract: A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a transport command word (TCW) at a channel subsystem for an I/O operation, the TCW including an address of a transport command control block (TCCB) having a transport command area (TCA) configured to hold a first plurality of device command words (DCW) and control data associated with respective DCWs, the first plurality of DCWs including a transfer TCA extension (TTE) DCW that specifies a TCA extension, the TCA extension configured to hold one or more DCWs and control data associated with respective DCWs; gathering the TCCB from one or more locations specified in the TCCB address and transferring the TCCB to the control unit; gathering the TCA extension specified by the TTE DCW; and transferring the TCA extension to the control unit.

Abstract: A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.

Abstract: A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.

Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.

Abstract: A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.

Abstract: One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer.

Abstract: A robotic tape library which queues two or more move instructions is described. Generally, the robotic system receives a first move instruction which commands a first robot to move a first tape cartridge from a shelf to a first tape drive to be loaded therein. Though the first move has not actually taken place, the library replies to the host computer that the first tape drive has been loaded with the first tape cartridge, at least to an acceptable level of engagement, at which point, the first move instruction is queued. After receiving a second move instruction from the host to move a second tape cartridge from the shelf to a second tape drive, the library reorganizes and physically carries out the move instructions in a preferred order.

Abstract: Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption.

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Abstract: Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.

Abstract: A command portal enables a host system to send non-standard or “vendor-specific” storage subsystem commands to a storage subsystem using an operating system (OS) device driver that does not support or recognize such non-standard commands. The architecture thereby reduces or eliminates the need to develop custom device drivers that support the storage subsystem's non-standard commands. To execute non-standard commands using the command portal, the host system embeds the non-standard commands in blocks of write data, and writes these data blocks to the storage subsystem using standard write commands supported by standard OS device drivers. The storage subsystem extracts and executes the non-standard commands. The non-standard commands may alternatively be implied by the particular target addresses used. The host system may retrieve execution results of the non-standard commands using standard read commands.

Abstract: A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.

Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.

Abstract: A robotic tape library which queues two or more move instructions is described. Generally, the robotic system receives a first move instruction which commands a first robot to move a first tape cartridge from a shelf to a first tape drive to be loaded therein. Though the first move has not actually taken place, the library replies to the host computer that the first tape drive has been loaded with the first tape cartridge, at least to an acceptable level of engagement, at which point, the first move instruction is queued. After receiving a second move instruction from the host to move a second tape cartridge from the shelf to a second tape drive, the library reorganizes and physically carries out the move instructions with potentially different hardware in a preferred order.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers by virtualizing DMA transfer requests into available DMA channel identifiers using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once an input value associated with the DMA transfer request is mapped to the selected DMA channel identifier, the DMA transfer is performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfer. When there is a request to wait for completion of the data transfer, the same input value is used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A method and apparatus for accessing information from a network device, said device being managed through a command line interface, said method comprising storing information regarding operation of the device in a hierarchical structure in a memory within the device, searching for a command line management feature or configuration by passing a search command to the device and then passing a command relating to the feature name or configuration to the device, whereby the device then searches through the hierarchical data structure for the feature name or configuration in which the search command is provided in the first layer of the hierarchical structure in the memory and the feature name or configuration is provided in the second layer of the hierarchical structure in the memory within the device.

Abstract: Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.

Abstract: A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be tra

Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: Scheduling Direct Memory Access (DMA) operations. Blocks are provided in a first DMA chain, with each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer pointing to a command structure to be executed or a data structure to be moved, and a second pointer pointing to a next block in the first DMA chain. A DMA engine processes successive operations in the first DMA chain. Time remaining in an interval for processing the first DMA chain is tracked. A second DMA chain of conditional blocks are maintained, with each conditional block corresponding to a conditional operation and containing an estimate of time needed to complete the conditional operation. A conditional operation is executed from the second DMA chain if the remaining time in the interval is greater than the estimated time to complete processing of the conditional operation.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor.

Abstract: A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attribute out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attribute different from the attribute in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined.

Abstract: According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

Abstract: Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance optimization functions. The present invention also provides a new flag in the machine status register (MSR) to enable or disable a performance monitoring application or process to perform code-patching functions. If the code patching function is enabled, the application or process may patch code at run time by associating the metadata with the selected instructions. The metadata includes pointers pointing to the patch code block code. The program code may be patched autonomically without modifying original code.

Abstract: Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command including random IO processing and the reception of commands is complete, it determines whether the valid extents prescribed in seek parameters attached to an LOC command overlap, and executes extent exclusive wait processing which causes access to the logical volume to enter a wait state or access processing to the logical volume based on the determination result. If the reception of commands is incomplete, the controller determines whether the access ranges (extents) designated in a DX command overlap, and executes extent exclusive wait processing or access processing to the logical volume based on the determination result.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: An apparatus generally having a processor and a direct memory access controller is disclosed. The processor may be configured to increment a task counter to indicate that a new one of a plurality of tasks is scheduled. The direct memory access controller may be configured to (i) execute the new task to transfer data between a plurality of memory locations in response to the task counter being incremented and (ii) decrement the task counter in response to the executing of the new task.

Abstract: A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.

Abstract: A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying a first predetermined sequence number for performing a first set of one or more commands as part of an I/O operation. The method further includes receiving a second command message specifying a second predetermined sequence number for performing a second set of one or more commands as part of the I/O operation. The method also includes comparing the sequence numbers to a next expected predetermined sequence number to determine an order of performing the commands. The method additionally includes executing the commands in the determined order to perform the I/O operation.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Scheduling Direct Memory Access (DMA) operations. Blocks are provided in a first DMA chain, with each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer pointing to a command structure to be executed or a data structure to be moved, and a second pointer pointing to a next block in the first DMA chain. A DMA engine processes successive operations in the first DMA chain. Time remaining in an interval for processing the first DMA chain is tracked. A second DMA chain of conditional blocks are maintained, with each conditional block corresponding to a conditional operation and containing an estimate of time needed to complete the conditional operation. A conditional operation is executed from the second DMA chain if the remaining time in the interval is greater than the estimated time to complete processing of the conditional operation.

Abstract: Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.

Abstract: There is provided an information processing system that includes an integrated circuit chip having stored therein a plurality of file systems, a first information processing apparatus that engages in communication with the integrated circuit chip and a second information processing apparatus that engages in communication with the first information processing apparatus. The first information processing apparatus includes a command packet linking unit that generates a single linked command packet by linking a second command packet generated by the second information processing apparatus within a first command packet and a first command packet transmission unit that transmits the linked command packet to the integrated circuit chip to be directed to the plurality of file systems.