Abstract: Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption.

Abstract: A mechanism is provided for removal of instructions for context re-evaluation. The mechanism receives an external request to perform the instruction remove. In response to this external request, the mechanism next determines when the state of the system is stable for allowing the instruction remove. Then the mechanism creates a first event to remove a current data instruction in a DMA, if present, and merge it back onto the list of pending contexts from where it originated. The mechanism waits for feedback that the first event has completed. Then the mechanism creates a second event to remove a pending data instruction that was chosen to be next in the DMA, if present, and merge it back onto the list of pending contexts from where it originated. Finally the mechanism waits for feedback that the second event has completed.

Abstract: A method for combining partial records into a single direct memory access (DMA) operation for a count key data (CKD) protocol in a computer environment is provided. In an initiator processor of the computer environment, a number of the partial records to be prefetched is determined by gathering a plurality of descriptor information for a command according to a predetermined algorithm having a plurality of assumptions for the command. The number of partial records is prefetched. At least one of record headers and record keys of the number of partial records are concatenated into the single DMA operation. The DMA operation is forwarded to a receiver process to be completed.

Abstract: A method, apparatus, and computer program product for processing a chained-pair linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying that a device command word (DCW) list is encoded in a data message associated with the first command message as part of the chained-pair linked transport control channel program. The method further includes receiving a second command message chained-pair linked to the first command message, the second command message specifying data attributes associated with the DCW list. The method additionally includes extracting the DCW list from the data message in response to receiving the data message, and executing the DCW list.

Abstract: A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting.

Abstract: The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.

Abstract: A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.

Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.

Abstract: Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

Abstract: A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.

Abstract: An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.

Abstract: A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

Abstract: A graphic accelerator including a frame memory and the same interface as a memory of a processor and a graphic accelerating method are provided. The graphic accelerator includes: a frame memory; an accelerator controller having the same interface as a memory of the processor on an input side and recording data, which should be transmitted from the processor to the display device, in the frame memory; and a display DMA (Direct Memory Access) transmitting the data recorded in the frame memory to the display device in a DMA manner. A memory bandwidth of the processor is not reduced even by continuous reading operations based on DMA transmission of the display device, by recording data corresponding to the frame memory in the graphic accelerator disposed outside the processor.

Abstract: A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an available DMA channel identifier using a channel bitmap listing of available DMA channels to select and set an allocated DMA channel identifier. Once the input values associated with the DMA transfer requests are mapped to the selected DMA channel identifier, the DMA transfers are performed using the selected DMA channel identifier, which is then deallocated in the channel bitmap upon completion of the DMA transfers. When there is a request to wait for completion of the data transfers, the same input values are used with the mapping to wait on the appropriate logical channel. With this method, all available logical channels can be utilized with reduced instances of false-sharing.

Abstract: A multiprocessor computing system includes a direct memory access (DMA) engine, a main memory and a host processor including a just-in-time compiler (JIT) that converts bytecode into machine code in discrete executable superblocks (XSBs). The system also includes a system bus coupled to the host processor, the DMA engine and the main memory and allowing communication there between and an auxiliary processing unit (APU) coupled to the system bus and having a local memory, the APU receiving a first XSB from the JIT and storing it in the local memory and loading the one or more next XSBs for execution found in the header of the first XSB into the local memory via the DMA engine.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of input data pieces are divided into a plurality of pieces to perform an operation processing without performing the operation of the arbitrary number of input data pieces at a time. The operational circuit once stores an intermediate result for each of the divided operations in an external storage device, performs an operation processing read with an intermediate result in the next operation processing, and obtains a final result by repeating these operation processings. The operation is performed at a cyclic unit of processing corresponding to the number of address registers provided in the operational circuit.

Abstract: A method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions. DMA I/O operations and performance are improved by reducing the overhead in DMA chaining events by creating a software DMA queue when a hardware DMA queue overflows and dynamically linking new DMA requests to the software queue until a hardware queue becomes available at which time the software queue is put on the hardware queue. Thus, microcode does not need to manage the hardware queues and keep the DMA engine running continuously because it no longer has to wait for microcode to reset the DMA chain completion indicator.

Abstract: A computer program product, apparatus and method for processing a variable length device command word (DCW) at a control unit configured for communication with an input/output (I/O) subsystem in an I/O processing system. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a DCW at the control unit from the I/O subsystem. The DCW specifies one or more I/O operations and includes a command, a control data count, and control data having a varying length specified by the control data count. The control data is extracted in response to the control data count. The command is then executed in response to the extracted control data to perform the specified one or more I/O operations.

Abstract: An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a capsule interface information table including bandwidth information and for setting the forming status of a pair of capsule interfaces and, during data transfer subdivides the descriptors for the capsule interfaces into multiple groups for each data buffer size satisfying the preset bandwidth information and, copies one group at each fixed sample time set by the descriptor registration means, into the descriptor ring and performs DMA transfer. To control this copy information, the IO driver contains a ring scheduler information table for managing the number of descriptor entries for the capsule interface cycle time and, a ring scheduler cancel means for renewing the entries in the ring scheduler information table each time one transmission of the descriptor group ends.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract: A method of packaging locate record commands for device command word (DCW) processing is provided. A first locate record command is packaged into DCW prefix parameter data. The first locate record command includes first search and first seek arguments, a first intent count argument, a first transfer length factor argument, and a plurality of remaining arguments. A plurality of truncated locate record commands is embedded in the DCW prefix parameter data as concatenations to the first locate record command. Each of the plurality of truncated locate record commands include a unique search argument, intent count argument, and transfer length factor argument. Seek argument parameters for each of the plurality of truncated locate record commands are calculated by taking an offset from the first seek argument and the first search argument, applying the offset to each of the plurality of truncated locate record commands. The plurality of remaining arguments is shared.

Abstract: A direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA transfer processing based on the read transfer setting value includes a unit configured to receive a No Operation (NOP) designation for designating no performance of DMA transfer as the transfer setting value, and a unit configured to generate, if the NOP designation has been performed with the transfer setting value read into the register, an NOP interrupt signal to end transfer processing without performing the DMA transfer.

Abstract: Embodiments may comprise logic such as hardware and/or code within a heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously. Many embodiments include multi-buffering logic for implementing a procedure for a processing unit of a specialized processing element. The multi-buffering logic may instruct a direct memory access controller of the specialized processing element to read data from some memory location and store the data in a first buffer. The specialized processing element can then process data in the second buffer and, thereafter, the multi-buffering logic can block read access to the first buffer until the direct memory access controller indicates that the read from the memory location is complete. In such embodiments, the multi-buffering logic may then instruct the direct memory access controller to write the processed data to other memory.

Abstract: A method, medium and system for setting a transfer unit in a data processing system. The method comprises setting a transfer unit in a data processing system which repeatedly performs a process of transmitting data stored in a first memory to a second memory in a predetermined transfer unit, processing the transmitted data stored in the second memory, and transmitting the processed data to the first memory. The method includes computing overhead on the data processing system according to the size of each of a plurality of data units available as the transfer unit; and setting a data unit, which corresponds to a minimum overhead from among the computed overheads, as the transfer unit. Accordingly, it is possible to set an optimum transfer unit according to an environment of a data processing system in order to improve the performance of the data processing system.

Abstract: There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first and second bus. The transfer apparatus controls a transfer sequence of transaction transfers by the bridge and data transfers by the data transfer unit, in which transaction transfers by the bridge are based on bus sequencing rules and data transfers by the data transfer unit are based on a data transfer activation condition.

Abstract: Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from a MCU (micro-controller unit) bus. A system GBL class is selected based on the highest GBL class which has been selected among the GBL classes. A bandwidth limiter of a DMA (direct memory access) unit is assigned according to the system GBL class and the priority of a second task if the DMA unit is activated by the second task. The second task is from a DMA bus, and the cycle between the DMA and MCU buses is determined according to the bandwidth limiter.

Abstract: The invention is provided to improve the information processing efficiency of a multiprocessor system. An information processing apparatus 1000 comprises a main processor 200 for exercising centralized control on the entire apparatus, a graphic processor 100 for performing image processing operations, and a main memory 50. The information processing apparatus 1000 also comprises a DMA controller 28 which controls m (m is an integer, m>1) pieces of data transfer simultaneously, a main memory 50 for data intended for the particular processing is expanded first, and a group of n (n is an integer, n>m) buffers 12 for storing data when the data is transferred from the main memory 50. When a plurality of data transfers are performed simultaneously, a first buffer out of the group of buffers 12 is set as the destination of one of the data transfers, and a second buffer is set as the destination of another data transfer.

Abstract: A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to migrate data from the source physical page to the destination physical page which causes a host bridge to enter a first state. The host bridge then suspends processing of direct memory access operations when the host bridge is in the first state. The data is migrated from the source physical page to the destination physical page while the host bridge is in the first state.

Abstract: In a communication system having a master-slave arrangement communicating with each other using the RS485 protocol, an FPGA with a buffer memory is provided in the master and slave, respectively, to handle the actual communication. The CPUs of the master and slave transfer data to and from the respective buffer memory. The master's FPGA initiates and maintains communication with the slave's FPGA. The masters FPGA and the slave's FPGA communicate with each other using the RS485 protocol by transmitting requests, acknowledgements and data. From the standpoint of the CPUs of the master and slave, the communication appears to be full duplex, although the actual communication between the FPGAs is half duplex. One particular application of the communication method is a KVM switch system where the KVM switch acts as the master and the computers connected to the KVM switch act as slaves.

Abstract: A network interface is disclosed for enabling remote programmed I/O to be carried out in a “lossy” network (one in which packets may be dropped). The network interface: (1) receives a plurality of memory transaction messages (MTM's); (2) determines that they are destined for a particular remote node; (3) determines a transaction type for each MTM; (4) composes, for each MTM, a network packet to encapsulate at least a portion of that MTM; (5) assigns a priority to each network packet based upon the transaction type of the MTM that it is encapsulating; (6) sends the network packets into a lossy network destined for the remote node; and (7) ensures that at least a subset of the network packets are received by the remote node in a proper sequence. By doing this, the network interface makes it possible to carry out remote programmed I/O, even across a lossy network.

Abstract: A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and output data from the buffer per byte, and a rotator for rotating data. The internal memory receives read data from a transfer source, the buffer receives data from the internal memory, the selector receives data from the internal memory and data from the buffer, and the rotator receives data selected by the selector. An output of the rotator is used as write data. Thereby, high-speed DMA transfer is performed even when data transfer source addresses and data transfer destination addresses have different byte alignments where the addresses are located.

Abstract: Provided are an information processing apparatus and a command multiplicity control method that enable easy and proper control of command multiplicity assigned to each host. The information processing apparatus, which executes processing in accordance with a command sent from each of plural hosts, dynamically determines each host's command multiplicity with respect to the information processing apparatus in accordance with command issue frequency of each host, and sets the determined multiplicity for the host. Accordingly, an information processing apparatus that enables easy and proper control of the command multiplicity assigned to each host can be realized.

Abstract: A computer that operates in a metered mode for normal use and a restricted mode uses an input/output memory management unit (I/O MMU) in conjunction with a security policy to determine which peripheral devices are allowed direct memory access during the restricted mode of operation. During restricted mode operation, non-authorized peripheral devices are removed from virtual address page tables or given vectors to non-functioning memory areas.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: A method for coordinating descriptor lists updates between a host computer and a client computer, where the host and the client each maintain respective descriptor lists of bus controller commands. The client computer has a bus controller that changes its descriptor list. The host computer receives from the client computer update commands that, when executed, change the host's descriptor lists in substantially the same manner in which the bus controller changes the descriptor lists on the host computer.

Abstract: A method for combining partial records into a single direct memory access (DMA) operation for a count key data (CKD) protocol in a computer environment is provided. In an initiator processor of the computer environment, a number of the partial records to be prefetched is determined by gathering a plurality of descriptor information for a command according to a predetermined algorithm having a plurality of assumptions for the command. The number of partial records is prefetched. At least one of record headers and record keys of the number of partial records are concatenated into the single DMA operation. The DMA operation is forwarded to a receiver process to be completed.

Abstract: A method of packaging locate record commands for device command word (DCW) processing is provided. A first locate record command is packaged into DCW prefix parameter data. The first locate record command includes first search and first seek arguments, a first intent count argument, a first transfer length factor argument, and a plurality of remaining arguments. A plurality of truncated locate record commands is embedded in the DCW prefix parameter data as concatenations to the first locate record command. Each of the plurality of truncated locate record commands include a unique search argument, intent count argument, and transfer length factor argument. Seek argument parameters for each of the plurality of truncated locate record commands are calculated by taking an offset from the first seek argument and the first search argument, applying the offset to each of the plurality of truncated locate record commands. The plurality of remaining arguments is shared.

Abstract: A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system serial COM port. Data is secured and re-directed to a legacy device via a network port instead of the serial COM port. Conversely, data destined for the host system is provided to a device server via a server COM port by the legacy serial device. The data can be encrypted and sent to the host system via the network. The redirector software module decrypts the encrypted data and presents it to the consumer application as if the data had arrived via the local COM port.

Abstract: The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

Abstract: A data storage system is provided with command queue controller circuitry for positionally pushing pending access commands from a command queue to a selected target zone of a storage space. A method is provided for dividing a storage space into a plurality of LBA zones, selecting a target zone in relation to a number of pending access commands for each of the plurality of LBA zones, and pushing access commands to the target zone.

Abstract: A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: A drive device capable of preventing a drop in the data transfer rate, even when write instructions from a host device are given with commands having a short write data length. If the write end address of one of a plurality of ATA commands issued by a host device 2 is consecutive with the write start address of the next ATA command, a command analysis unit 11 has data writing to an SD card 1 by the consecutive commands performed in a single process. As a result, overheads when writing data to SD cards are incurred only once, allowing the transfer rate to be improved.

Abstract: A system and method is provided for communicating with at least one network device via a network bus comprising a bus controller and a host computer. The bus controller executes a series of instructions, which can be transferred to the bus controller from the host computer. The instructions are executed in a manner independent of the host computer so as to reduce the workload of the host computer. Since the bus controller can execute the series of instructions without further intervention of the host computer, the host computer can perform other operations concurrent with the execution of the series of instructions by the bus controller. In one embodiment, at least one of the instructions has an associated data field that is variable and can be altered by the host computer, such that the host computer can alter the instruction used by the bus controller.

Abstract: A method and system for transferring units of data between a computer memory and an external system in which a DMA controller stores and uses information from an I/O device interfacing with the external system to transfer data more efficiently.