Abstract: A conflict detection method for a disk drive controller is used to handle a conflict potentially occurring if the execution sequence of queued commands sent from a host to a controller is reordered to optimize disk drive transfers. The conflict detection method determines if there is an address range overlap between two queued commands. If an overlap exists, a conflict flag is set. The controller microprocessor utilizes this flag to restrict command reordering and prevent a conflict from producing erroneous data. Conflict detection and command reordering restriction are facilitated by a queued command RAM and a command FIFO. The queued command RAM stores command parameters indexed by command tag values. These parameters include command direction (read or write), LBA, block count, a valid flag and a conflict flag. The conflict detection method compares the address range of a new command with the address range of valid commands in the command RAM to determine range overlaps.

Abstract: In a SCI based multi-node system, the write purge command joins the new node that is requesting to write to the memory of the sharing list, while maintaining the connection between the memory and the sharing list. The new node then issues the purging command to each node in the sharing list, while still maintaining the connection of the sharing list to the memory. Next, the new node issues the collapsing command to separate the sharing list from the memory after the purging command has been issued to each node. A send request data packet is used to distribute the write purge command to the memory node.

Abstract: An improved method and computer to parse a data stream comprising a series of command strings is disclosed. The method provides superior performance in terms of balance between processor cycle usage, memory usage and portability across platforms.

Abstract: A direct memory access (DMA) controller is provided for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer.

Abstract: A system and method of increasing the efficiency of a data processing system by alternately streaming portions of a large block of data from a large memory area into two memory banks within a smaller memory area using consecutive DMA transactions. Each streaming DMA transaction is entered in a DMA transaction queue and once it becomes active, transfers a block of data, the same size as one of the two memory banks, into one of the memory banks, after which it becomes inactive and is re-entered in the queue. When the streaming DMA transaction becomes active again, it switches to a different memory bank address and continues in the large data block where it stopped last time it was active. The streaming DMA transaction continues to be circulated in the queue until a total number of transaction iterations is reached, at which point the streaming DMA transaction is complete and is removed from the queue.

Abstract: A computer system or computer system main memory is provided. The computer system includes a secondary memory and a buffer. The buffer is one having a faster access time than the secondary memory, and data placed within the buffer can be controlled by a control block configured with a control field and a byte count value of data bytes transferred during a DMA cycle, or a chain of DMA cycles. A counter may be used to increment the byte count within one or more control blocks during transfer of data bytes from secondary memory to the buffer. A requester is coupled to forward a read request that is serviced from the buffer if an address of the read request is included within an address incremented by the byte count. Both the control blocks and the buffer can be contained within a main memory local to the requester.

Abstract: A computer system, bus interface unit, and method is provided for noting a control block transfer at which an interrupt occurs. The control block is but one control block within a chain of control blocks necessary to effectuate a chain of DMA transfers. If the control block undergoes an interrupt, that control block must be noted and control information associated therewith placed within a register so that when the DMA transfers are resumed, that control block can be immediately pointed to rather than having to initiate the first control block of the chain up to and including the control block undergoing interrupt. By purposely programming interrupts within the tag field of select control blocks and maintaining a software tag register within system memory, a control block within an expanded number of control blocks within a chain can be kept track of and pointed to following an error-induced interrupt.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: A communication system includes a communication control section which may receive bus use requests of both of a DV camera/recorder (50) which becomes an output machine on a serial bus (60D) and a DV deck (40) which becomes an input machine on the serial bus (60D), may check whether or not the serial bus (60D) which were requested to be used is in use, may open the serial bus (60D) to the DV camera/recorder (50) and the DV deck (40) which issued the use requests, may protect a connection between the DV camera/recorder (50) and the DV deck (40), may open a serial bus (60A) to an IRD receiver (10) and a mini disc (20) which issued use requests and which may protect a connection between the IRD receiver (10) and the mini disc (20).

Abstract: The present invention relates to a method and circuit for prefetching direct memory access descriptors from memory of a computer system, and storing the prefetched direct memory access descriptors within a unified descriptor memory for subsequent access by direct memory access controllers. The descriptors are generated by a central processing unit of the computer system while executing software applications. The descriptors define data transfer operations between memory of the computer system and input/output devices via direct memory access controllers. The direct memory access controllers generate requests for descriptors. Upon generation of a request, the unified descriptor memory is checked to determine whether the requested descriptor is contained therein. If the requested descriptor is contained within the unified descriptor memory, the request descriptor is provided to the requesting direct memory access controller.

Abstract: A host bridge having a dataflow controller is provided. In a preferred embodiment, the host bridge contains a read command path which has a mechanism for requesting and receiving data from an upstream device. The host bridge also contains a write command path that has means for receiving data from a downstream device and for transmitting the received data to an upstream device. A target controller is used to receive the read and write commands from the downstream device and to steer the read command toward the read command path and the write command toward the write command path. A bus controller is also used to request control of an upstream bus before transmitting the request for data of the read command and transmitting the data of the write command.

Abstract: An information handling system which efficiently processes auxiliary functions such as graphics processing includes one or more processors, a high speed processor bus connecting the one or more processors, a memory controller for controlling memory and for controlling the auxiliary function processing, a memory system, and an I/O bus having one or more I/O controllers with I/O devices connected thereto.

Abstract: A command queuing engine in a target controller ASIC automatically detects sequential commands received from an initiator and generates a linked list of data transfer descriptors for the sequential commands. The data transfer descriptors are automatically processed by the command queuing engine to reduce command overhead from interrupt processing by a microprocessor in the target controller, thereby improving the performance of the target controller.

Abstract: A method and apparatus for dynamic chaining of DMA operations that includes a count to keep track of control blocks associated with such operations when appended to a current chain of control blocks. The count is checked by a DMA controller upon completing the data-transfer operation associated with each block or each control-block chain depending on the use of a wait bit. Memory used to hold control blocks may be preallocated with anticipated control blocks associated in a predefined linked list to avoid the need for subsequently updating existing control blocks when new blocks are appended to a chain.

Abstract: The present invention is a method and apparatus for re-recording audio events. Scattered audio events on a first track are determined based on a linked list. The scattered audio events are merged into a combined audio event on a second track. The combined audio event is copied on the second track to the first track.

Abstract: The present invention includes a method of transferring data when some of the data is masked. A mask table is provided to a storage device where it is duplicated and stored with the duplicate. The duplicate data is compared to the original data for a data protection function. A mask index counter and mask bit counter maintain provide values for specific data that are to be processed. The counters are programmable so that if a transfer error occurs, counter values for the next data after the previously transferred good data is calculated and loaded therein. The present invention also has the capability not to transfer the last requested sector if that sector is masked. The present invention evaluates whether a stop count value equals a stop threshold value when a sector is identified as being masked. The stop count value is incremented for each sector that is read from the first storage device, regardless of whether that sector is to be transferred or masked.

Abstract: An output method and apparatus, a storage medium, and an output control program product are provided for sequentially receiving a plurality of control information for setting an output environment based on externally supplied data, and controlling the setting of the output environment in accordance with the first received control information.

Abstract: A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices.

Abstract: The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.

Abstract: An apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device, such as a bus bridge.

Abstract: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete.

Abstract: In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.

Abstract: A data transfer apparatus is provided for transferring data with a DMA method between a plurality of disk apparatuses and a memory using a DMA command table. A processor generates the DMA command table composed of an array of the DMA commands which are each composed of an address (starting address) of the data area and a size of data to be transferred. A disk access unit transfers data between the disk apparatuses and the memory using the DMA command table. When it is judged that the disk apparatus currently transferring data has temporarily released the bus use right, the processor, concurrently in preparation for the resumption of the data transfer, updates the DMA command table by deleting DMA commands having been executed and adding new DMA commands. This eliminates or reduces the generation of the table update interrupt.

Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.

Abstract: A method and system for autonomously operation a PCI-serial bus interface device (20) in an autonomous mode includes directing circuitry (370) for directing an autonomous boot mode select signal to the data transfer device. Instructions configure registers (36, 38) associated with the data transfer device for autonomous operation of a data transfer device. The directing circuit (370) associates with the data packet transfer device for transferring data to at least one program control list (456) for operating said data packet transfer device in an autonomous mode.

Abstract: An input/output (I/O) buffer has a block-end detector which detects that an access has reached the last word in a block of the I/O buffer. If the block-end detector detects the last word of the block, then the block is invalidated. The I/O buffer also has a direct-memory-access-end detector which detects that an access has reached the last word in a direct-memory-access (DMA) transfer. If the DMA-end detector detects the last word of the DMA transfer, then the block is invalidated. The I/O buffer may also have a configuration memory which stores configuration information concerning whether a DMA controller accesses the input/output buffer instead of a storage. If the configuration information indicates that the DMA controller does not access the input/output buffer, then data from the storage are bypassed to the DMA controller.

Abstract: A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are efficiently timesharing a global memory storage area. The received data streams are each divided into fixed portions called spans. The invention is operable for sequencing the movement of the time-sliced spans between the processors, adjusting the scheduling of particular ones of the time-sliced spans as a function of either processor availability or maintenance of real-time transmission of the received real-time time-sliced data streams.

Abstract: A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor.

Abstract: A method and apparatus for fencing the execution of commands. A fence command and an executable command are received in succession. The executable command is enqueued in a first queue together with an indication that the executable command succeeded the fence command. A synchronization value is enqueued in a second queue. The executable command is then delayed from being dequeued from the first queue until the synchronization value is advanced to the head of the second queue.

Abstract: The present invention discloses a method for organizing audio events recorded on a storage medium to facilitate efficient storage and fast access. The method comprises the steps of: (1) maintaining attributes of the audio events in a list; (2) determining if a subset of the audio events causes a medium fragmentation based on the attributes, the subset including originally sequential audio segments; (3) if the medium fragmentation occurs, copying the subset of said audio events from the storage medium into a buffer memory of a predetermined size; and (4) copying the buffer memory onto the storage medium.

Abstract: A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address.

Abstract: A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain commands which are fully programmable at the user level. The processor itself is programmed at the register level to assure the fastest data rate possible (32 bit access) across the VMEbus. The processor driver is invisible to the user.

Abstract: A SCSI-2-and-DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI-2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to down load a very compact control program and then transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

Abstract: A method for queuing hardware control blocks for a system including a host microprocessor and a plurality of devices that each includes an onboard sequencer is based on a single host endless new hardware control block queue in a host memory that is managed such that the host endless new hardware control block queue never goes empty. Each device, that is coupled to the host microprocessor by an I/O bus, also has a device endless new hardware control block queue in a common hardware control block array. These device endless new hardware control block queues are managed such that the queues never are empty. A single device on the bus fetches hardware control blocks from the host endless hardware control block queue and loads the hardware control blocks in the common hardware control block array. The other devices on the I/O bus do not participate in the transfer of hardware control blocks to the common hardware control block array.

Abstract: A method for queuing TCBs for a system including a microprocessor and at least one host adapter device is based on an endless new TCB queue, that is managed such that the endless new TCB queue never goes empty. A device driver executing on the microprocessor manages an endless new TCB queue for each host adapter device in the system. The TCBs in the endless queue include a next TCB address field and a host adapter (HA) TCB array site field. The next TCB address field is used to couple TCB sites in a host memory into a linked list. The destination of a TCB in a host adapter (HA) TCB array is specified in the HA TCB array site field. The endless new TCB queue has head and tail pointer delimiters. The head pointer is accessible only by the host adapter device, and the tail pointer is accessible only by the device driver. The device driver appends a new TCB to the endless new TCB queue using the tail pointer to identify the next TCB storage site.

Abstract: A packet control list (456) controls the transfer of data packets between at least one source location (452) and at least one destination location (460) each associated with a data packet transfer device (20). Packet control list (456) associates a plurality of data packet transfer control instructions (454) in a sequential list (466) including a plurality of logical functions (472) for controlling logical operations relating to the transfer of data packets from at least one source location (452) to at least one destination location (460). Instructions (486) control the operation of data packet transfer device (20) according to instructions (486).

Abstract: Higher speed data transactions between a host computer's system memory and a plurality of slow peripheral devices are accomplished by providing distributed DMA functions along with distributed pre-fetch buffers. The first I/O device accesses the host bus via a first DMA channel and a first pre-fetch buffer, the second I/O device accesses the host bus via a second DMA channel and a second pre-fetch buffer, and the third I/O device accesses the host bus via a third DMA channel and a third pre-fetch buffer. In a first DMA transaction, the first pre-fetch buffer is filled with data being transferred between the first I/O device and the host system memory. While the data are transferred between the pre-fetch buffer and either the first I/O device or the system memory, the second pre-fetch buffer is being filled pursuant to a second DMA transaction between the second I/O device and the system memory.

Abstract: An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The command blocks are transferred from the host processing side to the local processing side by storing the host address of the command block in a local side register set. Upon storing the host address a transfer signal is given to a command block transfer controller to start a command block transfer without the local processor unit intervention.

Abstract: A data transfer apparatus for DMA-transferring stream data between a memory and each of n ports.