Abstract: The present subject matter relates to a method comprising acquiring a master role by a processing unit of a multi-processor system, executing by the processing unit a master function part of a set of tasks: comprising searching an available processing unit of the multi-processor system; wherein in case an available processing unit is found, controlling the found processing unit to perform a slave function part of the set of tasks, and in case no available processing unit is found, executing by the processing unit the slave function part of the set of tasks, wherein the master function comprises a master to slave switching function for releasing the master role and the slave function composes a slave to master switching function for acquiring the master role.

Abstract: Techniques are described herein that are capable of reducing interrupts using buffering for data processing. In a first example, information is received at an operating system from an application. The information indicates multiple buffers, including a triggering buffer to trigger an interrupt from hardware. Portions of the data are stored in the respective buffers. A schedule for processing the buffers is provided to the hardware. The schedule indicates that the interrupt is to be delayed until the triggering buffer is processed by the hardware. In a second example, a network interface controller is configured to provide one interrupt to the operating system for each of multiple subsets of network packets that is processed by the network interface controller. Each subset includes a number of the network packets that is greater than one. The network packets are associated with a common network socket.

Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

Abstract: An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.

Abstract: In a computing system, an application thread is executed on a hardware thread. Based on a configuration of the computing system, a first threshold is determined comprising a threshold percentage of execution time spent servicing a set of interrupts to the application thread relative to a total execution time for the hardware thread. For the hardware thread, a length of a first time period spent servicing an interrupt in the set of interrupts and a length of a second time period spent executing the application thread are measured. A cumulative percentage of execution time spent in the first time period relative to execution time spent in the first time period and the second time period is calculated. Responsive to the cumulative percentage being above the threshold percentage, interrupt servicing on the hardware thread is disabled.

Abstract: One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.

Abstract: A method is provided for performing a secure communication between a real-time operating system and a general purpose operating system. The systems are provided in a single computing apparatus and separated by a virtual machine monitor. The systems include a first and second open platform communications interfaces, respectively. The method includes: receiving a request with the virtual machine monitor from a user via the first or second open platform communications interface to access data of the real-time operating system from the general purpose operating system or to access data of the general purpose operating system from the real-time operating system; establishing a secure communication path via a software bus between the first and the second open platform communications interfaces according to the request; and performing a secure communication between the real-time operating system and the general purpose operating system via. the established secure communication path for accessing the data.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes initiating a read request associated with an address from an input/output device, redirecting the read request to a hierarchical memory component, generating, by the hierarchical memory component, an interrupt message to send to a hypervisor, gathering, at the hypervisor, address register access information from the hierarchical memory component, and determining a physical location of data associated with the read request.

Abstract: An operating system, when having incorporated data, with a certificate attached, for limiting a function of copying a screen, limits the function of the operating system and when receiving a request for a result of an inspection to determine whether the incorporated data is valid, sends out the result of the inspection in response to the request. An application program makes a request to the operating system for the result of the inspection of the data incorporated in the operating system at startup or return from a background processing. When an inspection result sent from the operating system indicates that the data is invalid, the application program forbids a display control means to display a given screen and instructs the operating system to incorporate a valid data therein. When the inspection result indicates that the data is valid, the application program makes the display means display the given screen.

Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus and a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using a mapping table comprised by the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

Abstract: Status indicators are provided. An operation is performed in a current operating mode of the processor, in which the current operating mode is dynamically selectable from a plurality of supported operating modes. A first set of status indicators is set, based on performing the operation in the current operating mode. A second set of status indicators is set, based on performing the operation in the current operating mode, but the setting is to reflect at least one status condition for another operating mode supported by the processor. At least one of the first set of status indicators or the second set of status indicators is used in further processing.

Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.

Abstract: The present invention discloses a method and an apparatus for executing a non-maskable interrupt. The method includes: obtaining a secure interrupt request in a non-secure mode, and interrupting an operation of an operating system OS, where the secure interrupt request cannot be masked; entering a secure mode by using the secure interrupt request, and saving, in the secure mode, an interrupt context of an OS status when the operation of the OS is interrupted; returning to the non-secure mode to execute user-defined processing; after the user-defined processing is completed, entering the secure mode again, and resuming the OS status in the secure mode according to the interrupt context; and returning to the non-secure mode again, and continuing to execute an operation of the OS. The method and the apparatus for executing a non-maskable interrupt in embodiments of the present invention can easily implement an NMI mechanism without depending on hardware.

Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

Abstract: A method of executing an instruction of a core includes calling a first function; calling a second function in the first function; and updating a path identifier including path information of called functions based on a second function return address corresponding to where the second function ends and returns to.

Abstract: This servo system is a servo system in which a host apparatus and a plurality of servo amplifiers transmit and receive a communication signal. Each of the servo amplifiers includes a servo computation unit configured to perform servo computation processing, a communication unit configured to transmit and receive the communication signal, a storage unit configured to save servo computation information in the servo computation processing as history data, and a trigger information processor configured to set, in advance, a save stop condition for stopping saving the history data, determine, for each servo computation period, whether the save stop condition is matched, and notify, when the save stop condition is matched, the communication unit of a determination result indicating detection of a trigger as a trigger detection flag.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing application program interface calls.

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract: A microcontroller with a built-in self-healing function. A programmable memory stores a normal control routine. A processing unit is arranged to execute the normal control routine in order to provide output data on the output line. A danger signal input line which is connected to a logic unit and dedicated to communicating a danger signal to the logic unit. Processor and logic unit state lines are provided between the processing unit and the logic unit for communicating processor state data from the processing unit to the logic unit and communicating logic unit state data from the logic unit to the processing unit. An interrupt line between the logic unit and the processing unit is dedicated to communicating an interrupt signal from the logic unit to the processing unit.

Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.

Abstract: Optimizing network driver performance and power consumption in multi-core processor-based systems is disclosed. In this regard, a multi-core processor-based system provides multiple processor cores comprising one or more power-optimized processor cores and one or more performance-optimized processor cores, and a network device configured to assign network streams to a plurality of interrupts. A network driver calculates a current throughput level of the network device, and determines whether a throughput mode of the network driver should be modified to a high-throughput mode. If so, the network driver assigns each interrupt to one of the performance-optimized processor cores, and disables system reassignment of interrupts among the processor cores.

Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. Other embodiments are also disclosed and claimed.

Abstract: Register restoration invalidation based on a context switch. A context switch from one executing entity to another executing entity is detected. Based on detecting the context switch, an entry of a snapshot stack to be invalidated is selected. The entry of the snapshot stack provides an indication of a snapshot. The snapshot includes an assignment of one or more physical registers to one or more architected registers. The entry of the snapshot stack selected for invalidation is invalidated.

Abstract: An embodiment of a semiconductor package apparatus may include technology to process a single stream of video frames which includes frame information from two or more video sources, and process a current frame based on information from a prior frame in the single stream of video frames which precedes the current frame by a number of frames based on a number of video sources represented in the single stream of video frames. Other embodiments are disclosed and claimed.

Abstract: In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

Abstract: A device is provide including: a storage device comprising a memory configured to store configuration data used for test booting for a process of testing the device, before the test booting; and a controller configured to perform the test booting using the stored configuration data when receiving a start signal of the test booting, to control the process of testing the device to be performed after the test booting, and to delete the configuration data stored in the storage device when a completion signal of the process of testing the device is received.

Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Abstract: A computer, on which operating systems run, the computer comprising a virtualization function module configured to manage virtual computers. A operating system is configured to run on each of the virtual computers. The virtualization function module includes an interrupt controller. The interrupt controller is configured to hold vector information for managing host-side interrupt vectors, and interrupt vector allocation information for managing allocation of the host-side interrupt vectors to the guest-side interrupt vectors that are set by the operating systems. The virtualization function module is configured to analyze a state of allocation of the host-side interrupt vectors to the guest-side interrupt vectors, and change the allocation of the host-side interrupt vectors to the guest-side interrupt vectors based on a result of the analysis.

Abstract: A method for real-time data acquisition in a processing component using chained direct memory access (DMA) channels that includes receiving a DMA event signal in a DMA controller of the processing component, and executing, responsive to the DMA event signal, a plurality of DMAs to read at least one data sample from a peripheral device, in which a last DMA in the plurality of DMAs performs a write operation to acknowledge completion of the DMA event.

Abstract: An improved high-voltage AC power supply energizes and regulates plasma actuators for aerodynamic flow control. Such plasma actuators are used, for example, on aerodynamic surfaces, wind turbine blades, and the like for vehicle control, drag or noise reduction, or efficient power generation. Various embodiments of the power supply are small, compact, lightweight, portable, modular, self-contained in its own housing, easily replaceable and swappable, autonomous, self-cooling, and/or gangable in series or parallel to provide any desired control authority over the selected surface. In some embodiments, the parameters for the plasma electronics can be manually selected and pre-programmed for a specific application, while in preferred embodiments, the plasma electronics can automatically identify the appropriate parameters and self-tune the performance of the plasma actuators.

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.

Abstract: A system, methods, and apparatus for using hypervisor trapping for protection against interrupts in virtual machine functions are disclosed. A system includes memory, one or more physical processors, a virtual machine executing on the one or more physical processors, and a hypervisor executing on the one or more physical processors. The hypervisor reads an interrupt data structure on the virtual machine. The hypervisor determines whether the interrupt data structure points to an alternate page view. Responsive to determining that the interrupt data structure points to an alternate page view, the hypervisor disables a virtual machine function.

Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Abstract: A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.

Abstract: Techniques for runtime patching of an OS without stopping execution of the OS are presented. When a patch function is needed, it is loaded into the OS code. Threads of the OS that are in kernel mode have a flag set and a jump is inserted at a location of an old function. When the old function is accessed, the jump uses a trampoline to check the flag, if the flag is set, processing returns to the old function; otherwise processing jumps to a given location of the patch. Flags are unset when exiting or entering the kernel mode.

Abstract: A system and method are provided for data collection and analysis of information related to applications. Specifically, the developer of the application may install analytic software, which may be embodied as a software development kit (SDK), on an integrated development environment (“IDE”) associated with the developer, wherein the analytic software may be installed with a wizard-like interface having a series of easy to follow instructions. Once installed, the application, with the analytic software incorporated therein, may be provided and installed on a plurality of end user devices. Thereafter, the analytic software may work in conjunction with analytic processing logic to assist the developer in obtaining pertinent information related to bugs associated with the application that is being executed on an end user device.

Abstract: A method for protecting computer software code is disclosed. In the embodiment, the method involves receiving instructions corresponding to computer software code for an application, the instructions including a first section of instructions to protect that is indicated by a first indicator and a second section of the instructions to protect that is indicated by a second indicator, rewriting the first section of instructions into a first section of virtual instructions, and rewriting the second section of instructions into a second section of virtual instructions, wherein the first section of instructions includes a first virtual instruction that corresponds to a first handler and the second section of virtual instructions includes a second virtual instruction that corresponds to a second handler, the first handler having different properties than the second handler.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Disclosed herein is a digital rights management system that includes a storage module that stores a usage right for digital content in a tamper-resistant portion of a memory. The system also includes a flag status module that generates a flag corresponding with a transfer status of the usage right, sets the flag to one of a plurality of transfer statuses, and stores the flag in the tamper-resistant portion of the memory. The transfer statuses include a status indicating a request for the usage right was generated by a device with a usage right recovery mechanism.

Abstract: One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ). Specifically, memory for context data is pre-allocated when a new TMDQ is created. A new TMDQ may be integrated with an existing TMDQ, where computational tasks within that TMDQ include task from each of the original TMDQs. A scheduling operation is executed on completion of each computational task in order to preserve sequential execution of tasks without the use of atomic locking operations. One advantage of the disclosed technique is that GPUs are enabled to queue computational tasks within TMDQs, and also create an arbitrary number of new TMDQs to any arbitrary nesting level, without intervention by the CPU. Processing efficiency is enhanced where the GPU does not wait while the CPU creates and queues tasks.

Abstract: A virtual machine manager (e.g., hypervisor) implements a virtual secure mode that makes multiple different virtual trust levels available to virtual processors of a virtual machine. Different memory access protections (such as the ability to read, write, and/or execute memory) can be associated with different portions of memory (e.g., memory pages) for each virtual trust level. The virtual trust levels are organized as a hierarchy with a higher level virtual trust level being more privileged than a lower virtual trust level, and programs running in the higher virtual trust level being able to change memory access protections of a lower virtual trust level. The number of virtual trust levels can vary, and can vary for different virtual machines as well as for different virtual processors in the same virtual machine.

Abstract: A method for managing I/O event notifications in a data processing system, the data processing system comprising a plurality of applications and an operating system having a kernel and an I/O event notification mechanism operable to maintain a plurality of I/O event notification objects each handling a set of file descriptors associated with one or more I/O resources, the method comprising: for each of a plurality of application-level configuration calls: intercepting at a user-level interface a configuration call from an application to the I/O event notification mechanism for configuring an I/O event notification object; and storing a set of parameters of the configuration call at a data structure, each set of parameters representing an operation on the set of file descriptors handled by the I/O event notification object; and subsequently, on a predetermined criterion being met: the user-level interface causing the plurality of configuration calls to be effected by means of a first system call to the kernel.

Abstract: A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter.

Abstract: Aspects relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.

Abstract: An audio accelerator includes a decoder to decode first and second sets of data blocks, a processor to process the first and second sets of decoded data blocks, a storage area to store the first and second sets of processed data blocks, and a controller to generate interrupt signals for controlling operation of the decoder. The controller may control a rate at which data blocks are to be decoded by the decoder to reduce a time gap between outputting adjacent ones of the data blocks from the first and second sets in the storage area.

Abstract: One embodiment of the present invention is a method of interposing operations in a computational system that includes a virtualization system executable on an underlying hardware processor that natively supports one or more instructions that transition between host and guest execution modes.

Abstract: Techniques for runtime patching of an OS without stopping execution of the OS are presented. When a patch function is needed, it is loaded into the OS code. Threads of the OS that are in kernel mode have a flag set and a jump is inserted at a location of an old function. When the old function is accessed, the jump uses a trampoline to check the flag, if the flag is set, processing returns to the old function; otherwise processing jumps to a given location of the patch. Flags are unset when exiting or entering the kernel mode.