Multimode Interrupt Processing Patents (Class 710/261)
  • Patent number: 10078605
    Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: September 18, 2018
    Assignee: Cavium, Inc.
    Inventors: Vishal Anand, Harish Krishnamoorthy, Guy Townsend Hutchison, Gerald Schmidt
  • Patent number: 10067892
    Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 4, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Keith Curtis, Ashish Senapati, Anthony Garcia, Vijay Sarvepalli, Prashanth Pulipaka, Kevin Kilzer, David Forst, Rob Kennedy, Primo Castro, Aaron Barton
  • Patent number: 10042790
    Abstract: A computer, on which operating systems run, the computer comprising a virtualization function module configured to manage virtual computers. A operating system is configured to run on each of the virtual computers. The virtualization function module includes an interrupt controller. The interrupt controller is configured to hold vector information for managing host-side interrupt vectors, and interrupt vector allocation information for managing allocation of the host-side interrupt vectors to the guest-side interrupt vectors that are set by the operating systems. The virtualization function module is configured to analyze a state of allocation of the host-side interrupt vectors to the guest-side interrupt vectors, and change the allocation of the host-side interrupt vectors to the guest-side interrupt vectors based on a result of the analysis.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 7, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Kazuaki Okada, Takao Totsuka
  • Patent number: 10019397
    Abstract: A method for real-time data acquisition in a processing component using chained direct memory access (DMA) channels that includes receiving a DMA event signal in a DMA controller of the processing component, and executing, responsive to the DMA event signal, a plurality of DMAs to read at least one data sample from a peripheral device, in which a last DMA in the plurality of DMAs performs a write operation to acknowledge completion of the DMA event.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreeram Subramanian
  • Patent number: 10011344
    Abstract: An improved high-voltage AC power supply energizes and regulates plasma actuators for aerodynamic flow control. Such plasma actuators are used, for example, on aerodynamic surfaces, wind turbine blades, and the like for vehicle control, drag or noise reduction, or efficient power generation. Various embodiments of the power supply are small, compact, lightweight, portable, modular, self-contained in its own housing, easily replaceable and swappable, autonomous, self-cooling, and/or gangable in series or parallel to provide any desired control authority over the selected surface. In some embodiments, the parameters for the plasma electronics can be manually selected and pre-programmed for a specific application, while in preferred embodiments, the plasma electronics can automatically identify the appropriate parameters and self-tune the performance of the plasma actuators.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: July 3, 2018
    Assignee: Orbital Research Inc.
    Inventors: Srikanth Vasudevan, Frederick J. Lisy, Mike Ward
  • Patent number: 9965413
    Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 8, 2018
    Assignee: Google LLC
    Inventors: Benjamin C. Serebrin, Michael R. Marty, Paul Jack Turner
  • Patent number: 9875128
    Abstract: A system, methods, and apparatus for using hypervisor trapping for protection against interrupts in virtual machine functions are disclosed. A system includes memory, one or more physical processors, a virtual machine executing on the one or more physical processors, and a hypervisor executing on the one or more physical processors. The hypervisor reads an interrupt data structure on the virtual machine. The hypervisor determines whether the interrupt data structure points to an alternate page view. Responsive to determining that the interrupt data structure points to an alternate page view, the hypervisor disables a virtual machine function.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: January 23, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 9870230
    Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 16, 2018
    Assignee: ARM Limited
    Inventors: Simon Andrew Ford, Stephen John Hill
  • Patent number: 9811467
    Abstract: A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: November 7, 2017
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Richard Eugene Kessler, Daniel Edward Dever, Nitin Dhiroobhai Godiwala
  • Patent number: 9652221
    Abstract: Techniques for runtime patching of an OS without stopping execution of the OS are presented. When a patch function is needed, it is loaded into the OS code. Threads of the OS that are in kernel mode have a flag set and a jump is inserted at a location of an old function. When the old function is accessed, the jump uses a trampoline to check the flag, if the flag is set, processing returns to the old function; otherwise processing jumps to a given location of the patch. Flags are unset when exiting or entering the kernel mode.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Micro Focus Software Inc.
    Inventors: Vojtech Pavlik, Jiri Kosina
  • Patent number: 9606904
    Abstract: A system and method are provided for data collection and analysis of information related to applications. Specifically, the developer of the application may install analytic software, which may be embodied as a software development kit (SDK), on an integrated development environment (“IDE”) associated with the developer, wherein the analytic software may be installed with a wizard-like interface having a series of easy to follow instructions. Once installed, the application, with the analytic software incorporated therein, may be provided and installed on a plurality of end user devices. Thereafter, the analytic software may work in conjunction with analytic processing logic to assist the developer in obtaining pertinent information related to bugs associated with the application that is being executed on an end user device.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: March 28, 2017
    Assignee: Crashlytics, Inc.
    Inventors: Wayne Chang, Jeffrey H. Seibert, Jr.
  • Patent number: 9501301
    Abstract: A method for protecting computer software code is disclosed. In the embodiment, the method involves receiving instructions corresponding to computer software code for an application, the instructions including a first section of instructions to protect that is indicated by a first indicator and a second section of the instructions to protect that is indicated by a second indicator, rewriting the first section of instructions into a first section of virtual instructions, and rewriting the second section of instructions into a second section of virtual instructions, wherein the first section of instructions includes a first virtual instruction that corresponds to a first handler and the second section of virtual instructions includes a second virtual instruction that corresponds to a second handler, the first handler having different properties than the second handler.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: November 22, 2016
    Assignee: NXP B.V.
    Inventor: Philippe Teuwen
  • Patent number: 9465760
    Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 11, 2016
    Assignee: Futurewei Technologies, Inc.
    Inventors: Norbert EGI, Robert Lasater, Thomas Boyle, John Peters, Guangyu Shi
  • Patent number: 9460027
    Abstract: Disclosed herein is a digital rights management system that includes a storage module that stores a usage right for digital content in a tamper-resistant portion of a memory. The system also includes a flag status module that generates a flag corresponding with a transfer status of the usage right, sets the flag to one of a plurality of transfer statuses, and stores the flag in the tamper-resistant portion of the memory. The transfer statuses include a status indicating a request for the usage right was generated by a device with a usage right recovery mechanism.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: October 4, 2016
    Assignee: HGST NETHERLANDS, B.V.
    Inventors: Dai Yun, Toshiyuki Masue, Tatsuya Hirai
  • Patent number: 9436504
    Abstract: One embodiment of the present disclosure sets forth an enhanced way for GPUs to queue new computational tasks into a task metadata descriptor queue (TMDQ). Specifically, memory for context data is pre-allocated when a new TMDQ is created. A new TMDQ may be integrated with an existing TMDQ, where computational tasks within that TMDQ include task from each of the original TMDQs. A scheduling operation is executed on completion of each computational task in order to preserve sequential execution of tasks without the use of atomic locking operations. One advantage of the disclosed technique is that GPUs are enabled to queue computational tasks within TMDQs, and also create an arbitrary number of new TMDQs to any arbitrary nesting level, without intervention by the CPU. Processing efficiency is enhanced where the GPU does not wait while the CPU creates and queues tasks.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: September 6, 2016
    Assignee: NVIDIA Corporation
    Inventor: Luke Durant
  • Patent number: 9430642
    Abstract: A virtual machine manager (e.g., hypervisor) implements a virtual secure mode that makes multiple different virtual trust levels available to virtual processors of a virtual machine. Different memory access protections (such as the ability to read, write, and/or execute memory) can be associated with different portions of memory (e.g., memory pages) for each virtual trust level. The virtual trust levels are organized as a hierarchy with a higher level virtual trust level being more privileged than a lower virtual trust level, and programs running in the higher virtual trust level being able to change memory access protections of a lower virtual trust level. The number of virtual trust levels can vary, and can vary for different virtual machines as well as for different virtual processors in the same virtual machine.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: August 30, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David A. Hepkin, Arun U. Kishan
  • Patent number: 9384071
    Abstract: A method for managing I/O event notifications in a data processing system, the data processing system comprising a plurality of applications and an operating system having a kernel and an I/O event notification mechanism operable to maintain a plurality of I/O event notification objects each handling a set of file descriptors associated with one or more I/O resources, the method comprising: for each of a plurality of application-level configuration calls: intercepting at a user-level interface a configuration call from an application to the I/O event notification mechanism for configuring an I/O event notification object; and storing a set of parameters of the configuration call at a data structure, each set of parameters representing an operation on the set of file descriptors handled by the I/O event notification object; and subsequently, on a predetermined criterion being met: the user-level interface causing the plurality of configuration calls to be effected by means of a first system call to the kernel.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 5, 2016
    Assignee: SOLARFLARE COMMUNICATIONS, INC.
    Inventors: Steven L. Pope, David J. Riddoch
  • Patent number: 9304955
    Abstract: A method for identifying and reporting interrupt behavior includes incrementing a counter when an interrupt signal is a designated type and is not received from an approved peripheral device, and performing a corrective action when the counter reaches a threshold value. In some embodiments, the designated type of the interrupt signal comprises a System Management Interrupt (SMI), which has the capability of halting operations at all processors within a system to execute associated instructions within a protected circumstance, resuming normal operations for each of the plurality of processors when the corrective action has been completed. In another embodiment, the corrective action includes creating a report identifying, within the same protected circumstance, the interrupt signal as an SMI. In some embodiments, the method performs a different corrective action when an interrupt signal is a designated type and is received from an approved peripheral device and decrements a counter.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 5, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Andrew G. Kegel
  • Patent number: 9280448
    Abstract: Aspects relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Marcel Mitran, Chung-Lung K. Shum, Timothy J. Slegel, Brian L. Smith, Kevin A. Stoodley
  • Patent number: 9236054
    Abstract: An audio accelerator includes a decoder to decode first and second sets of data blocks, a processor to process the first and second sets of decoded data blocks, a storage area to store the first and second sets of processed data blocks, and a controller to generate interrupt signals for controlling operation of the decoder. The controller may control a rate at which data blocks are to be decoded by the decoder to reduce a time gap between outputting adjacent ones of the data blocks from the first and second sets in the storage area.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Xiaocheng Zhou, Shoumeng Yan
  • Patent number: 9195487
    Abstract: One embodiment of the present invention is a method of interposing operations in a computational system that includes a virtualization system executable on an underlying hardware processor that natively supports one or more instructions that transition between host and guest execution modes.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: November 24, 2015
    Assignee: VMware, Inc.
    Inventor: Keith Adams
  • Patent number: 9170803
    Abstract: Techniques for runtime patching of an OS without stopping execution of the OS are presented. When a patch function is needed, it is loaded into the OS code. Threads of the OS that are in kernel mode have a flag set and a jump is inserted at a location of an old function. When the old function is accessed, the jump uses a trampoline to check the flag, if the flag is set, processing returns to the old function; otherwise processing jumps to a given location of the patch. Flags are unset when exiting or entering the kernel mode.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 27, 2015
    Assignee: Novell, Inc.
    Inventors: Vojtech Pavlik, Jirí Kosina
  • Patent number: 9160531
    Abstract: According to one embodiment, encrypted secret identification information (E-SecretID) and the key management information (FKB) are read from a memory device. Encrypted management key (E-FKey) is obtained using the key management information (FKB) and index information (k). The index information (k) and the encrypted management key (E-FKey) are transmitted to the semiconductor memory device. An index key (INK) is generated using the first key information (NKey) and the received index information (k). The encrypted management key (E-FKey) is decrypted using the index key (INK) to obtain management key (FKey), which is transmitted to the host device.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: October 13, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taku Kato, Tatsuyuki Matsushita, Yuji Nagai
  • Patent number: 9158660
    Abstract: An aspect includes enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. The instruction is executed based on determining, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Marcel Mitran, Chung-Lung K. Shum, Timothy J. Slegel, Brian L. Smith, Kevin A. Stoodley
  • Patent number: 9104418
    Abstract: A device reduces its energy consumption using a relatively lower frequency and lower power secondary oscillator to maintain timing information when a higher frequency and higher power primary oscillator is inactivated. The secondary oscillator maintains timing information at a higher resolution than the period of the oscillator, so as to conserve synchronization when the higher frequency, higher power primary oscillator is inactivated. In some embodiments, a microsequencer is programmably configured to control an integrated radio receiver and transmitter using less power than an associated microprocessor would use to perform the same functions. In other embodiments, flexible event timing facilitates the merging of wake-up events to reduce the energy consumed by wake-up operations in the device.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 11, 2015
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Brett Warneke, Maxim Moiseev
  • Patent number: 9103112
    Abstract: A mounting adapter for attaching an object to a mounting surface such as a flat roof includes a planar anchor plate having first apertures and second apertures extending therethrough. The first apertures receive an elongated fastener having a length sufficient to fasten the anchor plate over and to a support structure positioned beneath the mounting surface. A cover plate includes third apertures aligned with the second apertures and at least one fourth aperture. The cover plate extends over the first apertures and a second fastener extends through each third aperture and engages with a corresponding second aperture to secure the cover plate over the anchor plate. At least one third fastener interfaces with the at least one fourth aperture for attaching the object to the adapter such that load forces from the object are transferred directly to the support structure beneath the mounting surface through each elongated fastener.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 11, 2015
    Inventor: Peter A. Corsi
  • Patent number: 9069628
    Abstract: The techniques herein provide for “time-shifting” of intercepted system calls to enable a one-to-many (1:n) or a many-to-one (n:1) mapping of intercepted-to-real system calls. Any action that needs to be applied on the logical boundaries of the data (instead of the physical boundaries) presented upon system call interception spools (buffers) the data before taking the action and then unspools the result when finished. The action may be quite varied, e.g., examining the data, redacting the data, changing the data, restricting the data, processing the data, and updating the data, among others. The technique may be implemented in a database access control system.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Richard Ory Jerrell, Ury Segal, Galia Diamant
  • Patent number: 9043521
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Patent number: 9037768
    Abstract: Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: May 19, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hubert E. Brinkmann, Paul V. Brownell, David L. Matthews, Dwight D. Riley
  • Patent number: 9021172
    Abstract: A data processing apparatus has performance monitoring circuitry for generating performance monitoring data. The performance monitoring circuitry includes a first event counter for counting occurrences of a first event and a second event counter for counting occurrences of a second event. A performance monitoring interrupt signal is indicated if, when the number of first events counted by the first event counter reaches a first threshold value, the number of second events by the second event counter meets an interrupt triggering condition.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 28, 2015
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Christopher Daniel Emmons
  • Patent number: 9009377
    Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventors: Erik P Machnicki, Deniz Balkan, Manu Gulati
  • Patent number: 8997099
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20150067215
    Abstract: A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 5, 2015
    Inventors: G. Glenn Henry, Terry Parks
  • Publication number: 20150067214
    Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.
    Type: Application
    Filed: May 19, 2014
    Publication date: March 5, 2015
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean, Stephan Gaskins
  • Publication number: 20150067216
    Abstract: A memory controller (10) for a plurality of banks of memory (55a-55c) is disclosed. The memory controller (10) includes an interface (20) connectable to a bus (60) to communicate with a processor (70). The memory controller (10) redundantly maps the plurality of banks of memory (55a-55c) to a memory space (50) and includes a plurality of memory operators, each of the plurality of memory operators being executable by the memory controller for performing a different function on data in the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c). In response to receipt at the interface (20) of a request from the processor (70) for one of said memory operators, the memory controller (10) is configured to execute, independently of the processor (70), the respective memory operator on the memory space (50) and/or one or more of the plurality of banks of memory (55a-55c).
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventor: Nicholas Jarmany
  • Patent number: 8966149
    Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Bruce Fleming, Arvind Mandhani
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Publication number: 20140372651
    Abstract: According to an embodiment, an information processing apparatus includes a banked register determiner and a saving register determiner. The banked register determiner is configured to hold register information indicating which of a banked register and a non-banked register a register which is used by the operating system is, receive an acquisition instruction for the non-banked or banked register and the information about the mode of the operating system, and return a list of the non-banked or banked registers. The saving register determiner is configured to acquire the mode in which the operating system is capable of operating, determine that saving of the banked register for the mode is necessary when another operating system is capable of operating in the mode, acquire a list of the banked registers, and acquire a list of the non-banked registers from the banked register determiner.
    Type: Application
    Filed: March 5, 2014
    Publication date: December 18, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun KANAI, Hiroshi Isozaki
  • Publication number: 20140372650
    Abstract: Systems and methods for generating interruptions are provided. A method for generating interruptions, comprises generating a message for one or more recipients, detecting that a computing device is being used for a presentation, concluding, using a processor, that the one or more recipients are in an audience for the presentation, and after concluding that the one or more recipients are in the audience, interrupting the presentation with the message.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 18, 2014
    Inventors: Sasha P. Caskey, Robert G. Farrell, Dimitri Kanevsky, Tara N. Sainath
  • Patent number: 8898361
    Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventor: Sourin Sarkar
  • Patent number: 8861434
    Abstract: A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: October 14, 2014
    Assignee: Alcatel Lucent
    Inventors: Mohammad R. Khawer, Mugur Abulius
  • Publication number: 20140289437
    Abstract: In one example in accordance with aspects of the present disclosure, an expander is provided. The expander comprises a workload scheduling module to cause the expander to enter a first mode of operation where the expander processes interrupts, and further to enter a second mode of operation where the expander processes interrupts for up to a predetermined time period before responding to at least one of Serial Management Protocol (SMP) commands and Serial SCSI Protocol (SSP) commands with a retry message.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 25, 2014
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Michael G. Myrah, Balaji Natrajan, Rodrido Stoll Martins Machado
  • Publication number: 20140258580
    Abstract: A motor control apparatus includes: a driving control unit that performs driving control of a motor in accordance with a drive command; an interrupt control unit that starts and executes interrupt processing for performing the driving control at an interrupt cycle; a first processing unit that executes same first processing every time the interrupt processing starts; and a second processing unit that selects and executes a different piece of processing from second processing every time the interrupt processing starts. The interrupt control unit executes at least one piece of the first processing before executing the second processing in the interrupt processing.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 11, 2014
    Applicant: RICOH COMPANY, LIMITED
    Inventor: Haruyuki SUZUKI
  • Patent number: 8813077
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Steven Bennett, Andrew Anderson, Gilbert Neiger, Scott Rodgers, Richard Uhlig, Lawrence Smith, III, Barry Huntley
  • Publication number: 20140223059
    Abstract: A method and circuit for a data processing system (12) provide a virtualized programmable interrupt control system (70) which processes interrupt event reports from interrupt sources (e.g., 14, 40) which generate write transactions to an address for an interrupt event register (80) which is authenticated and then interpreted based on the current state of the targeted interrupt to generate the next state using an interpretation table (306) and predetermined configuration/state bits (310-314).
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Inventor: Bryan D. Marietta
  • Publication number: 20140223060
    Abstract: Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: RED HAT ISRAEL, LTD.
    Inventors: Michael Tsirkin, Avi Kivity
  • Publication number: 20140207988
    Abstract: In accordance with the present disclosure, a system and method are herein disclosed for providing secure SMI memory services, including the protection of SMM memory from surreptitious attacks by, for example, rootkits. Information handling systems are susceptible to attacks, especially attacks on SMM memory. In one example, an SMI handler corresponding to the SMI Driver associated with an SMI interrupt performs validation of a password. An SSMS driver allocates memory for the SMI handler to use with the validation process and also performs a secure erase of allocated memory blocks upon completion of all secure SMI Memory Services. By controlling the validation and secure erase process through the use of the SMI handler and SSMS driver, information leakage can be prevented resulting in system data integrity.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Inventor: Allen C. Wynn
  • Patent number: 8788735
    Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 22, 2014
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Tatsuya Maruyama, Tsutomu Yamada, Norihisa Yanagihara, Shinji Yonemoto, Takashi Iwaki, Hiroshi Fujii
  • Patent number: 8787255
    Abstract: A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: July 22, 2014
    Assignee: Alcatel Lucent
    Inventors: Mohammad R. Khawer, Mugur Abulius
  • Patent number: 8732263
    Abstract: A network interface card may issue interrupts to a host in which the determination of when to issue an interrupt to the host may be based on the incoming packet rate. In one implementation, an interrupt controller of the network interface card may issue interrupts to that informs a host of the arrival of packets. The interrupt controller may issue the interrupts in response to arrival of a predetermined number of packets, where the interrupt controller re-calculates the predetermined number based on an arrival rate of the incoming packets.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 20, 2014
    Assignee: Juniper Networks, Inc.
    Inventor: Dharmadeep Muppalla