Interrupt Inhibiting Or Masking Patents (Class 710/262)
  • Patent number: 10430199
    Abstract: Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
  • Patent number: 10423550
    Abstract: A processing unit connected via a system fabric to multiple processing units calls a first single command in a bus protocol that allows sampling over the system fabric of the capability of snoopers distributed across the processing units to handle an interrupt. The processing unit, in response to detecting at least one first selection of snoopers with capability to handle the interrupt, calling a second single command in the bus protocol to poll the first selection of snoopers over the system fabric for an availability status. The processing unit, in response to detecting at least one second selection of snoopers respond with the available status indicating an availability to handle the interrupt, assigning a single snooper from among the second selection of snoopers to handle the interrupt by calling a third single command in the bus protocol.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard L. Arndt, Florian Auernhammer, Wayne M. Barrett, Robert A. Drehmel, Guy L. Guthrie, Michael S. Siegel, William J. Starke
  • Patent number: 10333786
    Abstract: Methods and systems for refreshing an information handling system may include receiving a request for information, searching a group inventory for the information, and responding to the request with the information. The information may correspond to a configuration. The request may be received from a node in a group with a plurality of nodes. The information requested may correspond to an update to the configuration of the node. The group inventory may be sourced from the group. The information in the response may be based on finding a match in the group inventory.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 25, 2019
    Assignee: Dell Products L.P.
    Inventors: Vigneswaran Ponnusamy, Sundar Dasar, Cyril Jose, Yogesh P. Kulkarni, Marshal F. Savage
  • Patent number: 10318193
    Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The device may be configured according to a mode in which execution of a particular command is unauthorized while the device is configured in the mode. While in the mode, the device may authorize execution of the command to occur during the mod.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 11, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ronen Haen, Shmuel Cohen, Alon Marcu
  • Patent number: 10282327
    Abstract: Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Dan F. Greiner, Jeffrey P. Kubala, James H. Mulder, Timothy J. Slegel
  • Patent number: 10083134
    Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.
    Type: Grant
    Filed: November 28, 2015
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind
  • Patent number: 10061723
    Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The background counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10042791
    Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuya Hirade, Yukitoshi Tsuboi, Ryosuke Okuda
  • Patent number: 10025923
    Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 17, 2018
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Richard Roy Grisenthwaite, Simon John Craske
  • Patent number: 10019391
    Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
  • Patent number: 10019392
    Abstract: According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
  • Patent number: 10019390
    Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventor: Nagabhushan Chitlur
  • Patent number: 9904576
    Abstract: A task scheduling method is disclosed, where each processor core is programmed with a short list of priorities, each associated with a minimum response time. The minimum response times for adjacent priorities are different by at least one order of magnitude. Each process is assigned a priority based on how its expected response time compares with the minimum response times of the priorities. Lower priorities may be assigned a timeslice period that is a fraction of the minimum response time. Also disclosed is a task division method of dividing a complex task into multiple tasks is; one of the tasks is an input gathering authority task having a higher priority, and it provides inputs to the other tasks which have a lower priority. A method that permits orderly shutdown or scaling back of task activities in case of resource emergencies is also described.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 27, 2018
    Inventor: Lawrence J. Dickson
  • Patent number: 9875198
    Abstract: A computer device includes a processor, a circuit block capable of issuing an interrupt to the processor, and a cacheable memory configured to include a register that is mapped to the logic block for storing interrupt status information of the logic block.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventor: Nagabhushan Chitlur
  • Patent number: 9858219
    Abstract: In one embodiment, a timer apparatus is configured to time a duration in which interrupts are disabled on a processor. The apparatus includes an input to receive a start signal indicating that an interrupt on a processor is disabled, a counter to determine the duration in which interrupts are disabled, and an output to signal a timer event based on the counter. The processor may be configured to trigger a hardware exception in response to the timer event signal. When the interrupts are re-enabled on the processor, the counter of the apparatus may be disabled.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventor: Satish G. U
  • Patent number: 9846578
    Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 19, 2017
    Assignee: Silicon Motion, Inc.
    Inventor: Chun-Yi Lo
  • Patent number: 9804874
    Abstract: Idle virtual machine partitions in a virtualized computing environment are consolidated onto one or more idle logical processors. A hypervisor monitors the individual utilization of multiple virtual machine partitions in a computing environment and determines which virtual machine partitions are idle. The hypervisor also monitors the individual utilization of multiple logical processors in the computing environment and determines which logical processors are idle. The hypervisor schedules all of the idle virtual machine partitions on one or more of the idle logical processors. This can improve the performance for work-generating partitions and ensure compliance with service level agreements. At the same time, it can provide efficient power management in that is consolidates idle virtual machines onto a smaller subset of logical processors.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: October 31, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig
  • Patent number: 9778950
    Abstract: Techniques are disclosed relating to processor power control and interrupts. In one embodiment, an apparatus includes a processor configured to assert an indicator that the processor is suspending execution of instructions until the processor receives an interrupt. In this embodiment, the apparatus includes power circuitry configured to alter the power provided to the processor based on the indicator. In this embodiment, the apparatus includes throttling circuitry configured to, in response to receiving a request from the power circuitry to alter the power provided to the processor, block the request until the end of a particular time interval subsequent to receipt of the request or de-assertion of the indicator. In some embodiments, the particular time interval corresponds to latency between the processor receiving an interrupt and de-asserting the indicator.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: October 3, 2017
    Assignee: Apple Inc.
    Inventor: Shu-Yi Yu
  • Patent number: 9766880
    Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 19, 2017
    Assignee: Silicon Motion, Inc.
    Inventor: Chun-Yi Lo
  • Patent number: 9594419
    Abstract: This application discloses a method for prolonging sleeping time of CPU. After CPU enters sleeping state, interrupt controller delays reporting deferrable external interrupts to the CPU, with the delay time set or as default. This application also provides a device corresponding to the method. This application can prolong the sleeping time of CPU in all kinds of intelligent electronic devices, and make the CPU enter a deep sleeping mode, thereby reducing power consumption substantially without affecting system performance.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 14, 2017
    Assignee: SONY CORPORATION
    Inventors: Hu Chen, Junjie Cai, Hao Zhao, Jing Xu
  • Patent number: 9588972
    Abstract: Software, firmware, and systems are described herein that permit an organization to dock previously-utilized, limited-feature data management modules with a full-featured data management system. By docking limited-feature data management modules to a full-featured data management system, metadata and data from the various limited-feature data management modules can be integrated and utilized more efficiently and effectively. Moreover, additional data management features can be provided to users after a more seamless transition.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 7, 2017
    Assignee: Commvault Systems, Inc.
    Inventors: Bheemesh R. Dwarampudi, Rajiv Kottomtharayil, Rahul S. Pawar, Parag Gokhale
  • Patent number: 9582438
    Abstract: A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, includes the steps of having the interrupt indicating circuit provided with a plurality of lowest-layer registers having a plurality of bits, each of the plurality of bits corresponding to the cause of the interrupt, and one or more upper-layer registers for aggregating the plurality of lowest-layer registers; forming a hierarchical structure with the one or more upper-layer registers and the plurality of lowest-layer register; and identifying the cause of the interrupt by having the processor read the upper-layer registers and the lowest-layer registers in order following the hierarchical structure.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yukio Yamazaki, Masaaki Saito
  • Patent number: 9563588
    Abstract: The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: February 7, 2017
    Assignee: Google Inc.
    Inventors: Michael Roger Marty, Joel Scherpelz
  • Patent number: 9483045
    Abstract: In a numerical controller, alarm mask information is preset. The alarm mask information is compared with alarm factor information generated by any of control circuits, and depending on a comparison result, an alarm is masked so as not to be delivered to a central processing unit. Thus, depending on the type of the alarm factor information, delivery of an alarm to the central processing unit is omitted when processing need not be stopped.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 1, 2016
    Assignee: FANUC Corporation
    Inventor: Hiroshi Okita
  • Patent number: 9469304
    Abstract: A use specifying unit specifies a “purpose of use” of a vehicle based on a running-data table. An application selection unit selects one or more information-related applications which are suitable for the “purpose of use”, from a plurality of information-related applications. Then, an execution inhibition unit inhibits execution of information-related applications which are not selected to be suitable for the specified purpose of the vehicle. As a result, it is possible to prevent information-related applications which are unnecessary for the “purpose of use” of the vehicle from being executed wastefully.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 18, 2016
    Assignee: FUJITSU TEN LIMITED
    Inventors: Kyohei Morita, Noriaki Inoue, Kazuyoshi Kasai, Yusuke Iguchi
  • Patent number: 9465673
    Abstract: A deferral instruction associated with a transaction is executed in a transaction execution computing environment with transactional memory. Based on executing the deferral instruction, a processor sets a defer-state indicating that pending disruptive events such as interrupts or conflicting memory accesses are to be deferred. A pending disruptive event is deferred based on the set defer-state, and the transaction is completed based on the disruptive event being deferred. The progress of the transaction may be monitored during a deferral period. The length of such deferral period may be specified by the deferral instruction. Whether the deferral period has expired may be determined based on the monitored progress of the transaction. If the deferral period has expired, the transaction may be aborted and the disruptive event may be processed.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9436495
    Abstract: A system, methods, and apparatus for protection against interrupts in virtual machine functions are disclosed. A hypervisor determines a first location in the memory, corresponding to a physical address of the virtual machine function. The hypervisor then determines a second location in the memory of the virtual machine function, where the second location is offset from the first location. The hypervisor modifies the virtual machine function at the second location in the memory to include checking code. The virtual machine function is executed and the checking code is executed while the virtual machine function is executing. While executing the checking code, the hypervisor determines whether interrupts are disabled on a virtual machine. Responsive to determining that interrupts are enabled on the virtual machine, disabling the interrupts on the virtual machine and/or aborting the virtual machine function.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 6, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 9411624
    Abstract: A mechanism for virtual device interrupt hinting in virtualization systems is disclosed. A method of the invention includes receiving a virtual device event from a host central processing unit (CPU) of a multi-CPU host machine, the virtual device event directed to a virtual machine (VM) managed by the hypervisor on the host machine, identifying one or more virtual CPUs (VCPUs) of the VM that are running on the host CPU, and providing the identified one or more VCPUs of the VM as a hint to the VM, the hint sent to the VM with the virtual device event, wherein the VM programs a virtual device associated with the event to deliver interrupts to a VCPU of the VM identified in the hint.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: August 9, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael S. Tsirkin
  • Patent number: 9378164
    Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Xiaowei Jiang, Srihari Makineni, Ramesh G. Illikkal, Ravishankar Iyer
  • Patent number: 9311137
    Abstract: A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing the set of instructions within the predetermined time period, the mechanism processes the interrupt.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Guenter Gerwig, Christian Jacobi, Frank Lehnert
  • Patent number: 9292328
    Abstract: Approaches for enabling Supervisor Mode Execution Protection (SMEP) for a guest operating system which does not support SMEP. A guest operating system (OS), which does not support SMEP, is executed within a virtual machine. A hypervisor instructs hardware to enable SMEP for the virtual machine executing the guest operating system. When the hypervisor is notified that the hardware has detected the guest operating system instructing a central processing unit (CPU) to execute code stored in virtual memory accessible by user space while the CPU is in supervisor mode, the hypervisor may consult a policy to identify what, if any, responsive action the hypervisor should perform.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: March 22, 2016
    Assignee: Bromium, Inc.
    Inventors: Ian Pratt, Rafal Wojtczuk
  • Patent number: 9075639
    Abstract: Disclosed are apparatus and methods for simulating a software design that is to be implemented in a system. A co-simulation platform comprising a physical link coupling a first physical component with a models module is provided. The models module emulates one or more other physical components of the system, and such models module includes a processor model associated with an interrupt service routine (ISR) for handling an interrupt on an interrupt line of the first physical component. Via a physical link, an interrupt request from the interrupt line of the first physical component is received into the models module. In response to the received interrupt request, the ISR associated with the processor model is initiated. Prior to exiting the ISR, an interrupt line de-assert request is sent from the models module to the first physical component via the physical link.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: July 7, 2015
    Assignee: Altera Corporation
    Inventor: Yi Ni
  • Patent number: 9043519
    Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plurality of functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: May 26, 2015
    Assignee: QLOGIC, Corporation
    Inventors: Bradley S. Sonksen, Richard S. Moore
  • Publication number: 20150143010
    Abstract: In a real-time embedded system, if a higher-level interrupt having a higher priority than a lower-level interrupt being processed occurs, the lower-level interrupt is stopped from being processed and the higher-level interrupt is processed. Upon completion of the processing of the higher-level interrupt, delay information about the lower-level interrupt is recorded in a compensation timer register corresponding to the lower-level interrupt, and when the processing is stopped, the lower-level interrupt is restarted. Upon completion of the processing of the lower-level interrupt, the next period of the lower-level interrupt is adjusted based on the delay information recorded in the compensation timer register to compensate for the delay.
    Type: Application
    Filed: May 6, 2014
    Publication date: May 21, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jeong Ho SON, Yun Won Choi
  • Patent number: 9021172
    Abstract: A data processing apparatus has performance monitoring circuitry for generating performance monitoring data. The performance monitoring circuitry includes a first event counter for counting occurrences of a first event and a second event counter for counting occurrences of a second event. A performance monitoring interrupt signal is indicated if, when the number of first events counted by the first event counter reaches a first threshold value, the number of second events by the second event counter meets an interrupt triggering condition.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 28, 2015
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Christopher Daniel Emmons
  • Patent number: 9015374
    Abstract: A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: April 21, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Andrew G. Kegel
  • Patent number: 8997099
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Publication number: 20150089101
    Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Publication number: 20150089102
    Abstract: Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that intercepts Input/Output requests directed to the Hard Disk Drive prior to loading a kernel of the Operating System. The interrupt handler is able to determine whether each intercepted request can be serviced with data from the boot cache, and to redirect a request to the SSD instead of the Hard Disk Drive if the request can be serviced with data from the boot cache.
    Type: Application
    Filed: February 6, 2014
    Publication date: March 26, 2015
    Applicant: LSI CORPORATION
    Inventors: Amit Kumar, Pradeep R. Venkatesha
  • Patent number: 8984200
    Abstract: One aspect provides a method comprising: ascertaining an interrupt at an information handling device having two or more cores of different size; determining if the interrupt should be directed to one of a bigger core and a littler core based on a policy for scheduling interrupts; directing the interrupt to the little core if the interrupt does not qualify as an exception based on the policy for scheduling interrupts; and processing the interrupt on an appropriate core according the policy for scheduling interrupts. Other aspects are described and claimed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Mark C. Davis, Daryl C. Cromer, Howard J. Locker, Scott E. Kelso
  • Patent number: 8966149
    Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Bruce Fleming, Arvind Mandhani
  • Patent number: 8949833
    Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N-M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: February 3, 2015
    Assignee: Fortinet, Inc.
    Inventor: Jianzu Ding
  • Patent number: 8949498
    Abstract: A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Upon occurrence of an event pertaining to a given virtual machine during a period in which the given virtual machine is unable to receive an interrupt, an interrupt message is written to a pre-assigned interrupt address in the memory. When the given virtual machine is able to receive the interrupt, after writing of the interrupt message, a context of the given virtual machine is copied from the memory to a given core on which the given virtual machine is running, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: February 3, 2015
    Assignee: Mellanox Technologies Ltd.
    Inventor: Michael Kagan
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Patent number: 8914566
    Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 16, 2014
    Assignee: Teradyne, Inc.
    Inventors: David Vandervalk, Lloyd K. Frick
  • Publication number: 20140365697
    Abstract: In a communication system, a master device gives a data control to one of a plurality of slave devices, and stops controlling data transmission and reception in the master device. A dual-role device executes the data transmission and reception with the other slave devices according to the data control given by the master device. The master device transmits an abort signal to the dual-role device while data is being transmitted and received by the dual-role device according to the data control. The dual-role device receives the abort signal from the master device, and transmits an interrupt signal to the master device when no data is being transmitted or received. The master device enables data transmission and reception according to the data control after receiving the interrupt signal from the dual-role device. The dual-role device stops data transmission and reception according to the data control after receiving the interrupt signal.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventor: Masayuki TOYAMA
  • Patent number: 8898246
    Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: November 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gary Belgrave Gostin, Larry N. McMahan, Michael A. Schroeder, Craig W. Warner, Richard W. Adkisson, Huai-Ter Victor Chong, David M. Binford, Mark Edward Shaw, Joe P. Cowan, Thierry Fevrier, Arad Rostampour
  • Publication number: 20140344491
    Abstract: Example embodiments disclosed herein relate to locking a system management interrupt (SMI) enable register of a chipset. Example embodiments include at least one contact configuration register to configure a contact of a chipset, and a contact SMI enable register of a chipset to store an enable value or a disable value. In example embodiments, the disable value stored in the contact SMI enable register is to prevent the chipset from providing an SMI request to a processor in response to an SMI signal received at the contact. Example embodiments further include locking the contact SMI enable register.
    Type: Application
    Filed: January 31, 2012
    Publication date: November 20, 2014
    Inventors: Gregory P. Ziarnik, Michael R. Durham, Mark A. Piwonka
  • Patent number: 8892803
    Abstract: Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Pyung Lee
  • Patent number: 8886862
    Abstract: A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Respective interrupt addresses in the memory are assigned to the virtual machines. Upon occurrence on a device connected to the computer of an event pertaining to a given virtual machine during a period in which the given virtual machine is swapped out of operation, an interrupt message is written from the device to a respective interrupt address that is assigned to the given virtual machine in the memory. Upon activating the given virtual machine on a given core after writing of the interrupt message, a context of the given virtual machine is copied from the memory to the given core, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: November 11, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventor: Michael Kagan