Abstract: In one embodiment, a timer apparatus is configured to time a duration in which interrupts are disabled on a processor. The apparatus includes an input to receive a start signal indicating that an interrupt on a processor is disabled, a counter to determine the duration in which interrupts are disabled, and an output to signal a timer event based on the counter. The processor may be configured to trigger a hardware exception in response to the timer event signal. When the interrupts are re-enabled on the processor, the counter of the apparatus may be disabled.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: Idle virtual machine partitions in a virtualized computing environment are consolidated onto one or more idle logical processors. A hypervisor monitors the individual utilization of multiple virtual machine partitions in a computing environment and determines which virtual machine partitions are idle. The hypervisor also monitors the individual utilization of multiple logical processors in the computing environment and determines which logical processors are idle. The hypervisor schedules all of the idle virtual machine partitions on one or more of the idle logical processors. This can improve the performance for work-generating partitions and ensure compliance with service level agreements. At the same time, it can provide efficient power management in that is consolidates idle virtual machines onto a smaller subset of logical processors.

Abstract: Techniques are disclosed relating to processor power control and interrupts. In one embodiment, an apparatus includes a processor configured to assert an indicator that the processor is suspending execution of instructions until the processor receives an interrupt. In this embodiment, the apparatus includes power circuitry configured to alter the power provided to the processor based on the indicator. In this embodiment, the apparatus includes throttling circuitry configured to, in response to receiving a request from the power circuitry to alter the power provided to the processor, block the request until the end of a particular time interval subsequent to receipt of the request or de-assertion of the indicator. In some embodiments, the particular time interval corresponds to latency between the processor receiving an interrupt and de-asserting the indicator.

Abstract: A firmware update method applied to a host device and a peripheral device, wherein the peripheral device includes a memory device and a controller. The firmware update method includes: transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector has a first mode parameter; and retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device after an interruption event has occurred on the memory device during the transmission.

Abstract: This application discloses a method for prolonging sleeping time of CPU. After CPU enters sleeping state, interrupt controller delays reporting deferrable external interrupts to the CPU, with the delay time set or as default. This application also provides a device corresponding to the method. This application can prolong the sleeping time of CPU in all kinds of intelligent electronic devices, and make the CPU enter a deep sleeping mode, thereby reducing power consumption substantially without affecting system performance.

Abstract: Software, firmware, and systems are described herein that permit an organization to dock previously-utilized, limited-feature data management modules with a full-featured data management system. By docking limited-feature data management modules to a full-featured data management system, metadata and data from the various limited-feature data management modules can be integrated and utilized more efficiently and effectively. Moreover, additional data management features can be provided to users after a more seamless transition.

Abstract: A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, includes the steps of having the interrupt indicating circuit provided with a plurality of lowest-layer registers having a plurality of bits, each of the plurality of bits corresponding to the cause of the interrupt, and one or more upper-layer registers for aggregating the plurality of lowest-layer registers; forming a hierarchical structure with the one or more upper-layer registers and the plurality of lowest-layer register; and identifying the cause of the interrupt by having the processor read the upper-layer registers and the lowest-layer registers in order following the hierarchical structure.

Abstract: The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.

Abstract: In a numerical controller, alarm mask information is preset. The alarm mask information is compared with alarm factor information generated by any of control circuits, and depending on a comparison result, an alarm is masked so as not to be delivered to a central processing unit. Thus, depending on the type of the alarm factor information, delivery of an alarm to the central processing unit is omitted when processing need not be stopped.

Abstract: A use specifying unit specifies a “purpose of use” of a vehicle based on a running-data table. An application selection unit selects one or more information-related applications which are suitable for the “purpose of use”, from a plurality of information-related applications. Then, an execution inhibition unit inhibits execution of information-related applications which are not selected to be suitable for the specified purpose of the vehicle. As a result, it is possible to prevent information-related applications which are unnecessary for the “purpose of use” of the vehicle from being executed wastefully.

Abstract: A deferral instruction associated with a transaction is executed in a transaction execution computing environment with transactional memory. Based on executing the deferral instruction, a processor sets a defer-state indicating that pending disruptive events such as interrupts or conflicting memory accesses are to be deferred. A pending disruptive event is deferred based on the set defer-state, and the transaction is completed based on the disruptive event being deferred. The progress of the transaction may be monitored during a deferral period. The length of such deferral period may be specified by the deferral instruction. Whether the deferral period has expired may be determined based on the monitored progress of the transaction. If the deferral period has expired, the transaction may be aborted and the disruptive event may be processed.

Abstract: A system, methods, and apparatus for protection against interrupts in virtual machine functions are disclosed. A hypervisor determines a first location in the memory, corresponding to a physical address of the virtual machine function. The hypervisor then determines a second location in the memory of the virtual machine function, where the second location is offset from the first location. The hypervisor modifies the virtual machine function at the second location in the memory to include checking code. The virtual machine function is executed and the checking code is executed while the virtual machine function is executing. While executing the checking code, the hypervisor determines whether interrupts are disabled on a virtual machine. Responsive to determining that interrupts are enabled on the virtual machine, disabling the interrupts on the virtual machine and/or aborting the virtual machine function.

Abstract: A mechanism for virtual device interrupt hinting in virtualization systems is disclosed. A method of the invention includes receiving a virtual device event from a host central processing unit (CPU) of a multi-CPU host machine, the virtual device event directed to a virtual machine (VM) managed by the hypervisor on the host machine, identifying one or more virtual CPUs (VCPUs) of the VM that are running on the host CPU, and providing the identified one or more VCPUs of the VM as a hint to the VM, the hint sent to the VM with the virtual device event, wherein the VM programs a virtual device associated with the event to deliver interrupts to a VCPU of the VM identified in the hint.

Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.

Abstract: A mechanism is provided for completing of set of instructions while receiving interrupts. The mechanism executes a set of instructions. Responsive to receiving an interrupt and determining that the interrupt requires processing within an implementation time frame, the mechanism delays the interrupt for a predetermined time period. Responsive to completing the set of instructions within the predetermined time period, the mechanism processes the interrupt.

Abstract: Approaches for enabling Supervisor Mode Execution Protection (SMEP) for a guest operating system which does not support SMEP. A guest operating system (OS), which does not support SMEP, is executed within a virtual machine. A hypervisor instructs hardware to enable SMEP for the virtual machine executing the guest operating system. When the hypervisor is notified that the hardware has detected the guest operating system instructing a central processing unit (CPU) to execute code stored in virtual memory accessible by user space while the CPU is in supervisor mode, the hypervisor may consult a policy to identify what, if any, responsive action the hypervisor should perform.

Abstract: Disclosed are apparatus and methods for simulating a software design that is to be implemented in a system. A co-simulation platform comprising a physical link coupling a first physical component with a models module is provided. The models module emulates one or more other physical components of the system, and such models module includes a processor model associated with an interrupt service routine (ISR) for handling an interrupt on an interrupt line of the first physical component. Via a physical link, an interrupt request from the interrupt line of the first physical component is received into the models module. In response to the received interrupt request, the ISR associated with the processor model is initiated. Prior to exiting the ISR, an interrupt line de-assert request is sent from the models module to the first physical component via the physical link.

Abstract: Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plurality of functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.

Abstract: In a real-time embedded system, if a higher-level interrupt having a higher priority than a lower-level interrupt being processed occurs, the lower-level interrupt is stopped from being processed and the higher-level interrupt is processed. Upon completion of the processing of the higher-level interrupt, delay information about the lower-level interrupt is recorded in a compensation timer register corresponding to the lower-level interrupt, and when the processing is stopped, the lower-level interrupt is restarted. Upon completion of the processing of the lower-level interrupt, the next period of the lower-level interrupt is adjusted based on the delay information recorded in the compensation timer register to compensate for the delay.

Abstract: A data processing apparatus has performance monitoring circuitry for generating performance monitoring data. The performance monitoring circuitry includes a first event counter for counting occurrences of a first event and a second event counter for counting occurrences of a second event. A performance monitoring interrupt signal is indicated if, when the number of first events counted by the first event counter reaches a first threshold value, the number of second events by the second event counter meets an interrupt triggering condition.

Abstract: A system for processing interrupts in a virtualized computing environment includes a virtual interrupt controller to provide virtual interrupts from peripherals to virtual machines. The system also includes a virtual interrupt filter that has an estimator circuit to provide an estimate of what proportion of interrupts from one or more of the peripherals are virtual interrupts. A determination is made as to whether the estimate satisfies a criterion; if it does, incoming interrupts are blocked.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: Methods and structure for utilizing a Solid State Drive (SSD) to enhance boot time for a computer. The computer includes an SSD that stores a boot cache for an Operating System of a computer, a Hard Disk Drive that stores the Operating System, and a processor. The processor is able to load an interrupt handler that intercepts Input/Output requests directed to the Hard Disk Drive prior to loading a kernel of the Operating System. The interrupt handler is able to determine whether each intercepted request can be serviced with data from the boot cache, and to redirect a request to the SSD instead of the Hard Disk Drive if the request can be serviced with data from the boot cache.

Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.

Abstract: One aspect provides a method comprising: ascertaining an interrupt at an information handling device having two or more cores of different size; determining if the interrupt should be directed to one of a bigger core and a littler core based on a policy for scheduling interrupts; directing the interrupt to the little core if the interrupt does not qualify as an exception based on the policy for scheduling interrupts; and processing the interrupt on an appropriate core according the policy for scheduling interrupts. Other aspects are described and claimed.

Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N-M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance.

Abstract: A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Upon occurrence of an event pertaining to a given virtual machine during a period in which the given virtual machine is unable to receive an interrupt, an interrupt message is written to a pre-assigned interrupt address in the memory. When the given virtual machine is able to receive the interrupt, after writing of the interrupt message, a context of the given virtual machine is copied from the memory to a given core on which the given virtual machine is running, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.

Abstract: In a communication system, a master device gives a data control to one of a plurality of slave devices, and stops controlling data transmission and reception in the master device. A dual-role device executes the data transmission and reception with the other slave devices according to the data control given by the master device. The master device transmits an abort signal to the dual-role device while data is being transmitted and received by the dual-role device according to the data control. The dual-role device receives the abort signal from the master device, and transmits an interrupt signal to the master device when no data is being transmitted or received. The master device enables data transmission and reception according to the data control after receiving the interrupt signal from the dual-role device. The dual-role device stops data transmission and reception according to the data control after receiving the interrupt signal.

Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Abstract: Example embodiments disclosed herein relate to locking a system management interrupt (SMI) enable register of a chipset. Example embodiments include at least one contact configuration register to configure a contact of a chipset, and a contact SMI enable register of a chipset to store an enable value or a disable value. In example embodiments, the disable value stored in the contact SMI enable register is to prevent the chipset from providing an SMI request to a processor in response to an SMI signal received at the contact. Example embodiments further include locking the contact SMI enable register.

Abstract: Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section.

Abstract: A method for computing includes running a plurality of virtual machines on a computer having one or more cores and a memory. Respective interrupt addresses in the memory are assigned to the virtual machines. Upon occurrence on a device connected to the computer of an event pertaining to a given virtual machine during a period in which the given virtual machine is swapped out of operation, an interrupt message is written from the device to a respective interrupt address that is assigned to the given virtual machine in the memory. Upon activating the given virtual machine on a given core after writing of the interrupt message, a context of the given virtual machine is copied from the memory to the given core, and a hardware interrupt is automatically raised on the given core responsively to the interrupt message in the memory.

Abstract: Systems and methods for debouncing a signal line within a computer device are provided. The mechanical nature of physical buttons and switches oftentimes present irregular or noisy signals on a signal line when depressed by a user. Thus, noise and/or irregular waveforms may be present on a signal line that is monitored to produce interrupt signals, when deemed valid and genuine. In many embodiments given herein, debounce modules and techniques set a debounce interval timer and/or a noise filtering interval timer in which debounce modules and/or techniques may note whether the signal line is still asserted (e.g., possibly a genuine interrupt signal) during the debounce interval timer and stable (e.g., no further interrupts have fired) during the noise filtering interval timer.

Abstract: A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. An interrupt handler of an operating system determines at least one of if the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and if the queue fails to include at least one pending reply for a previously received unprocessed interrupt. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt.

Abstract: A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold.

Abstract: A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.

Abstract: Some embodiments concern a kernel bus system for building at least one virtual machine monitor. The kernel bus system can include: (a) a hyperbus; (b) user space components; (c) guest space components configured to interact with the user space components via the hyperbus; (d) VMM components having frontend devices configure to perform I/O operations with the hardware devices of the host computer using a zero-copy method or non-pass-thru method; (e) para-virtualization components having (1) a virtual interrupt module configured to use processor instructions to swap the processors of the host computer between a kernel space and a guest space; and (2) a virtual I/O driver configured to enable synchronous I/O signaling, asynchronous I/O signaling and payload delivery, and pass-through delivery independent an QEMU emulation; and (f) KVM components. Other embodiments are disclosed.

Abstract: Systems and methods are disclosed for handling a level triggered interrupt generated by a device assigned to a virtual machine running on a host machine. An example system includes a host machine that hosts a virtual machine and a device coupled to the host machine. The device is assigned to the virtual machine and generates one or more interrupts. The example system also includes an interrupt handler that receives an interrupt generated by the device, masks the interrupt, injects the interrupt into the virtual machine, receives an indication that the virtual machine has attempted to access the device, and in response to the indication that the virtual machine has attempted to access the device, unmasks the interrupt from the device.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: An information processing system includes a memory that stores a first program and a second program, a first processor coupled to the memory and configured to execute the first program, and a second processor coupled to the memory and configured to delay execution of the second program until the first processor starts executing the first program.

Abstract: Methods, apparati, systems for including interrupt functionality in sensor interconnects field are disclosed in the present disclosure. A System on a Chip (SOC) consistent with the present disclosure includes a host and a unified sensor interconnect. A unified sensor interconnect is to be coupled to the host and at least one device. In one or more implementations, the unified sensor interconnect includes a clock line, data line, ground line, and power source line. Further, the unified sensor interconnect is to enable interrupts from at least one of the host or the at least one device.

Abstract: A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.

Abstract: An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.

Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.