Interrupt Queuing Patents (Class 710/263)
  • Patent number: 11108751
    Abstract: A first host receives a packet from a first compute node for a second compute node of a second host. The payload is larger than a maximum transmission unit size. The first packet is encapsulated with an outer header. The first host analyzes a length of at least a portion of the outer header in determining a size of an encrypted segment of the payload. Then, the first host forms a plurality of packets where each packet in the packets includes an encrypted segment of the payload, a respective encryption header, and a respective authentication value. The payload of the first packet is segmented to form a plurality of encrypted segments based on the size. The first host sends the packets to the second host and receives an indication that a packet was not received. A second packet including the encrypted segment is sent to the second compute node.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 31, 2021
    Assignee: NICIRA, INC.
    Inventors: Wenyi Jiang, Daniel G Wing, Bin Qian, Dexiang Wang
  • Patent number: 11080119
    Abstract: An information processing device is provided with: a first processing unit that generates first information by performing first processing with respect to sensor information acquired from a sensor; a second processing unit that generates second information by performing, with respect to the first information, second processing that is different from the first processing; and a third processing unit, which generates third information by performing, with respect to the first information, third processing, i.e., processing that corresponds to at least a part of the second processing, and which acquires the second information, and outputs the second information and the third information.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: August 3, 2021
    Assignees: PIONEER CORPORATION, NIKKISO COMPANY LIMITED
    Inventors: Tadashi Kondo, Wataru Onodera, Tomoya Murakami, Akari Agata, Genki Adachi
  • Patent number: 11061840
    Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: July 13, 2021
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 10985941
    Abstract: A method is described for communicating with data bus subscribers connected to a local bus, in particular a ring bus, with a local bus master, the method comprising sending a first data packet from the local bus master to all data bus subscribers for counting communication-ready data bus subscribers in a sequence, wherein the first data packet has a first counter value that is read out from each of the communication-ready data bus subscribers is changed in order; and sending a plurality of second data packets from the local bus master to all data bus subscribers, wherein the number of second data packets is based on the first counter value and wherein each of the second data packets is assigned to one of the communication-ready data bus subscribers based on the respective relative position of the communication-ready data bus subscribers in the sequence.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 20, 2021
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Daniel Jerolm
  • Patent number: 10958589
    Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Sayantan Sur, Mario Flajslik, Keith D. Underwood
  • Patent number: 10657084
    Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 19, 2020
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Darren Jue, Tao Yu, Kushagra Sharma, Tuan Van-Dinh
  • Patent number: 10650450
    Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data processing by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for processing of data using distributed network resources.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: May 12, 2020
    Assignee: ROYAL BANK OF CANADA
    Inventors: Daniel Aisen, Bradley Katsuyama, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy
  • Patent number: 10642768
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Hase, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
  • Patent number: 10467162
    Abstract: Examples include interrupting a processing resource based on a last interrupt request indicator and a work acknowledgement. Some examples include completion of work associated with a plurality of work units, storage of a last interrupt request indicator to specify a last completed work unit that includes a request to interrupt a processing resource, comparison of work unit information associated with the last interrupt request indicator with work unit information associated with a work acknowledgement generated by the processing resource, and interrupting the processing resource when the comparison indicates that the processing resource has not processed the completed work unit indicated by the last interrupt request indicator.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregory Lee Dykema, Joel Leon Lach, Michael T. Longenbach
  • Patent number: 10437735
    Abstract: A system and method relates to detecting a hardware event, determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread, identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file, identifying a memory address table associated with the file descriptor, translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread, and transmitting, to the second processing thread, a notification comprising the second virtual memory address.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Lee Arcangeli, David Alan Gilbert
  • Patent number: 10346070
    Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shinichiro Matsumura, Motohiro Sakai, Takahiro Ohyama, Takuro Kumabe, Akihito Kobayashi
  • Patent number: 10268504
    Abstract: An interrupt information processing method, a virtual machine monitor, and an interrupt controller. The method includes receiving Q pieces of first interrupt information and obtaining a corresponding interrupt processing function from a specific register according to an interrupt number of each piece of first interrupt information. Calling the obtained interrupt processing function to obtain M pieces of second interrupt information. Obtaining an identifier of a virtual machine corresponding to the M pieces of second interrupt information. Writing the M pieces of second interrupt information and the identifier of the virtual machine into a virtual CPU interrupt interface such that after determining that the virtual machine is running, the virtual CPU interrupt interface sends the M pieces of second interrupt information to a processor corresponding to the virtual machine. Technical solutions provided in the embodiments of the present disclosure are used to improve interrupt information processing efficiency.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 23, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Bo Li
  • Patent number: 10210114
    Abstract: An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that remove the need for DMA (Direct-Memory-Access) signals, Bus-request/Bus-grant signals, and bridges consequently removing the need for a bus system to connect peripherals such as the PCI (Peripheral-Connect-Interface). The I/O arbiter consists of an interrupt controller with circular buffers, FIFOs (First-In-First-Out) and port engines for directly attaching devices with proper interface buffers, together with a compatible CPU interrupt signals, and synchronous data transfers with only this one arbiter.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 19, 2019
    Assignees: UNIVERSITI TEKNOLOGI MALAYSIA, PAHLAWAN MIKRO
    Inventors: Muhammad Nasir Bin Ibrahim, Namazi Bin Azhari, Adam Bin Baharum
  • Patent number: 10187753
    Abstract: Queue Information & Prediction System (QIPS) uses the probability of queue existing in a given venue to assess the queue time. The instantaneous queue time for a location may be determined using Bluetooth, Wi-Fi, or other wireless networks. QIPS uses the distances from signal strengths along with venue characteristics to determine an estimated queue time. Using queue probability for a venue and the instantaneous queue time for the same area QIPS may generate a Queue Decision Window (QDW). The QDW is a period of time leading up to a transaction or a consumption of a service. QIPS sorts through information surrounding a venue where crowds as well as queues may exists to determine queue time. Knowing the approximate queue time for transactions and consumption of services is helpful for consumers to manage their time.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 22, 2019
    Inventors: James D Logan, Richard A Baker, Jr.
  • Patent number: 10102162
    Abstract: Processing an adaptive interrupt includes selectively setting an input/output (I/O) device in a computing system to an adaptive masking mode when at least one factor value of the at least one I/O device regarding a workload of the computing system exceeds a first threshold condition. Processing the adaptive interrupt further includes performing an interrupt masking process, where an interrupts generated by an I/O device set to the adaptive masking mode are prevented from being output when a time interval between I/O submission events of the I/O device is less than a first threshold value. The adaptive interrupt may be processed by an adaptive interrupt processing module (AIPM). The AIPM may be included in various portions of the computing system, including the I/O device and a host connected to the I/O device.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-pyung Lee
  • Patent number: 10078543
    Abstract: A switched fabric hierarchy (e.g., a PCIe hierarchy) may utilize hardware, firmware, and/or software for filtering duplicative or otherwise undesirable correctable error messages from reaching a root complex. An operating system of the root complex may detect a persistent stream or storm of correctable errors from a particular endpoint and activate filtering of correctable errors from that endpoint. A filtering device may receive filtering commands and parameters from the operating system, implement the filtering, and monitor further correctable errors from the offending device. While an offending device is being filtered, correctable error messages from the offending device may be masked from the operating system, while correctable error messages from other devices in the switched fabric hierarchy may be transmitted.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 18, 2018
    Assignee: Oracle International Corporation
    Inventors: John E. Watkins, Joseph R. Wright, John R. Feehrer
  • Patent number: 10078604
    Abstract: In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: September 18, 2018
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Arnaldo Cristobal, Marlon Verdan
  • Patent number: 10057333
    Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 21, 2018
    Assignee: ROYAL BANK OF CANADA
    Inventors: Walter Michael Pitio, Philip Iannaccone, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy, Daniel Michael Aisen, Bradley Katsuyama
  • Patent number: 9979589
    Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 22, 2018
    Assignee: ROYAL BANK OF CANADA
    Inventors: Philip Iannaccone, Walter Michael Pitio, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy, Daniel Michael Aisen, Bradley Katsuyama
  • Patent number: 9965412
    Abstract: According to one embodiment, a computer system includes a host computer, and a storage device coupled to the host computer. The host computer has a user-space device driver of the storage device in a user space of a host operating system (OS). The user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Fei Liu, Yang Seok Ki, Xiling Sun
  • Patent number: 9959572
    Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 1, 2018
    Assignee: ROYAL BANK OF CANADA
    Inventors: Philip Iannaccone, Walter Michael Pitio, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy, Daniel Aisen, Bradley Katsuyama
  • Patent number: 9952989
    Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: April 24, 2018
    Assignee: Oracle International Corporation
    Inventors: John R. Feehrer, Patrick Stabile, Hugh R. Kurth, David M. Kahn
  • Patent number: 9946670
    Abstract: Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven E. Klein, Timothy J. Van Patten
  • Patent number: 9940670
    Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data transmission by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for transmitting data using distributed network resources.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 10, 2018
    Assignee: ROYAL BANK OF CANADA
    Inventors: Daniel Aisen, Bradley Katsuyama, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy
  • Patent number: 9846626
    Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 19, 2017
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zehan Cui, Mingyu Chen, Licheng Chen, Mingyang Chen
  • Patent number: 9836226
    Abstract: A method of processing input/output (I/O) in a storage device includes adjusting a read anticipation time based on a change of a resource management status related to operations of the storage device and performing an I/O processing operation at the storage device based on the adjusted read anticipation time. The I/O processing operation is performed to postpone an operation regarding a program command and perform a read command at higher priority than a write command at the storage device in a period from completion of a read operation at the storage device until the read anticipation time has elapsed.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Ho Park, Chan-Ik Park, Chul Lee, In-Hwan Doh, Nam-Wook Kang, Kwang-Hun Lee, In-Sung Song
  • Patent number: 9830086
    Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Sun Young Lim, Indong Kim
  • Patent number: 9817586
    Abstract: A system and method for enabling an application (125, 305, 310, 315) and a storage device (120) to be more aware of each other may include a computer (105), a processor (110), and a memory (115) as well as the storage device (120). An application (125, 305, 310, 315) stored in the memory may communicate with a user space device driver (130). The user space device driver (130) may include a Mode Configure Module (320) to receive an application profile (405, 430, 435) from the application (125, 305, 310, 315) and an Application Aware Module (325) to receive I/O commands (555) from the application (125, 305, 310, 315) and place them in command queues (510, 515, 520, 525, 535, 540, 545, 550) according to the application profile (405, 430, and 435). The I/O commands (555) may then be sent to the storage device (120).
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fei Liu, Yang Seok Ki, Xiling Sun
  • Patent number: 9798682
    Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: October 24, 2017
    Assignee: Dell Products L.P.
    Inventors: Don H. Walker, William Lynn
  • Patent number: 9734110
    Abstract: In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Garrett M. Drapala, Michael F. Fee, Kenneth D. Klapproth, Robert J. Sonnelitter, III
  • Patent number: 9727500
    Abstract: Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 8, 2017
    Assignee: NXP USA, Inc.
    Inventor: William C. Moyer
  • Patent number: 9697151
    Abstract: A data processing system includes a plurality of processors, each processor configured to execute instructions, including a message send instruction, and a message filtering unit. The message filtering system is configured to receive messages from one or more of the plurality of processors in response to execution of message send instructions, each message indicating a message type and a message payload. The message filtering unit is configured to determined, for each received message, a recipient processor indicated by the message payload. The message filtering system is further configured to, in response to receiving, within a predetermined interval of time, at least two messages having a same recipient processor and indicating a same message type, delivering a single interrupt request indicated by the same message type to the same recipient processor, wherein the single interrupt request is representative of the at least two messages.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, Inc.
    Inventor: William C. Moyer
  • Patent number: 9690730
    Abstract: A register slicing circuit includes first and second register circuits, a forward channel and a backward channel. The first and second register circuits sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device. The forward channel is used for sending a first request from the first register circuit to the second register circuit, and the backward channel is used for sending back a second request from the second register circuit to the first register circuit.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 27, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Geun Yun, Sung-Hoon Shim, Bub-Chul Cheong
  • Patent number: 9547546
    Abstract: An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Markus Baumeister, Jeffrey L. Freeman
  • Patent number: 9336165
    Abstract: In a computer system, a method of controls interrupts which correspond to input/output (I/O) processing. For each delivery of an I/O completion interrupt, the method provides a recordation of a delivery time; identifies I/O completions for which deliveries of corresponding I/O completion interrupts involve deliveries of inter-processor interrupts; and for each of the identified I/O completions, accesses the recordation of the most recent delivery time to determine whether a selected period of time has elapsed since a last delivery of an inter-processor interrupt. As a response to a determination that the selected period has elapsed, an inter-processor interrupt is delivers. As a response to a determination that less than the duration of the selected period has elapsed, the method refrains from delivering an inter-processor interrupt.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 10, 2016
    Assignee: VMware, Inc.
    Inventors: Irfan Ahmad, Maxime Austruy, Mallik Mahalingam
  • Patent number: 9298652
    Abstract: The moderation of event notifications from a network interface card. The network interface card has multiple completion queues that queue of completed work. The moderation batches up this completed work such that potentially multiple work requests are aggregated into a single event notification. This moderation reduces processing overhead since it spreads the overhead associated with a single interrupt to multiple event notifications The decision on moderation may be performed per connection, or even per constituent queue of the connection. The principles herein allow moderation to reduce overhead without slowing network throughput.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 29, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas M. Talpey, Gregory R. Kramer
  • Patent number: 9274988
    Abstract: A mode switch method of an portable electronic device includes: when the electronic device is electrically connected to a host, setting the electronic device to start to be operated under a first mode; when the host has installed a operating system, detecting whether the host has a driver of the electronic device or not; when the host has the driver of the electronic device, the electronic device continues to be operated under the first mode; and when the host does not have the driver of the electronic device, switching the electronic device to be operated under a second mode.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: March 1, 2016
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chin-Yu Hsu, Yi-Huai Chen
  • Patent number: 9189245
    Abstract: A server comprises a first motherboard module. The first motherboard module comprises a first motherboard, a first CPU, at least one first memory module, a chipset, input/output units, a BIOS unit and a first QPI connector. The first CPU is disposed on the first motherboard. The first memory module electrically couples with the first CPU. The chipset electrically couples with the first CPU. The input/output units electrically couple with the chipset. The BIOS unit electrically couples with the chipset. The first QPI connector electrically couples with the first CPU through a QPI bus. The first QPI connector is connected to a second motherboard module.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 17, 2015
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Yan-Long Sun
  • Patent number: 9122515
    Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 1, 2015
    Assignee: Dell Products L.P.
    Inventors: Don H. Walker, William Lynn
  • Publication number: 20150143011
    Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Inventors: Charles W. Gainey, JR., Klaus Meissner, Damian L. Osisek, Klaus Werner
  • Publication number: 20150127865
    Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 7, 2015
    Inventors: Davide Sarta, Ignazio Antonino Urzi
  • Patent number: 8997099
    Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
  • Patent number: 8996774
    Abstract: In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Publication number: 20150089103
    Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.
    Type: Application
    Filed: December 12, 2014
    Publication date: March 26, 2015
    Inventors: Chang-hee LEE, Jung-Been IM, Jung-Yeon YOON, Young-Goo KO, Dong-Hyun SONG
  • Publication number: 20150081942
    Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 19, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA
  • Patent number: 8984201
    Abstract: In one embodiment, a system includes a local processor, a peripheral component interconnect express (PCIe) switch electrically coupled to the local processor, one or more local I2C bus devices, a dedicated processor electrically coupled to the one or more local I2C bus devices and the PCIe switch, and a local network switch electrically coupled to the dedicated processor and the PCIe switch, wherein the dedicated processor is adapted for routing interrupts from the one or more local I2C bus devices to the local processor, and wherein the local processor is adapted for handling the interrupts from the one or more local I2C bus devices. Other distributed fabric protocol (DFP) systems, computer program products, and methods are presented according to additional embodiments.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alexander P. Campbell, Keshav G. Kamble, Vijoy A. Pandey
  • Patent number: 8984137
    Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data processing by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for processing of data using distributed network resources.
    Type: Grant
    Filed: July 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Royal Bank of Canada
    Inventors: Daniel Aisen, Bradley Katsuyama, Robert Park, John Schwall, Richard Steiner, Allen Zhang, Thomas L. Popejoy
  • Publication number: 20150067217
    Abstract: Implementations of the present disclosure involve a system and/or method for handling errors in a multi-node commercial computing system running a number of guest applications simultaneously. In particular, the system and/or method provides the ability to program on a per-error basis the destination within the system for an interrupt based on an I/O error, the ability to provision for multiple/redundant error reporting paths for a class of more severe errors and/or distributed set of error status and log registers to aid software in narrowing down the source of an error that triggered the interrupt. In addition, the system provides for dynamically altering the destination of the error handling in response to one or more operating conditions of the system. Such flexibility in the system provides for a more robust error handling without impacting the performance of the multi-node computing system.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: Oracle International Corporation
    Inventors: John Ross Feehrer, Ryan Benjamin Olivastri, Patrick Francis Stabile
  • Patent number: 8959265
    Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 17, 2015
    Assignee: Mellanox Technologies Ltd.
    Inventors: Ofer Hayut, Noam Bloch, Michael Kagan, Ariel Shachar
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles