Abstract: A cloud-enterprise resource management system enables sharing of computing resources belonging to different datacenters by one or more clients of a resource pooling and sharing service. Each datacenter of includes a first partition of computing resources and a second partition of computing resources. The first partition is designated as reserved for use by an enterprise operating the datacenter. The second partition is designated as available for use by one or more clients of the resource pooling and sharing service. A workload manager in each datacenter predicts workload and transfers (i) a first computing resource from the first partition to the second partition wherein when the predicted workload is below a first threshold and (ii) a second computing resource from the second partition to the first partition when the predicted workload is above a second threshold.

Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

Abstract: Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located.

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Abstract: A method, computer program product, and computer system are provided. An adjunct processor receives an indication to reset a message queue. The reset removes all messages from the message queue on the adjunct processor. The reset is in response to a hardware failure or an external manual operation. An operation to enqueue a message to the message queue is received. Based on completing a successful enqueue operation, the adjunct processor sets a status that includes an indication that the enqueue operation is a first operation following the reset. A requestor receives the indication of the first operation. Based on the internal count of pending messages being greater than one, the requestor requeues to the adjunct processor, the message requests, except for the first message, having outstanding replies, and resets the indication of the first enqueue operation upon the requeuing of the message requests being complete.

Abstract: A method, computer program product, and computer system are provided. A message storage area of an adjunct processor (AP) crypto adapter is filled with a plurality of command request messages sufficient to maximize utilization and performance of the AP crypto adapter. In response to detecting an error during execution of one of the plurality of command request messages, generating an AP crypto adapter command reply message. The AP crypto adapter command reply message includes the error. In response to the error being a non-recoverable failure, determining a state of the command request message, wherein the state of the command request message comprises an in-process state or a request-pending state. The AP crypto adapter command reply message is formatted, wherein the formatted AP crypto adapter command reply message is stored in a message queue in the AP crypto adapter pending completion of machine failure recovery. The AP crypto adapter is recovered.

Abstract: An embodiment method for managing an operation for modifying the content of the memory plane of a memory device coupled to a processing unit, comprises a communication by the processing unit to the memory device of a control of the operation, an execution of the operation by the memory device, and at the end of the operation, a communication by the memory device itself to the processing unit of information indicating the end of the operation.

Abstract: Upon each new detection, called pivot detection, by a radar system, the method includes the steps consisting of: grouping together, with the pivot detection, grouped detections, defined as detections that belong to a sweep preceding the sweep of the pivot detection and that have a non-nil probability according to a grouping criterion; filtering the grouped detections so as to keep only detections that are kinematically strictly coherent with the pivot detection, by: initializing a histogram, each dimension of which is a temporal variation of a coordinate measured by the radar system; computing a potential value interval for each coordinate of the pivot detection and each grouped detection; computing a minimum temporal variation and a maximum temporal variation for the or each coordinate from potential value intervals of the pivot detection and each grouped detection; incrementing the set of classes of the histogram whose index along each dimension is located between the computed minimum and maximum temporal v

Abstract: A method of accessing a remote storage subsystem from a host device separate from the remote storage subsystem and connected via interfaces to a data communications topology is disclosed. In one embodiment, the communications interface comprises an RDMA network fabric. In one embodiment, the method includes queuing a write command or a read command in a submission queue of the remote storage subsystem, and placing a write data into a memory of the remote storage subsystem. The method further includes transmitting a message to the remote storage subsystem indicating the write command or the read command has been submitted in the submission queue, and detecting a command completion status from a completion queue of the remote storage subsystem. The method further includes transmitting a message to the remote storage subsystem indicating the command completion status has been detected.

Abstract: An embodiment of a radar subsystem includes at least one antenna and a control circuit. The at least one antenna is configured to radiate at least one first transmit beam and to form at least one first receive beam. And the control circuit is configured to steer the at least one first transmit beam and the at least one first receive beam over a first field of regard during a first time period, and to steer the at least one first transmit beam and the at least one first receive beam over a second field of regard during a second time period.

Abstract: A first host receives a packet from a first compute node for a second compute node of a second host. The payload is larger than a maximum transmission unit size. The first packet is encapsulated with an outer header. The first host analyzes a length of at least a portion of the outer header in determining a size of an encrypted segment of the payload. Then, the first host forms a plurality of packets where each packet in the packets includes an encrypted segment of the payload, a respective encryption header, and a respective authentication value. The payload of the first packet is segmented to form a plurality of encrypted segments based on the size. The first host sends the packets to the second host and receives an indication that a packet was not received. A second packet including the encrypted segment is sent to the second compute node.

Abstract: An information processing device is provided with: a first processing unit that generates first information by performing first processing with respect to sensor information acquired from a sensor; a second processing unit that generates second information by performing, with respect to the first information, second processing that is different from the first processing; and a third processing unit, which generates third information by performing, with respect to the first information, third processing, i.e., processing that corresponds to at least a part of the second processing, and which acquires the second information, and outputs the second information and the third information.

Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.

Abstract: A method is described for communicating with data bus subscribers connected to a local bus, in particular a ring bus, with a local bus master, the method comprising sending a first data packet from the local bus master to all data bus subscribers for counting communication-ready data bus subscribers in a sequence, wherein the first data packet has a first counter value that is read out from each of the communication-ready data bus subscribers is changed in order; and sending a plurality of second data packets from the local bus master to all data bus subscribers, wherein the number of second data packets is based on the first counter value and wherein each of the second data packets is assigned to one of the communication-ready data bus subscribers based on the respective relative position of the communication-ready data bus subscribers in the sequence.

Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.

Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data processing by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for processing of data using distributed network resources.

Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

Abstract: Examples include interrupting a processing resource based on a last interrupt request indicator and a work acknowledgement. Some examples include completion of work associated with a plurality of work units, storage of a last interrupt request indicator to specify a last completed work unit that includes a request to interrupt a processing resource, comparison of work unit information associated with the last interrupt request indicator with work unit information associated with a work acknowledgement generated by the processing resource, and interrupting the processing resource when the comparison indicates that the processing resource has not processed the completed work unit indicated by the last interrupt request indicator.

Abstract: A system and method relates to detecting a hardware event, determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread, identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file, identifying a memory address table associated with the file descriptor, translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread, and transmitting, to the second processing thread, a notification comprising the second virtual memory address.

Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: An interrupt information processing method, a virtual machine monitor, and an interrupt controller. The method includes receiving Q pieces of first interrupt information and obtaining a corresponding interrupt processing function from a specific register according to an interrupt number of each piece of first interrupt information. Calling the obtained interrupt processing function to obtain M pieces of second interrupt information. Obtaining an identifier of a virtual machine corresponding to the M pieces of second interrupt information. Writing the M pieces of second interrupt information and the identifier of the virtual machine into a virtual CPU interrupt interface such that after determining that the virtual machine is running, the virtual CPU interrupt interface sends the M pieces of second interrupt information to a processor corresponding to the virtual machine. Technical solutions provided in the embodiments of the present disclosure are used to improve interrupt information processing efficiency.

Abstract: An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that remove the need for DMA (Direct-Memory-Access) signals, Bus-request/Bus-grant signals, and bridges consequently removing the need for a bus system to connect peripherals such as the PCI (Peripheral-Connect-Interface). The I/O arbiter consists of an interrupt controller with circular buffers, FIFOs (First-In-First-Out) and port engines for directly attaching devices with proper interface buffers, together with a compatible CPU interrupt signals, and synchronous data transfers with only this one arbiter.

Abstract: Queue Information & Prediction System (QIPS) uses the probability of queue existing in a given venue to assess the queue time. The instantaneous queue time for a location may be determined using Bluetooth, Wi-Fi, or other wireless networks. QIPS uses the distances from signal strengths along with venue characteristics to determine an estimated queue time. Using queue probability for a venue and the instantaneous queue time for the same area QIPS may generate a Queue Decision Window (QDW). The QDW is a period of time leading up to a transaction or a consumption of a service. QIPS sorts through information surrounding a venue where crowds as well as queues may exists to determine queue time. Knowing the approximate queue time for transactions and consumption of services is helpful for consumers to manage their time.

Abstract: Processing an adaptive interrupt includes selectively setting an input/output (I/O) device in a computing system to an adaptive masking mode when at least one factor value of the at least one I/O device regarding a workload of the computing system exceeds a first threshold condition. Processing the adaptive interrupt further includes performing an interrupt masking process, where an interrupts generated by an I/O device set to the adaptive masking mode are prevented from being output when a time interval between I/O submission events of the I/O device is less than a first threshold value. The adaptive interrupt may be processed by an adaptive interrupt processing module (AIPM). The AIPM may be included in various portions of the computing system, including the I/O device and a host connected to the I/O device.

Abstract: In an embodiment of the invention, a method comprises: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In another embodiment of the invention, an apparatus comprises: an interrupt controller configured to collect a plurality of interrupts and configured to service coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired. In yet another embodiment of the invention, an article of manufacture comprises: a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: collecting a plurality of interrupts and servicing coalesced active interrupts to a processor if an interrupt count limit has occurred or if a timeout count has expired.

Abstract: A switched fabric hierarchy (e.g., a PCIe hierarchy) may utilize hardware, firmware, and/or software for filtering duplicative or otherwise undesirable correctable error messages from reaching a root complex. An operating system of the root complex may detect a persistent stream or storm of correctable errors from a particular endpoint and activate filtering of correctable errors from that endpoint. A filtering device may receive filtering commands and parameters from the operating system, implement the filtering, and monitor further correctable errors from the offending device. While an offending device is being filtered, correctable error messages from the offending device may be masked from the operating system, while correctable error messages from other devices in the switched fabric hierarchy may be transmitted.

Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.

Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.

Abstract: According to one embodiment, a computer system includes a host computer, and a storage device coupled to the host computer. The host computer has a user-space device driver of the storage device in a user space of a host operating system (OS). The user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer.

Abstract: Systems, methods, and computer-readable media for coordinating processing of data by multiple networked computing resources include monitoring data associated with a plurality of networked computing resources, and coordinating the routing of data processing segments to the networked computing resources.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.

Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data transmission by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for transmitting data using distributed network resources.

Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

Abstract: A method of processing input/output (I/O) in a storage device includes adjusting a read anticipation time based on a change of a resource management status related to operations of the storage device and performing an I/O processing operation at the storage device based on the adjusted read anticipation time. The I/O processing operation is performed to postpone an operation regarding a program command and perform a read command at higher priority than a write command at the storage device in a period from completion of a read operation at the storage device until the read anticipation time has elapsed.

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

Abstract: A system and method for enabling an application (125, 305, 310, 315) and a storage device (120) to be more aware of each other may include a computer (105), a processor (110), and a memory (115) as well as the storage device (120). An application (125, 305, 310, 315) stored in the memory may communicate with a user space device driver (130). The user space device driver (130) may include a Mode Configure Module (320) to receive an application profile (405, 430, 435) from the application (125, 305, 310, 315) and an Application Aware Module (325) to receive I/O commands (555) from the application (125, 305, 310, 315) and place them in command queues (510, 515, 520, 525, 535, 540, 545, 550) according to the application profile (405, 430, and 435). The I/O commands (555) may then be sent to the storage device (120).

Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.

Abstract: In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.

Abstract: Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor.

Abstract: A data processing system includes a plurality of processors, each processor configured to execute instructions, including a message send instruction, and a message filtering unit. The message filtering system is configured to receive messages from one or more of the plurality of processors in response to execution of message send instructions, each message indicating a message type and a message payload. The message filtering unit is configured to determined, for each received message, a recipient processor indicated by the message payload. The message filtering system is further configured to, in response to receiving, within a predetermined interval of time, at least two messages having a same recipient processor and indicating a same message type, delivering a single interrupt request indicated by the same message type to the same recipient processor, wherein the single interrupt request is representative of the at least two messages.

Abstract: A register slicing circuit includes first and second register circuits, a forward channel and a backward channel. The first and second register circuits sequentially store requests received from a plurality of master devices to output the stored requests toward a slave device. The forward channel is used for sending a first request from the first register circuit to the second register circuit, and the backward channel is used for sending back a second request from the second register circuit to the first register circuit.

Abstract: An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device.

Abstract: In a computer system, a method of controls interrupts which correspond to input/output (I/O) processing. For each delivery of an I/O completion interrupt, the method provides a recordation of a delivery time; identifies I/O completions for which deliveries of corresponding I/O completion interrupts involve deliveries of inter-processor interrupts; and for each of the identified I/O completions, accesses the recordation of the most recent delivery time to determine whether a selected period of time has elapsed since a last delivery of an inter-processor interrupt. As a response to a determination that the selected period has elapsed, an inter-processor interrupt is delivers. As a response to a determination that less than the duration of the selected period has elapsed, the method refrains from delivering an inter-processor interrupt.

Abstract: The moderation of event notifications from a network interface card. The network interface card has multiple completion queues that queue of completed work. The moderation batches up this completed work such that potentially multiple work requests are aggregated into a single event notification. This moderation reduces processing overhead since it spreads the overhead associated with a single interrupt to multiple event notifications The decision on moderation may be performed per connection, or even per constituent queue of the connection. The principles herein allow moderation to reduce overhead without slowing network throughput.

Abstract: A mode switch method of an portable electronic device includes: when the electronic device is electrically connected to a host, setting the electronic device to start to be operated under a first mode; when the host has installed a operating system, detecting whether the host has a driver of the electronic device or not; when the host has the driver of the electronic device, the electronic device continues to be operated under the first mode; and when the host does not have the driver of the electronic device, switching the electronic device to be operated under a second mode.

Abstract: A server comprises a first motherboard module. The first motherboard module comprises a first motherboard, a first CPU, at least one first memory module, a chipset, input/output units, a BIOS unit and a first QPI connector. The first CPU is disposed on the first motherboard. The first memory module electrically couples with the first CPU. The chipset electrically couples with the first CPU. The input/output units electrically couple with the chipset. The BIOS unit electrically couples with the chipset. The first QPI connector electrically couples with the first CPU through a QPI bus. The first QPI connector is connected to a second motherboard module.

Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.