Abstract: A server comprises a first motherboard module. The first motherboard module comprises a first motherboard, a first CPU, at least one first memory module, a chipset, input/output units, a BIOS unit and a first QPI connector. The first CPU is disposed on the first motherboard. The first memory module electrically couples with the first CPU. The chipset electrically couples with the first CPU. The input/output units electrically couple with the chipset. The BIOS unit electrically couples with the chipset. The first QPI connector electrically couples with the first CPU through a QPI bus. The first QPI connector is connected to a second motherboard module.

Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

Abstract: A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.

Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.

Abstract: In one embodiment, a system includes a local processor, a peripheral component interconnect express (PCIe) switch electrically coupled to the local processor, one or more local I2C bus devices, a dedicated processor electrically coupled to the one or more local I2C bus devices and the PCIe switch, and a local network switch electrically coupled to the dedicated processor and the PCIe switch, wherein the dedicated processor is adapted for routing interrupts from the one or more local I2C bus devices to the local processor, and wherein the local processor is adapted for handling the interrupts from the one or more local I2C bus devices. Other distributed fabric protocol (DFP) systems, computer program products, and methods are presented according to additional embodiments.

Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data processing by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for processing of data using distributed network resources.

Abstract: Implementations of the present disclosure involve a system and/or method for handling errors in a multi-node commercial computing system running a number of guest applications simultaneously. In particular, the system and/or method provides the ability to program on a per-error basis the destination within the system for an interrupt based on an I/O error, the ability to provision for multiple/redundant error reporting paths for a class of more severe errors and/or distributed set of error status and log registers to aid software in narrowing down the source of an error that triggered the interrupt. In addition, the system provides for dynamically altering the destination of the error handling in response to one or more operating conditions of the system. Such flexibility in the system provides for a more robust error handling without impacting the performance of the multi-node computing system.

Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt.

Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.

Abstract: In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available (i.e., currently unused) capacity of the hardware interrupt buffer is allocated based on those programmed scale factors. If the node determines to handle the detected event using the hardware interrupt buffer, then the node stores a hardware interrupt corresponding to the detected event in the hardware interrupt buffer. Otherwise, the node handles the detected event using a fallback action.

Abstract: The present disclosure relates to a method and an apparatus for allocating interruptions in a multi-core system. A method for allocating interruptions in a multi-core system according to one embodiment of the present disclosure comprises: an interrupt load extraction step of extracting interrupt loads of each interruption type; a step of extracting task loads of each core; a weighting factor determination step of determining weighting factors using a difference between task loads of the cores; a step of reflecting weighting factors to extract a converted value of the interrupt load; and an interruption allocation step of allocating interruption types to the cores such that the sums of the converted values of the interrupt loads allocated to each core and the allocated task loads are uniform. According to one embodiment of the present disclosure, interruptions can be allocated such that both task processing and interruption processing can be performed in an efficient manner.

Abstract: A method of interrupt control for an electronic system, the electronic system including a host and an electronic device, includes receiving digital data generated by the electronic device; determining a value of the digital data and dividing a possible range of the value of the digital data into a plurality of regions; and sending an interrupt signal to the host when the value of the digital data changes from a first region among the plurality of regions to a second region among the plurality of regions and remains within the second region for a specific period of time.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: The moderation of event notifications from a network interface card. The network interface card has multiple completion queues that queue of completed work. The moderation batches up this completed work such that potentially multiple work requests are aggregated into a single event notification. This moderation reduces processing overhead since it spreads the overhead associated with a single interrupt to multiple event notifications The decision on moderation may be performed per connection, or even per constituent queue of the connection. The principles herein allow moderation to reduce overhead without slowing network throughput.

Abstract: A central manager receives tick subscription requests from subscribers, including a requested period and an allowable variance. The manager selects a group period for a group of requests, based on requested period(s) and allowable variance(s). In some cases, the group period is not a divisor of every requested period but nonetheless provides at least one tick within the allowable variance of each requested period. Ticks may be issued by invoking a callback function. Ticks may be issued in a priority order based on the subscriber's category, e.g., whether it is a user-interface process. An application platform may send a tick subscription request on behalf of an application process, e.g., a mobile device platform may submit subscription requests for processes which execute on a mobile computing device. Tick subscription requests may be sent during application execution, e.g., while the application's user interface is being built or modified.

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: A system and method for creating a guaranteed MSI latency by coupling a coprocessor, which may be a dedicated agent, to the existing front side bus (“FSB”) in a processor (e.g., Intel® Atom™ processor) to handle deterministic interrupts. MSI interrupts may be automatically forwarded to the coprocessor using the existing Direct Cache Access field. Users may control the handling time and methodology of MSI interrupts.

Abstract: Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.

Abstract: A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.

Abstract: A method for providing notification of completion of a computing task includes providing access to an information handling resource for a first information handling system, registering the first information handling system with a first completion queue, submitting commands from the first information handling system to a first submission queue, providing access to the information handling resource for second first information handling system, registering the second information handling system with the first completion queue, and submitting commands from the second information handling system to a second submission queue. Upon execution of commands in the first submission queue and the second submission queue, an entry in is created a first completion queue. Upon the creation of an entry in the first completion queue, an interrupt is selectively sent to the first information handling resource and to the second information handling resource.

Abstract: A hardware interrupt processing circuit converts selected hardware interrupts to an interrupt vector having bits corresponding to the selected hardware interrupts. The hardware interrupt processing circuit includes circuit assemblies that correspond to the selected hardware interrupts. Each circuit assembly includes a detector circuit and a persistent capture circuit. The detector circuit is to output a pulse responsive to the corresponding selected hardware interrupt being asserted. The persistent capture circuit is triggered by the persistent capture circuit to output a corresponding bit of the interrupt vector until a ready signal has been asserted.

Abstract: Available buffers in the memory space of a guest operating system of a virtual machine are provided to a network interface controller (NIC) for use during direct memory access (DMA) and the guest operating system is notified accordingly when data is written into such available buffers. These capabilities obviate the requirement of using hypervisor memory as a staging area to determine which virtual machine to forward incoming data.

Abstract: A network interface card may issue interrupts to a host in which the determination of when to issue an interrupt to the host may be based on the incoming packet rate. In one implementation, an interrupt controller of the network interface card may issue interrupts to that informs a host of the arrival of packets. The interrupt controller may issue the interrupts in response to arrival of a predetermined number of packets, where the interrupt controller re-calculates the predetermined number based on an arrival rate of the incoming packets.

Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a queue using the APD, generating a user-level interrupt and transmitting to the CPU the plurality of tasks in the queue using an interrupt handler associated with a CPU thread.

Abstract: Techniques are described that can be used by a message engine to notify a core or hardware thread of activity. For example, an inter-processor interrupt can be used to notify the core or hardware thread. The message engine may generate notifications in response to one or more message received from a transmitting message engine. Message engines may communicate without sharing memory space.

Abstract: One or more techniques and/or systems are provided for suspending logically related processes associated with an application, determining whether to resume a suspended process based upon a wake policy, and/or managing an application state of an application, such as timer and/or system message data. That is, logically related processes associated with an application, such as child processes, may be identified and suspended based upon logical relationships between the processes (e.g., a logical container hierarchy may be traversed to identify logically related processes). A suspended process may be resumed based upon a wake policy. For example, a suspended process may be resumed based upon an inter-process communication call policy that may be triggered by an application attempting to communicate with the suspended process. Application data may be managed while an application is suspended so that the application may be resumed in a current and/or relevant state.

Abstract: A conversion unit converts a command part of an image inclusion command into an internal command. A first memory unit stores an image non-inclusion command and the internal command converted by the conversion unit. A second memory unit stores an image data part of the image inclusion command. A restart page number memory unit stores restart page number information when a print process being executed is interrupted in order to execute an interruption print process. When restarting the interrupted print process, a control unit executes control to read out the internal command and the image non-inclusion command stored in the first memory unit up to the page indicated by the restart page number information, and from the page indicated by the restart page number, further executes control to read out from the second memory unit the image data part following the internal command read out from the first memory unit.

Abstract: A LAN control unit receives print data from a client device or the like. An input job storage unit registered on a hard disk a series of PDL commands included in the print data received. An input job queue management unit registers print job specifying information specifying a print job represented by the print data received to the end of an input job queue. A PDL interpretation/execution unit successively executes from the head of the series of PDL commands stored on the hard disk device. When it is determined that the PDL command that has been executed is a re-execution unnecessary command, the PDL interpretation/execution unit overwrites the PDL command stored on the hard disk with a NOP command.

Abstract: An apparatus which comprises two or more moderation timers associated with an interrupt vector is presented. In one embodiment, the apparatus comprises two or more interrupt vectors and moderation timers are set with different interrupt rates. An interrupt vector logic unit sends an interrupt vector if there is an interrupt event from the queue associated with a moderation timer and the moderation timer expires.

Abstract: A method, system, and computer program product identify extraneous input/output interrupts for a queued input/output device architecture. At least one interrupt is determined to have been generated for at least one queue in a plurality of queues of a queued input/output device architecture. An interrupt handler of an operating system determines at least one of if the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and if the queue fails to include at least one pending reply for a previously received unprocessed interrupt. The interrupt is identified as an extraneous interrupt in response to the determining one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and that the queue fails to include at least one pending reply for a previously received unprocessed interrupt.

Abstract: A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt.

Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data processing by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for processing of data using distributed network resources.

Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.

Abstract: Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device. The method is a method in which the embedded operating system kernel determines a handling mode for all individual interrupts, the method includes: dividing interrupt handling modes into a first interrupt handling mode and a second interrupt handling mode which has a different process speed from the first interrupt handling mode, and variably determining a distribution ratio in which each of the interrupts are distributed to the first interrupt handling mode or to the second interrupt handling mode according to a predetermined process condition during boot-up.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: A method and system for processing an input/output request on a multiprocessor computer system comprises pinning a process down to a processor issuing the input/output request. An identity of the processor is passed to a device driver which selects a device adapter request queue whose interrupt is bound to the identified processor and issues the request on that queue. The device accepts the request from the device adapter, processes the request and raises a completion interrupt to the identified processor. On completion of the input/output request the process is un-pinned from the processor. In an embodiment the device driver associates a vector of the identified processor with the request and the device, on completion of the request, interrupts the processor indicated by the vector.

Abstract: A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

Abstract: Preventing time out of an IO transaction during CPU re-initialization by controlling the IO transaction so that the time when the IO transaction is continuously stopped during the CPU re-initialization process is within a predetermined time that prevents complete time out of an interrupt of an IO transaction. In a case where the IO transaction would be continuously stopped for greater than the predetermined time during a CPU re-initialization the IO transaction is stopped and restarted within the predetermined time. The status of the interrupt during such stopping and starting is stored so as not to loose the interrupt status during the interval between such stopping and starting.

Abstract: A method for issuing interrupts includes a receiving communication adapter receiving a first remote directed memory access (RDMA) write with immediate, identifying a completion queue descriptor corresponding to the first RDMA write with immediate and to a receiving entity, incrementing an interrupt counter in response to the first RDMA write with immediate. The method further includes storing, by the receiving communication adapter, in response to determining that the interrupt counter value is less than the interrupt threshold value, data in the first RDMA write with immediate on the receiving device without triggering an interrupt to the receiving entity. The receiving communication adapter further receives a second RDMA write with immediate, and increments the interrupt counter value corresponding to the completion queue descriptor in response to the second RDMA write with immediate.