Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and a single set of interrupt status-registers. The interrupts are generated by the interrupt generator in an order determined by the order of tasks sent by the CPU to the interrupt generator and indicate completion of those tasks. The CPU can maintain in the storage element an ordered list of at least a contiguous subset of the tasks sent to the interrupt generator. The CPU can also maintain in the storage element a count of tasks sent to the interrupt generator as part of the contiguous subset. For each interrupt it generates the interrupt generator increments the count in the interrupt counter and writes the address of the interrupt to the interrupt status register. Because a single interrupt status register is used, only the status information for the latest interrupt is available in the register.

Abstract: The invention provides structure and method to control the presentation of interrupts to a computer system by delaying communication of the interrupts to the host computer or processor according to predetermined rules. In particular, the method of the invention first detects the occurrence of an I/O interrupt related to a device. Next, the method reserves notification to the host processor of the I/O interrupt for a period of time based on a set of predetermined rules. Finally, the method notifies the host processor of substantially all I/O interrupts for which notification has been reserved during the period of time at expiration of the period of time, whereby the reserve notification lowers the overhead to the host processor in handling the I/O interrupts.

Abstract: Queue processing mechanism in which queued messages are processed based on combination of queue delay and queue priority. A scheduler dequeues the highest priority non-empty Microcode Input Queue (MIQ) to serve the queued messages. If there is no critical queue, meaning that the maximum aging of one or more queues has not been reached, the critical state is not entered. A static weight for each queue is then tested to determine if there is still a message to be processed from the corresponding MIQ. Messages are dequeued from the same MIQ until the static weight is reached. The next MIQ is then served etc., until the queue of the lowest priority level is served. If the critical phase is entered, the status of the normal state is stored for later return and the MIQs in critical state are dequeued according to their critical weights. If other MIQs appear to be critical, they are served in the order of their critical priorities (or weights).

Abstract: A programmable controller includes memory for storing a ladder logic control program having a plurality of ladder logic instruction rungs. Each rung begins with a start of rung (SOR) instruction. A processor is coupled to the memory for executing the ladder logic control program. User interrupts are disabled during execution of the rungs. During execution of the SOR instruction, a predetermined register, such as a MCR register, is read causing simultaneous enabling of user interrupts which overrides the previously disabled user interrupts to allow the processor to receive an interrupt request signal. The interrupt request signal is received before the read function of the predetermined register has completed.

Abstract: A multi-processor system is provided having a processor array configured of a plurality of CPUs (20) that are disposed on a global bus (14). A VEM interface (18) is provided for interfacing between the global bus (14) and a system bus (12). Interrupts that are generated on the system bus (12) are mapped to the CPUs (20) through an interrupt controller (82). The interrupt controller (82) is operable to receive multiple interrupts and store these interrupts and their associated interrupt vectors. After storage, a gating register associated with each CPU (20) is examined to determine which interrupts are serviced by a particular CPU (20). If an interrupt is received that is to be serviced by one or more of the CPUs (20), then an external interrupt is generated for that CPU (20).

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods.

Abstract: The present invention provides a method, device and article of manufacture for efficient transfer of data items between a host processor and an external device. The host processor is coupled to external queue pointers and is used for queuing a plurality of data items and transferring the plurality of data items to the external device using an interrupt service routine unit. The external device is coupled to the host processor and is used for storing and incrementing or decrementing the external queue pointers, and processing the data items.

Abstract: A method and apparatus for reducing interrupt density in a computer system. One or more interrupt events received at a first device are stored in a memory and an interrupt is issued from the first device to a second device attached to the first device upon an occurrence of a first predefined event, wherein the second device retrieves the stored interrupt events from the memory and processes the retrieved interrupt events in response to the issued interrupt. Thereafter, an interrupt is issued for every interrupt event from the first device to the second device after the occurrence of the first predefined event until an occurrence of a second predefined event. After the occurrence of the second predefined event, the interrupt events received at a first device are again stored in the memory without issuing an interrupt from the first device to the second device. Finally, an interrupt is issued from the first device to the second device upon another occurrence of the first predefined event.

Abstract: A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Abstract: A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request.

Abstract: A hardware implemented command queuing system in a hardware accelerated command interpreter engine. The command queuing system is an integral component of an autonomous hardware accelerated command interpreter type data processing engine that executes a programmable set of data processing commands in response to a stimulus from a host processor. The command queuing system is a configuration of registers and logic blocks that interact with a local host processor and other components within the command interpreter engine itself. The local host processor generates the commands to execute and the command queuing system queues the commands for seriatim execution by components within the command interpreter system.

Abstract: An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count.

Abstract: To facilitate access of interrupt status information, interrupt posting status. POST.sub.-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST.sub.-- STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST.sub.-- STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST.sub.-- STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST.sub.-- STAT registers. A host system software driver accesses the interrupt posting status POST.sub.

Abstract: A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers coupled to the inputs of the plurality of logical "OR" gates. Each logical "OR" gate corresponds to one of the second plurality of registers.

Abstract: Methods and apparatus process a plurality of interrupt status words from a network interface controller (NIC) to a plurality of processes. A first per-virtual circuit interrupt status word and a second per-virtual circuit interrupt status word can be sent by a per-virtual circuit interrupter having a per-virtual circuit interrupt output. A NIC interrupter can be in communication with the per-virtual circuit interrupt output and have a NIC interrupt output to send a first NIC interrupt status word and a second NIC interrupt status word to a global interrupt queue of a host system. The NIC interrupter can generate an interrupt signal to the host system, and a proxy interrupt handler of the host system can be in communication with the NIC interrupter.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A method and system for interrupt-responsive execution of a communications protocol which obtains data sent by a sending computer a receiving computer via a communications interface. An interrupt handler routine is provided which includes the communications protocol. When data requested by an application executing on the receiving computer is received by the communications interface, an interrupt is sent by the communications interface to the CPU in the receiving computer. When this interrupt is received, the interrupt handler routine is immediately accessed and executed to timely execute the communications protocol. As a result, the communications protocol obtains the data from the communications interface before it can be overwritten by new data sent by the sending computer. The application program can then be executed at a later time to read the data obtained.

Abstract: An interrupt system having three tiers is provided. The first tier includes individual interrupt and enable registers, each of which provides multiple local interrupt signals in response to various events in a multiport switch. Local enable signals are supplied to the individual interrupt and enable registers to enable the local interrupt signals to be written into a global interrupt status register that provides the second tier of the interrupt system. The global interrupt status register produces several global interrupt signals, each of which represents one of the individual interrupt and enable registers. The third tier of the interrupt system includes a switch command register that generates an interrupt pending signal if any one of the global interrupt signals is produced. A global enable signal provided by the host processor enables the switch command register to produce an interrupt request signal to be supplied to a host processor.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: The present invention relates to handling an interrupt between the multiple interrupt generating resources for use in connection with a pended bus and a host system, in which there is disclosed a multiple interrupt controller using an intelligent priority-decision mechanism and control method thereof which makes possible to transmit various interrupt resources within the system that is connected to the pended bus toward the host system through one interrupt line among the bus.

Abstract: A central processing unit (CPU) (162) furnishes an interrupt request acknowledge signal (107) to an interrupt control unit (ICU) (101) in response to an interrupt request signal (106) from the ICU (101). Then the CPU (102) reads the address specifying the origin of a program to process the interrupt request. After that, the CPU (102) causes the interrupt request acknowledge signal (107) to make a transition to its deactivated state. In response to the transition in the interrupt request acknowledge signal, the ICU (101) causes the interrupt request signal (106) to make a transition to its deactivated state and then clears an interrupt priority level signal (108) showing the priority level of the interrupt request (106).