Abstract: A computer system or peripheral device includes an arithmetic-logic circuit that provides, for example, in binary parallel format a maximum code from a set of input codes, each input code in binary parallel format. The circuit has minimal propagation delay owing to its expandable architecture which includes: an array of product term generators, a summary term generator, and a selection circuit. Each product term generator primarily includes one AND gate per product term having inputs that combine bits of an input code, the product terms being organized in sets. The summary term generator includes one OR gate for each summary term. The selection circuit includes a multiplexer for each set having data inputs responsive to summary term signals and control inputs responsive to summary term signals of higher significance than the highest summary term on a data input of the multiplexer. In illustrated embodiments, a printer includes an integrated circuit processor of the present invention.

Abstract: A noise reducing method for a radio portable terminal having a radio section for transmitting and receiving radio data, a CPU (Central Processing Unit), connected to the radio section and incorporating a cache, for performing predetermined data processing, and an external memory connected to the CPU, reads an internal operation program runnable only in the CPU from the external memory and stores the internal operation program in the cache prior to reception of the radio data, and then executes only the internal operation program. In this manner, this method suppresses access to the external memory, thereby reducing noise.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: An apparatus and method for communicating the completion of asynchronous I/O requests is provided. In particular, the apparatus and method make use of a new function call which is capable of waiting for a predetermined number of I/O requests to be completed prior to returning to the calling application. Control blocks for the I/O requests are updated after a predetermined number of I/O requests have been completed, i.e. in a process context rather than in an interrupt context as in the known systems. In this way, the overhead associated with known asynchronous I/O system calls is reduced.

Abstract: A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.

Abstract: In a peripheral component interconnect (PCI) bus system in which both intelligent and non-intelligent devices are connected to the PCI bus, each non-intelligent device is owned and managed by an intelligent device. The intelligent device owning a non-intelligent device provides access to the service functions of the non-intelligent device, making these service functions available even to other devices not possessing device drivers for the non-intelligent device. Accordingly, the PCI bus master does not have to access all devices connected to the PCI bus.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: In a message-passing, queue-oriented bus system, a separate interrupt work queue assigned to each interrupt line for each PCI device sends interrupt information packets from the device to the host. To prevent an interrupt from being transmitted before another DMA data write has been completed, interrupt requests are held on the interrupt work queue until all outstanding data transfer requests have been acknowledged. A special data structure called an interrupt scoreboard is created for each interrupt work queue entry associated with a DMA write in order to track the DMA data transfer. When an interrupt is received, the interrupt scoreboard acquires a “snapshot” of the state of the pending data requests and tracks the pending DMA transfers. When acknowledgement messages have been received for all pending DMA transfer requests, then the interrupt data packet is transmitted so that the interrupt can be serviced.

Abstract: Translation of PCI level interrupts into packet based messages for edge event drive microprocessors includes, a bridge device receiving interrupts via an interrupt line from one or more PCI devices. The bridge device further sends an interrupt write packet to a CPU to launch the interrupt routine. The interrupt routine services the interrupt and the PCI device negates the interrupt line. At this point, the CPU generates a non-blocking write. This write causes the bridge to check the level of the PCI interrupt line. If the line is active with the interrupt, another write packet is sent, otherwise the interrupt line is negated and the blocking write is ignored. As a result, the present invention prevents an interrupt from a PCI device from being overlooked, from being missed, or from repeating the interrupt by a microprocessor.

Abstract: To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.

Abstract: The present invention relates generally to interrupt processing. One embodiment relates to a method for executing an interrupt in a data processing system including fetching a conditional store instruction that is conditional upon a reservation, receiving notice that an interrupt is pending, invalidating a reservation in response to receiving the notice, and processing the interrupt. Invalidating the reservation allows the conditional store instruction to finish in a predetermined amount of time and properly update an architectural state of the processor. Therefore, interrupt latencies (the amount of time between receiving and processing an interrupt) corresponding to the conditional store instruction can be bounded. The method may be used in a single processor or multi-processor data processing system, wherein each processor includes a reservation register.

Abstract: A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, peripheral component events are coalesced. The time interval between succeeding peripheral component events is determined. This time interval is then compared to a time threshold. This process continues until the time interval between succeeding peripheral component events meets or exceeds the time threshold. Once the time interval between succeeding peripheral component events meets or exceeds the time threshold, an interrupt is generated. By appropriately selecting a time threshold, idle periods are identified. Thus, the present invention generates interrupts when idle conditions exist, optimizing the generation of interrupts. By optimizing the generation of interrupts, the number of interrupts generated is reduced, minimizing the CPU overhead associated with the servicing of interrupts.

Abstract: A communications system includes a communications channel, a first processing unit; and interface unit, and an interrupt controller. The first processing unit is adapted to monitor the communications channel and provide a plurality of status bits. The interface unit includes an interrupt register. The interrupt controller is adapted to identify a plurality of interrupts in response to changes in the status bits. Each interrupt has a priority, and the interrupt controller is adapted to store selected interrupts in the interrupt register in an order determined by the priority of the interrupts. A method includes monitoring a communications channel. A plurality of status bits associated with the monitoring are provided. A plurality of interrupts are identified based on changes in the status bits, each interrupt having a priority. Selected interrupts are stored in an interrupt queue in an order determined by the priority of the interrupts.

Abstract: A method for communication between a network interface adapter and a host processor coupled thereto includes writing information using the network interface adapter to a location in a memory accessible to the host processor. Responsive to having written the information, the network interface adapter places an event indication in an event queue accessible to the host processor. It then asserts an interrupt of the host processor that is associated with the event queue, so as to cause the host processor to read the event indication and, responsive thereto, to process the information written to the location.

Abstract: An interrupt management system includes a first down-counter which decrements in value in response to a clock signal to zero. When the value of the down-counter is equal to zero the down-counter is reset to a predetermined value X and an interrupt request signal is produced. The interrupt management system also includes a second down-counter which decrements in value from a predetermined value Y, where Y>X, in response to the clock signal. The interrupt request signal is received by a processor which services the interrupt and generates an interrupt serviced signal. The interrupt serviced signal is received by a controller which also receive the value of the second down-counter. Using the received value from the second down-counter, the controller can determine if an interrupt request has been missed and also determine the latency period for servicing an interrupt request.

Abstract: A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, peripheral component events are coalesced. The time that a peripheral component event has been stored is determined. This time interval is then compared to a storage time threshold. This process continues until the time that a peripheral component event has been stored meets or exceeds the storage time threshold. Once time that a peripheral component event has been stored meets or exceeds the storage time threshold, an interrupt is generated. By appropriately selecting a storage time threshold, the generation of interrupts is optimized. As a result, the present invention optimizes the generation of interrupts, reducing the frequency with which interrupts are generated, and minimizing the CPU overhead associated with the servicing of interrupts.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A queueing control system including a control unit (2) and a plurality of call units (14) that are connected to the control unit (2), each said call unit (14) including a call switch (24) that, when activated by a customer, causes the call unit to transmit to the control unit a “call” signal that contains information uniquely identifying the call unit, the control unit (2) including means for recognising “call” signals received from the call units and placing the call units associated with those signals in a queue according to the order in which the “call” signals were received, the system further including display means (4) driven by the control unit that, in use, identifies the call unit that is at the front of the queue.

Abstract: The processors in a multiprocessor computer system are grouped into nodes. The processors can request a lock, but the lock is granted to only one processor at any given time to provide exclusive processor access to the resource protected by the lock. When a processor releases the lock, the lock is made available to another processor at the same node, even though a processor at a different node may have requested the lock earlier. To maintain fairness, the lock is forced to another node after granting a certain number of consecutive requests at a node or after a certain time period. In one embodiment, a specialized data structure representing a lock request from a processor at a particular node is placed into a queue. A later requesting processor can acquire a preemptive position in the queue by spinning on a data structure already in the queue if the data structure corresponds to the processor's node.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: An input/output (I/O) controller in an I/O system processes I/O requests from a host computer to a plurality of I/O devices. The I/O controller generates an interrupt to the host computer and reports a plurality of completed I/O requests from the I/O devices when at least one condition of the I/O system is met. A first condition of the I/O system comprises a predetermined ratio between the total number of unreported I/O completions by the I/O devices and the total number of remaining I/O requests from the host computer. A second condition comprises the expiration of a timer, which starts when the number of remaining I/O requests left to process for any individual I/O device reaches a predetermined minimum limit.

Abstract: An interrupt handling mechanism within a data processing system is used to assign interrupts among multiple interrupt presentation controllers while avoiding the use of a significant amount of signal lines. An interrupt input message from an interrupt source controller is input into an interrupt presentation controller. Fields are added to the interrupt input message to facilitate the assignment of the interrupt input message to an interrupt presentation controller. The input interrupt message is passed between the interrupt presentation controller in a sequential fashion such that the collection of controllers forms a logical ring. On the first circle of the ring, the priority of the processors capable of handling the interrupt is discovered. A second pass through the interrupt presentation controller is used to assign the first processor that is both capable of taking the interrupt and also has an equal or lower priority to that noted on the first pass as to best priority.

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals.

Abstract: The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller (10) includes a main processor (12), a memory (14), a device interface (18) adapted to interface a peripheral component (28-32), such as a RAID storage device, with the storage system controller, and an operations sequencer (24). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Abstract: In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals.

Abstract: In some embodiments, the invention includes an apparatus including a host bridge coupled to a processor bus. The apparatus also includes an I/O bridge coupled to the host bridge, the I/O bridge including ports to receive an interrupt request signal in the form of address signals and data signals. Decode logic receives at least some of the address signals and data signals and to provide a decoded signal responsive thereto. A redirection table includes a send pending bit that is set responsive to the decoded signal.

Abstract: An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction.

Abstract: A method and apparatus are provided for supporting multiple display sessions through a single address on a non-programmable-terminal (NPT) attached to a host computer by a work station controller (WSC). The WSC enables shared addressing of multiple display sessions on the NPT. The WSC changes focus to a selected one of the multiple display sessions responsive to receiving from the host computer a data stream for a requested display session not having the focus and responsive to receiving a change focus request from the NPT. The NPT may have one display session active for the user interface and a different display session having the focus communicating with the host computer, which is transparent to the user and to the host computer.

Abstract: In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Abstract: A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, peripheral component events are coalesced. A peripheral component such as, for example, a network interface card generates a first interrupt when the number of coalesced peripheral component events meets a quantity threshold. In the present embodiment, a peripheral component driver such as, for example, a network interface card driver then services the first peripheral component event. In one embodiment of the present invention, the peripheral component then services any existing coalesced peripheral component event (or events) that has not yet generated a respective interrupt. The service of peripheral component events is monitored for determining the quantity of peripheral component events not serviced. The number of peripheral component events not serviced is then used to vary the quantity threshold.

Abstract: A processor for controlling execution of instructions stored in a main storage and interruption processing, comprises: interruption processing control device operable to accept an interruption request, analyze an accepted interruption to obtain a cause of the interruption, and generate information indicating a storage position in the main storage of a procedure for processing the cause of the interruption; specific address holding device operable to hold first address information obtained from the information generated by the interruption processing control device; and instruction execution control device operable to decide whether or not the first address information held by the specific address holding device is to be used as information indicating a storage position of an instruction to be executed and control instruction execution according to a decision result.

Abstract: System and method for scheduling I/O requests in a multi-tasking data processing environment. An I/O request issued by an application is placed in an I/O request holding queue. Under control of the requesting application (or, alternatively, the operating system), the I/O request is selectively canceled or moved to a service pending queue for execution. Requests can be moved either by the application or by the Operating system when an I/O completes (and hence the service pending queue has room for another IO).

Abstract: A compiler comprises a using register control table by function, a using register extracting unit by function for extracting a using register and a call function name, in every function, based on the intermediate code generated from a source program, and registering the same into the using register control table by function, a using register totaling unit by function for totaling the registers used by a call function called by an interruption function, and newly registering the totaled registers in the using register control table by function as the using registers of the interruption function, and an output unit for adding saving/return codes of a using register of the interruption function to the intermediate code, with reference to the using register control table by function so to generate and supply an assembly program file.

Abstract: An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

Abstract: A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pending interrupt request exists based on a status of the shared interrupt request flag. In the event that a pending interrupt request exists, a notification of the pending interrupt request is provided to an interrupt service routine. In the event that a pending interrupt request does not exist the circuitry that is reading or polling the shared interrupt request flag delays for a polling interval and then repeats reading or polling the shared interrupt request flag and determining whether a pending interrupt request exists.

Abstract: A method and an apparatus for handling interrupt requests generated by a plurality of interrupt sources (2A, 2N) for a processor. The method includes steps of scanning interrupt registering means (8) for determining a current interrupt request to be sent to the processor among interrupt requests having respective interrupt flags inputted in said interrupt registering means, and steps involving the processor for execution of an interrupt processing program according to the result of a comparison of a scanned interrupt flag with a predetermined flag value, characterised in that it includes a step of latching a flag corresponding to a first occurring interrupt request from a source in a group of sources into interrupt latch registering means (7) for further processing and for blocking further interrupt requests from at least the same source in the same group from having a flag latched before processor controlled resetting.

Abstract: A method and system for efficiently servicing a peripheral component event. In one embodiment of the present invention, a peripheral component such as, for example, a network interface card generates a first interrupt upon the occurrence of a first peripheral component event. In the present embodiment, a peripheral component driver such as, for example, a network interface card driver then services the first peripheral component event. In this embodiment of the present invention, the peripheral component then services any existing coalesced peripheral component event (or events) which has not yet generated a respective interrupt. In so doing, the present embodiment eliminates the need for the existing coalesced peripheral component event to generate an additional interrupt at some later time. As a result, the present embodiment reduces the frequency with which interrupts are generated, and minimizes the CPU overhead associated with the servicing of interrupts.

Abstract: A programmable interrupt controller (510) for a single interrupt architecture processor (518) includes a plurality of interrupt sources (502) each operable to generate an interrupt. A dynamically alterable interrupt mask (508) selectively blocks interrupt signals for the interrupt sources (502). Interrupts permitted by the dynamically alterable interrupt mask (508) are processed by an interrupt handler (500) for the single interrupt architecture processor (518) in order of priority. In addition, processing for a lower priority interrupt is interrupted in order to process a later received higher priority interrupt permitted by the dynamically alterable interrupt mask (508).

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a mailbox register to receive interrupt request information sent after a data write transaction. The data is sent from an initiating peripheral device over the buffered bus to arrive with an arbitrary delay at the host memory. After completing the sending phase for the data the initiating peripheral device sends a mailbox register data block containing an interrupt request to a mailbox register associated with the host processor. Because the mailbox register data block will necessarily arrive after the receipt of the actual data in the host memory because it is following the actual data through the same buffered bus, the interrupt will be properly sequenced with the receipt of data.

Abstract: A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Abstract: A data processing apparatus has a basic processing unit (BPU) 2, a channel processor (CHP) 10, message channel units (MCH) 11n, message channel receivers (MCHR) 6m connected respectively to the message channel units 11n, and a structured external storage device (SES) 6 which may be connected to a plurality of hosts via the message channel receivers 6m and which includes a cache memory 8 for accommodating data shared by the hosts. Before issuing a synchronous instruction, a program issues an instruction notifying in advance the inventive apparatus of the intended use of hardware resources. When the hardware resources are reserved by the notifying instruction, the apparatus guarantees the subsequent execution of the synchronous instruction. Because synchronous instructions are always carried out, the system overhead is lowered.

Abstract: Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among the interrupt controller, the state machine, and the queues is coordinated by a queue manager. For sending an interrupt, the interrupt controller accepts an interrupt placed on a bus within the node and intended for another node and stores it in the send queue. The controller then notifies the interrupt source that the interrupt has been accepted before it is transmitted to other node. The interrupt has a first form suitable for transmission on the bus. A state machine within the node takes the interrupt from the send queue and puts the interrupt into a second form suitable for transmission across a network connecting the multiple nodes.

Abstract: A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

Abstract: An interrupt mechanism which reduces or eliminates the need for an interrupt status register while at the same time provides suitable information to a host or other processor with respect to the cause and parameters surrounding an interrupt signal. An interrupt queue is maintained in shared memory accessible by both a host and an interrupting agent. The interrupt queue has a capacity or two or more separate interrupt requests, either from a same interrupting agent or from two different interrupting agents. As interrupting agents write to the interrupt queue, an agent current interrupt pointer (ACIP) is incremented to a next position in the interrupt queue. As the host services interrupts, the current host pointer is incremented to clear the serviced interrupt request entry.

Abstract: Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether or no the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern n the interrupt activation condition flag storing unit. As a result of the determination, an interrupt process is performed in accordance with an operational description storing unit which stores a process corresponding to the flag pattern if the pattern exits. Thereafter, bit for the flag corresponding to the executed process is cleared out.