Abstract: A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Abstract: Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among the interrupt controller, the state machine, and the queues is coordinated by a queue manager. For sending an interrupt, the interrupt controller accepts an interrupt placed on a bus within the node and intended for another node and stores it in the send queue. The controller then notifies the interrupt source that the interrupt has been accepted before it is transmitted to other node. The interrupt has a first form suitable for transmission on the bus. A state machine within the node takes the interrupt from the send queue and puts the interrupt into a second form suitable for transmission across a network connecting the multiple nodes.

Abstract: An interrupt load distribution system for a shared bus type multiprocessor system includes a processor statistical information table for storing processor statistical information consisting of processor activity ratios under the use by the operating system, processor activity ratios under the use by processes executing under a processor bind, and number of processes requesting a bind from each processor, an interrupt schedule information table for storing interrupt schedule information, an interrupt scheduler for referring to said two tables at fixed time intervals and re-scheduling interrupt load distribution as necessary to achieve appropriate distribution, and an I/O control part for notifying the designated processor of an interrupt request by reflecting a re-schedule created by the interrupt scheduler.

Abstract: One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register.

Abstract: Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether or no the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern n the interrupt activation condition flag storing unit. As a result of the determination, an interrupt process is performed in accordance with an operational description storing unit which stores a process corresponding to the flag pattern if the pattern exits. Thereafter, bit for the flag corresponding to the executed process is cleared out.

Abstract: The number of interrupts are controlled by delaying communication of the interrupt to the host computer or processor according to predetermined rules. This reduces the processing overhead and greatly increases system performance. Application of the inventive structure and method to network servers and RAID disk drive storage arrays is particularly beneficial. In one embodiment, the invention provides structure and method for reducing the number of system interrupts to the host processor to reduce host processor overhead for operation of a computer system having a host processor and a peripheral device coupled to the host processor by a device controller. In another embodiment, the invention provides structure and method for clustering command completion prior to posting completion. System, apparatus, method, and computer program products are described.

Abstract: A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

Abstract: A method for causing two programmable interrupts to take place is described herein, using a counter having an output having an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising loading the first register with a first value, loading the second register with a second value, simultaneously causing the counter to count down from said first value to zero, and causing an output of a timer to be a binary “0” during a first portion of the counter period, comparing the value of the first register to the value of the second register, causing, when the value of the first register and the second register are equal, the output of the counter to be a binary “1” until the value of the first register becomes zero.

Abstract: In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.

Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: A system generates interrupts in response to events and dynamically accommodates for changing rates of event generation. A number of events may be bundled together to generate one or more interrupts instead of generating an interrupt for each event. For example, in connection with network controllers, each time a frame is received, it may be stored and bundled with a predetermined number of other frame receipt events to decrease the number of interrupts which must be handled. If a timer times out before all of the predetermined events have occurred, the ensuing bundle size may be decreased. Conversely, if all of the events occur before the timer times out, the ensuing bundle may be increased in size. In this way, the system dynamically accommodates for increased or decreased event activity, optimizing the number of interrupts that may be necessary.

Abstract: One embodiment of the present invention provides a method that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices.

Abstract: An interrupt tracking mechanism includes a CPU that handles interrupts generated by an interrupt generator, a storage element accessible to the CPU, an interrupt counter implemented in hardware and a single set of interrupt status-registers. The interrupts are generated by the interrupt generator in an order determined by the order of tasks sent by the CPU to the interrupt generator and indicate completion of those tasks. The CPU can maintain in the storage element an ordered list of at least a contiguous subset of the tasks sent to the interrupt generator. The CPU can also maintain in the storage element a count of tasks sent to the interrupt generator as part of the contiguous subset. For each interrupt it generates the interrupt generator increments the count in the interrupt counter and writes the address of the interrupt to the interrupt status register. Because a single interrupt status register is used, only the status information for the latest interrupt is available in the register.

Abstract: A fault tolerant task dispatching technique schedules a plurality of tasks, monitors the progress of each task on a periodic basis, detects when a task has failed, and initializes a failed task in a manner that does not interfere with the execution of any non-failed task. Task granularity, afforded by the fault tolerant dispatch technique, allows each task (device service routine) to be designed substantially independently of any other task. This, in turn, can ease the design and implementation of individual tasks as well as their integration into a computer system.

Abstract: A reception indicator is within a network peripheral that receives information packets for a host system from a communications network. The reception indicator of the present invention allows the network peripheral to operate in one of a plurality of modes. The reception indicator of the present invention asserts an interrupt signal at a respective optimum interrupt time for each of the modes. If the network peripheral is operating in a programmed I/O mode (i.e. a slave mode), a slave optimum interrupt time is determined. In this mode, a host processor unit within the host system reads portions of information packets from a readable data port in a host system interface. In this mode, an interrupt is asserted at the slave optimum interrupt time before a last byte of an information packet is expected to be received from the communications network. If the network peripheral is operating in a DMA (Direct Memory Access) mode, a DMA (Direct Memory Access) optimum interrupt time is determined.

Abstract: A method and system for dynamic creation of APIC tables under the ACPI specification using existing APIC tables under the MP specification in a multi-processor computer. The method of the present invention provides for the dynamic creation of APIC entries in a computer memory, and includes the steps of: scanning the memory for an MP APIC header, reading MP APIC entries from a location in the memory indicated by the MP APIC header, building ACPI APIC entries in the memory from at least a portion of the MP APIC entries read, and updating an ACPI APIC header in the memory after the ACPI APIC entries have been built.

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programing of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-"OR" bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.

Abstract: In an interrupt steering circuit for a computer system having a PCI bus connected to four expansion slots, a controller includes a non-volatile memory previously storing a selection information of an initialization device select signal. Four selectors are provided to the four expansion slots, respectively. Each of the selectors is controlled by the controller on the basis of the selection information of the non-volatile memory for selecting one bit of an address/data bus of the PCI bus to supply the selected bit to a corresponding one of the "n" expansion slots. The non-volatile memory is rewritable in a software manner by the computer system, so that the device number of the devices connected to the expansion slots can be changed on the basis of the value set in the non-volatile memory.

Abstract: An interrupt management system that enables a user to handle interrupt events either in a real time mode of operation, or in a batch mode of operation. In the real time mode, an interrupt request signal is asserted in response to each interrupt event. In the batch mode, an interrupt request signal is delayed until a predetermined number of interrupt events is detected, or until a predetermined time interval has elapsed since the last interrupt event is captured. In response to an interrupt event, the corresponding bit in an interrupt register is set to an active state. A control interrupt bit is provided in an interrupt control register for each interrupt to enable the activation of an interrupt request pin in response to the interrupt event. A batch enable bit is provided in a batch register for each interrupt event to enable the batching of the interrupt event.

Abstract: A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Abstract: A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request.

Abstract: An interrupt mechanism for an operating system is portable to different data processing hardware. The interrupt mechanism includes a software interrupt management component which manages at least one software interrupt process and buffers system parameters in an interrupt stack during the software interrupt processing. The management component is configured to be hardware independent. A hardware dependent component is operable to select the interrupt stack and then to call the management component for managing software interrupt processing. The hardware dependent interface also deselects the interrupt stack on completion of software interrupt processing. It is thus possible to provide generic management process for software interrupts with a minimum of "glue" code.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match registers for special framing characters. Further, however, address bits are provided within the serial data, and additional matching bits are provided for matching those address bits along with the character data within the matching registers. In this way, not only is framing data detected by the detection of special characters, but a microcontroller can determine when it is being addressed in a multidrop, address bit protocol system by matching the address bit and address data.

Abstract: A circuit configuration for generating an interrupt signal for a microprocessor includes a multiplicity of signal generating circuits that are connected to one another via a logic combination element. Each of the signal generating circuits is configured to activate an intermediate signal when a specific event occurs for an assigned input signal. On the input side, each signal generating circuit has a respective edge detector for detecting rising and falling edges, which are routed via demultiplexers and two further logic combination elements to the set and reset inputs of a flip-flop. The structure can be programmed flexibly and detects, by hardware, an interrupt state with no additional computation loading on the microprocessor.

Abstract: An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a particular interrupt. An interrupt register from a plurality of interrupt registers is selected via an address decoder, and data bits from the selected interrupt register are steered to a data bus. Each interrupt register has a corresponding trailing edge detector which clears the data content of the interrupt register after a first one of a plurality of data processors has read the data bits of that interrupt register on the data bus to service that particular interrupt. In this manner, a second one of the data processors which also attempts to service that particular interrupt reads the cleared content of that interrupt register.

Abstract: An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.

Abstract: To facilitate access of interrupt status information, interrupt posting status. POST.sub.-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST.sub.-- STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST.sub.-- STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST.sub.-- STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST.sub.-- STAT registers. A host system software driver accesses the interrupt posting status POST.sub.

Abstract: A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers map each of a plurality of interrupts to an appropriate one of a second plurality of registers and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers coupled to the inputs of the plurality of logical "OR" gates. Each logical "OR" gate corresponds to one of the second plurality of registers.

Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

Abstract: An interrupt controller comprises a plurality of interrupt handling elements that are given different identification numbers for identification to which priorities are assigned. A first priority encoder accepts a plurality of level signals which are given different level numbers respectively representing the priorities assigned to the identification numbers, and then encodes the level number assigned to the highest-priority level signal included among all level signals at a low potential so as to generate an interrupt level number representing the encoded level number.

Abstract: A system and method for auto-polling a status register within a physical layer (PHY) interface to a local area network (LAN). The system includes a host CPU which needs to detect and service interrupts generated by a PHY device on the LAN which is coupled between a first transmission medium (such as copper or fiber cable) and a management interface to the system. The system further includes an auto-polling unit which monitors activity on the management interface of the PHY device. When the auto-polling unit detects a lack of activity on the management interface of the PHY for a predetermined interval, the auto-polling unit reads a first value from the PHY status register. This first status value is then compared to a previously stored value which corresponds to the last PHY status value read by the host CPU. If a mismatch is detected between these two values, an interrupt is generated to the CPU.

Abstract: A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock.

Abstract: A method and apparatus for generating an interrupt signal. A counter value is decremented each time a task is completed by a slave processor. The counter value is incremented each time a task is read by the slave processor. A delay value is set using the counter value. An interrupt is generated after a period of time set by the delay value has passed. The counter value is compared to a threshold value. The interrupt is generated upon detecting a condition in which the counter value is less than the threshold value or when the completion queue is full instead of after the period of time.

Abstract: An object-oriented interrupt processing system in a computer system creates a system database including a device namespace containing an entry for each device in the computer system and an interrupt namespace containing each entry in the interrupt source, arranged as an Interrupt Source Tree. Each entry in the Interrupt Source Tree is cross-referenced to a corresponding entry in the device namespace and contains a reference to an interrupt handler for the corresponding interrupt source. When an interrupt occurs, a single interrupt dispatcher is invoked, to access the Interrupt Source Tree and cause execution of the corresponding interrupt handler.

Abstract: A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

Abstract: A computer system includes first and second integrated circuits. A direct memory access (DMA) controller circuit on the first integrated circuit receives a direct memory access request (DRQ) input signal which is provided from the second integrated circuit, across a signal line of said bus. The value of the DRQ signal is updated at predetermined intervals on the signal line. A DMA synchronization control circuit on the first integrated circuit prevents the DMA controller circuit from evaluating its DRQ input signal, once a DMA operation has started, until after the value of the DRQ input signal has been updated by the second integrated circuit. In addition, the DMA acknowledge signal from the DMA controller circuit is mapped to an address indicative of the acknowledge signal, and the address is sent to the second integrated circuit.

Abstract: A computer system includes first and second integrated circuits. The first integrated circuit provides a first input/output bus operating in accordance with a first protocol, such as ISA. The first input/output bus includes a plurality of address and data lines respectively providing address and data information. The second integrated circuit includes a plurality of second functional blocks at least some of which interface to legacy devices. The first integrated circuit includes a host controller circuit, coupled to the first input/output bus and for coupling to a register access bus which includes a register data out and a register data in signal line. The register access bus connects the first and second integrated circuits. The host controller circuit receives address and data information from the input/output bus and serially provides the address and data information to the data out line. A target controller circuit on the second integrated circuit is coupled to the register access bus.

Abstract: A computer system having an advanced programmable interrupt controller (APIC) is described in which an I/O APIC module is included in core logic circuitry coupled between a processor bus and a system bus. An interrupt controller is included in bridge circuitry coupled between the system bus and an expansion bus. System and expansion bus devices requiring service output interrupt request signals (IRQs) which are received by the interrupt controller. The interrupt controller then outputs an interrupt signal which is received by the I/O APIC module. The I/O APIC module initiates a system bus acknowledge cycle to receive an interrupt vector from the interrupt controller. The I/O APIC module converts the interrupt vector into a system-appropriate APIC protocol and transmits the vector on an APIC bus to local APIC modules integrated within processors of the computer system.

Abstract: A multiprocessor system and method for minimizing perturbations while monitoring parallel applications. Perturbations due to monitoring the application are minimized by synchronizing all the nodes within the system to a very accurate global time clock such that all the nodes running the application stop and restart running the application at the same time. Within the time period bounded by the stop and restart time, all the performance monitoring data is transferred from performance monitoring data buffers to a secondary memory.

Abstract: Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a particular interrupt input; if it does, determining whether that particular interrupt input is programmed to be a level-triggered interrupt; if it is, determining whether the level-status of that particular interrupt input is active; and, if it is, sending a level-triggered active message for the highest priority pending interrupt, by maintaining the set status of a particular bit.

Abstract: A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.

Abstract: A computer system is capable of playing audio CDs in a CD-ROM drive independent of the operating system by using an embedded CD-ROM drive application or a CD-ROM drive controller. When an audio CD mode switch of the computer system is in an "on" state and the main power switch of the computer is in an "off" state, the computer system is in an audio CD mode. When the computer is placed in such an audio CD mode, the computer either loads the embedded CD application from a non-volatile memory region such as read-only-memory (ROM) region or enables the CD-ROM drive controller of the CD-ROM drive to receive a CD selection and transmit the selections to the CD-ROM drive.

Abstract: A data transfer system including a data transmission unit and a data reception unit, the data transmission unit including an arithmetic unit which, when accepting an interruption during data transfer, suspends processing in execution and immediately switches to a mode for executing the interruption processing, and the data reception unit including a received data accepting unit for temporarily accumulating received data, a data storage unit for receiving and storing received data accumulated at the received data accepting unit after the data transfer processing is completed, and a transfer control unit for inhibiting processing of shifting received data accumulated at the received data accepting unit to the data storage unit when detecting suspension of the data transfer processing due to generation of an interruption at the data transmission unit.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of the signal's generation. The first module then directs the signal to a second module, and causes the signal to be delivered to the second module.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.

Abstract: A flexible general input/output function utilizes a programmable logic circuit in conjunction with general purpose input/output pins. A programmable logic circuit receives the input signals from the input terminals. The programmable logic circuit program conditions the input signals and provides conditioned input signals to the remainder of the integrated circuit. An input register receives the conditioned input signals from the programmable logic circuit, and stores values representing the state of respective conditioned input signals. A transition detection circuit detects a specified transition for each of the conditioned input signals it receives and provides an indication of the specified transition. An interrupt circuit is responsive to transition indications provided from the transition detection circuit to generate an interrupt signal associated with the specified transition of a respective conditioned input signal.