Abstract: Apparatus, and an associated method, for requesting initiation of generation of an interrupt at an I/O APIC (input/output advanced programmable interrupt controller) of a multi-processor computer system. Initiation of generation of the inter-processor interrupt is requested by a peripheral component device, such as a PCI bus controller, not directly connected to an APIC bus extending to interrupt controllers associated with each of the processors of the multi-processor computer system. The interrupt permitted to be initiated by the peripheral component device includes, inter alia, a remote read request.

Abstract: Hardware and software triggered programmable reset circuitry for a serial communication device. The invention has particular use in conjunction with an IEEE 1394 standard serial communication device ("serial card") within a computer system. The serial communication device is for coupling with a peripheral component interface (PCI) bus of the computer system. The serial communication device provides a serial bus onto which other devices can connect. The present invention provides a reset circuit that is triggered by software and/or hardware. In one embodiment, the software triggering portion of the invention is triggered by three sources. A particular address range is predefined and software triggered accesses over this address range cause a reset on the serial card. Second, a predefined device ID pattern is presented to a device ID circuit causing the device ID circuit to generate a reset on the serial card.

Abstract: A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To this end, interrupt-time data structures and representations are precomputed and represented. The taxonomy of real time data types is organized. It is preferable to include isochronous media, together with supporting algorithms and heuristics.

Abstract: A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: An interrupt circuit on a first integrated circuit receives a plurality of interrupt request signals, at least one of which is provided over a bus. A interrupt synchronization control circuit receives an update synchronization signal, indicating when a value of one of the interrupt requests provided to the interrupt circuit has been updated. The interrupt synchronization control circuit also receives an end of interrupt from a processor. The interrupt synchronization control circuit prevents the interrupt circuit from reevaluating its interrupt request signals based on the end of interrupt until after a next update synchronization signal is received, thus synchronizing the reevaluating of interrupt requests to receipt of updated interrupt request information.

Abstract: The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt blocks. The interrupt blocks are used for coupling to a corresponding plurality of peripheral devices. Each of the interrupt blocks are coupled to a data bus included within the interrupt controller. The interrupt controller also includes an interrupt control register. The interrupt control register is coupled to each of the interrupt blocks, and upon receiving an internal interrupt request from any of the interrupt blocks, asserts a processor interrupt request responsive to the internal interrupt request. The interrupt controller includes a processor interrupt request line adapted to couple to a programmable digital processor.