Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: An interconnection controller for use in a computer system having a plurality of processor clusters is described. Each cluster includes a plurality of local nodes and an instance of the interconnection controller. The interconnection controller is operable to transmit locally generated interrupts to others of the clusters, and remotely generated interrupts to the local nodes. The interconnection controller is further operable to aggregate locally generated interrupt responses for transmission to a first remote cluster from which a first interrupt corresponding to the locally generated responses was generated. The interconnection controller is also operable to aggregate remotely generated responses for transmission to a first local node from which a second interrupt corresponding to the remotely generated responses was generated. A computer system employing such an interconnection controller is also described.

Abstract: In one embodiment, a method is provided. The method of this embodiment may include controlling, at least in part, by a first device, whether a first signal line of a second device is coupled to a bus, and whether a second signal line of a third device is coupled to the bus. The method of this embodiment may also include, after the first and second signal lines are coupled to the bus, supplying from the first device to the second and third devices, via the first and second signal lines, one or more signals that, after being received by the second and third devices, may permit, at least in part, at least one of control and configuration by the first device of the second and third devices. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: The invention relates to the processing of state information such as interrupt status in a hierarchical network of nodes having a tree configuration. There is a root node at the top of the hierarchy, one or more intermediate nodes, and a plurality of leaf nodes at the bottom of the hierarchy. Each leaf node is linked to the root node by zero, one or more intermediate nodes. Each leaf node maintains information about one or more interrupt states, and each intermediate node maintains information derived from the interrupt states of leaf nodes below it in the hierarchy. This interrupt information is then processed by navigating from the root node to a first leaf node having at least one set interrupt state which is then masked out. The status of any intermediate nodes between this first leaf node and the root node is then updated if appropriate to reflect the fact that the particular interrupt state at the first leaf node is now masked out.

Abstract: A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Abstract: A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: The aggregation of hardware events in multi-node systems is disclosed. An event occurring at a remote node is forwarded to a primary node, by firmware of the remote node writing to a first register of the primary node. The event is propagated from the first register of the primary node to a second register node. In automatic response, an interrupt is generated at the primary node. An interrupt handler of the primary node, in response to generation of the interrupt, then invokes code at the primary node to handle the event occurring at the remote node.

Abstract: A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruction may include an address of a register which holds the loop count value. The instruction immediately following the repeat instruction is the target instruction for repetition. The processing includes repeating execution of the target instruction according to the loop count value in a low processor cycle overhead manner. The processing may also include handling interrupts during repeat instruction processing in a low-overhead manner during the initial call of the interrupt service routine as well as upon returning from the interrupt service routine.

Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.

Abstract: An integrated circuit (7A) for multitasking support for processing unit (1A) holds control variables for each task (or activity) to run on its associated processor (1A) and identifies the next task that should run. The circuit (7A) employs level-driven, clock free ripple logic and is configured as a two dimensional array of “tiles”, each tile being composed of simple logic gates and performing a dedicated function. The circuit has particular application to asynchronous multiple processor networks.

Abstract: In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal processor sends a data packet to a target digital signal processor. Upon arrival at the target digital signal processor, its receiver drives the arriving request packet into an I/O memory and triggers a transmitter interrupt. Next, the pull interrupt causes the transmitter to execute on a next packet boundary the pull request packet. Finally, the execution of the pull request causes the transmitter to pull a portion of the local I/O memory and send it back to the requester digital signal processor. The same physical portion of the I/O memory is overlaid with two logical uses, a receiver channel and a transmitter code block.

Abstract: An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction.

Abstract: A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor depending on particular interrupts received. Wherein, THUMB program execution is more economical with program code space, and an interrupt service routine preamble is coded in ARM program code to cause a switch to THUMB program execution. The interrupt service routine preamble is shared amongst all the interrupt service routines to further economize on program code space.

Abstract: According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: Disclosed herein is a method and apparatus for handling an asynchronous interrupt while emulating software so that the system is in a known state when the interrupt is handled. The method includes suspending the asynchronous interrupt so that it remains pending without interrupting software execution when it arrives, then synchronizing delivery of the interrupt to an instruction by issuing an exception. The instructions which trigger exceptions are inserted in the native code at locations corresponding to original instruction boundaries.

Abstract: A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the computer subsystem comprises a system CPU, a digital-audio generating circuit, a digital computer bus coupling the CPU and the digital-audio generator circuit, and a digital computer bus controller. The CD audio subsystem comprises an audio device capable of playing an audio CD and coupled to the digital computer bus controller, an audio amplifier circuit coupled to the audio device, and an audio interface coupled to the digital computer bus in parallel to the digital computer bus controller and the audio device. The audio interface is adapted to generate signals to operate the audio device and play the audio CD when power is not being supplied to the computer subsystem or to the CPU.

Abstract: A system and technique provides fast acknowledgement and servicing of interrupt sources coupled to a high latency path of an intermediate node of a computer network. An external device coupled to the high latency path is provided with a separate interrupt signal for each type of interrupt supported by a processor of the intermediate node. Each interrupt signal is directly fed to an interrupt multiplexing device over a first low latency path. The multiplexing device is accessible to the processor through a second low latency path. The external device asserts an interrupt by “pulsing” an appropriate interrupt signal to the multiplexing device. The multiplexing device maintains a current counter for each interrupt signal and increments that counter every time an interrupt pulse is detected. In addition to the counter, the multiplexing device maintains a status bit for each interrupt.

Abstract: In a programmable controller which executes a user program process, an I/O refresh process and a peripheral service process by using a same microprocessor, the cyclic execution of the peripheral service process by a prescribed amount is ensured so as to enable a satisfactory data relay function without regard to the time period required for the execution of the user program process. The user program process which is being executed by the normal process means is interrupted by the peripheral service process which is executed by a prescribed amount according to an interruption procedure every time an interruption trigger is generated.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: A method and system that enables executable content in the form of one or more software drivers or firmware volumes to be loaded into the System Management Mode (SMM) of a microprocessor or the native mode of an Itanium-based processor. The mechanism allows for multiple drivers, possibly written by different parties, to be installed for these operations. An agent that registers event handlers provided by the drivers runs in the EFI boot-services mode and is composed of a CPU-specific component that binds the drivers and a platform component that abstracts chipset control of the xMI (PMI or SMI) signals corresponding to an event triggering condition. Accordingly, the functionality of the SMM mode of various processors and the native mode of Itanium processors can be extended through add-on drivers written by parties other than the OEM from the computer system or the BIOS vendor for the system.

Abstract: Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW utilization, and power control of VLIW-based vector processing using the ManArray register file indexing mechanism. These techniques are applicable to all processing elements (PEs) and the array controller sequence processor (SP) to provide substantial power savings.

Abstract: An interrupt signal processing apparatus, when receiving an interrupt requesting signal from one device, writes a pulse signal generated by an interrupt setting pulse generating section to a register. The interrupt signal processing apparatus, when receiving an interrupt clearing request signal from the other device, clears the register by using a pulse signal fed from the interrupt clearing pulse generating section and outputs the interrupt permission signal to the one device. When a clock speed of the other device is lower than that of the one device and when pulse generation is controlled by a control signal fed from the clearing pulse generating section of the other device, while the pulse signal fed from the other device is input to the delay circuit, a time delay is provided to operations of the second synchronization section. Thus, smooth interruption can be implemented regardless of the clock speed.

Abstract: Methods and apparatus for enabling timeouts with arbitrary resolutions to be implemented are disclosed. According to one aspect of the present invention, a method for enabling a device driver to communicate with a processor in a computing system includes exchanging information between the device driver and a clock system, and exchanging information between the clock system and a cyclic system. Information is also exchanged between the cyclic system and the processor. Although the clock system indirectly exchanges information with the processor, the clock system does not directly exchange information with the processor. In one embodiment, the clock system includes a callout system and a system clock, and exchanging information between the device driver and the clock system includes exchanging information between the system clock and the callout system, and exchanging information between the callout system and the device driver.

Abstract: An interrupt and status reporting method and structure for a timeslot bus communications protocol. In one embodiment, a peripheral bus is a timeslot bus configured to transmit information across the bus in frames. Each frame may include at least one timeslot dedicated to reporting interrupt and status information to a host computer system. An interrupt request bit may be transmitted by a peripheral to a peripheral bus host controller, and may signal a request for an interrupt by a peripheral device. The requesting peripheral device may also transmit a cause code, which may include general information about the cause of the interrupt request, and a parameter field, which may include specific information about the cause of the interrupt request. Additionally, a peripheral device may be configured to use the interrupt and status reporting structure to request data to be transmitted to it from a host controller.

Abstract: Mechanisms and techniques operate in a computerized device to execute critical code without interference from interruptions. Critical code is registered for invocation of a critical execution manager in the event of an interruption to the critical code. The critical code is then executed until an interruption to the critical code occurs. After handling the interruption, a critical execution manager is invoked and the critical execution manager detects if an interference signal indicates a reset value. If the interference signal indicates the reset value, the critical execution manager performs a reset operation on the critical code to reset a current state of the critical code to allow execution of the critical code while avoiding interference from handling the interruption and returns to execution of the critical code using the current state of the critical code.

Abstract: Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.

Abstract: Provided are a method, system, and program for handling interrupts. A request is received as to whether a device transmitted an interrupt and a determination is made as to whether the device transmitted the interrupt. If the device transmitted the interrupt, then indication is made that the device did not transmit the interrupt and work from the device related to the interrupt is processed.

Abstract: A system and method for implementing a flexible interrupt mechanism in an electronic system includes a processor that may initially execute an initialization routine for performing an interrupt configuration procedure. The foregoing interrupt configuration procedure may preferably be initiated when the processor programs a configuration register with certain selectable interrupt parameters that may be utilized to flexibly configure an interrupt module in the electronic system. Internal and external interrupt sources may then subsequently provide various interrupts to the configured interrupt module which may responsively detect and route the interrupts to the processor based upon interrupt information provided during the foregoing interrupt configuration procedure. The processor may then effectively service the interrupts during appropriate interrupt servicing procedures by utilizing corresponding interrupt handler routines.

Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt if no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A method for transmitting a data packet is disclosed. First, the size of the data packet is determined. If the size of the data packet is below a predetermined threshold size, then a transmit complete interrupt delay is set to a predetermined time. The packet is transmitted over a network. Finally, upon completing transmission of the data packet, a transmit complete interrupt is sent after waiting the predetermined time.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract: A method of downloading application programs on the editing system platform of an electronic communication apparatus, includes the step of connecting an electronic communication apparatus to the Internet, the step of driving an editing system of a processor of the electronic communication apparatus to define a total area from a memory thereof for use by the application programs to be downloaded from the Internet, for enabling the application programs to be stored in any address within the total area, the step of driving the editing system to directly correct the operating instruction of direct address searching to the correct address when downloading an application program from the Internet and then to search the address after address correction, and the step of using a software interrupt (SWI) to alternate the operating instruction of indirect address searching so as to obtain the desired correct address for the editing system for further indirect address searching operation.

Abstract: An interrupt request controller for processing a plurality of interrupt logic signals. The controller includes: a programmable bit masking section fed by the interrupt logic signals, adapted to mask selected ones of the interrupt signals; a interrupt priority section fed by the programmable mask section for coupling unmasked ones of the interrupt signals to a plurality of outputs selectively in accordance with a predetermined priority criteria. The request controller includes: a programmable section fed by the interrupt signals, for selecting assertion sense and/or assertion type of each one of the interrupt signals. The programmable section stores a bit for each one of the interrupt logic signals representative of whether the logic state of the interrupt logic signal should be, or should not be, inverted and for producing a corresponding output logic interrupt signal in accordance therewith.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: A computer subsystem of a computer includes a CPU, RAM, display, storage device, input device(s), and a digital-audio generating IC. A CD-ROM subsystem of the computer includes a CD-ROM drive and CD-ROM control buttons for controlling CD-ROM drivers operation while playing audio CDs. An audio-interface IC of the CD-ROM subsystem couples a bus of the computer subsystem to the CD-ROM drive, and to the control buttons. The audio-interface IC, in one operating mode, relays commands and data between the bus and the CD-ROM drive. A second operating mode permits turning the computer subsystem off while the audio-interface IC autonomously responds to the control buttons and transmits commands to the CD-ROM drive for playing an audio CD.

Abstract: A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter. If the number of input interrupt lines is greater than the number of output lines, then interrupt sharing is necessary. The number of input interrupt lines can be determined automatically by scanning all the card slots or can be determined by values stored in lookup tables. The algorithm to determine a logical mapping of the input interrupt lines to the output lines, in cases where interrupt sharing is required, can be based on a number of factors. A simple approach is to distribute the interrupts as equally as possible. Another algorithm may take into account the expected frequency of interrupts based on the device involved. Yet another approach may use a set of predetermined priorities. Since these algorithms are implemented in firmware or software, they can be changed to meet a particular set of needs.

Abstract: A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.

Abstract: A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing special cluster manager devices that can convert “N” serial messages received from a local APIC to “M” parallel messages, wherein M is less than N. The special cluster manager device then transfers the “M” parallel messages to a receiving cluster manager device. The receiving cluster manager device converts the “M” parallel messages into the original “N” serial messages, and sends the “N” serial messages to the appropriate local APIC within the receiving cluster.

Abstract: A method, computer program product and computer system that features intermittently entering the system management mode of a processor to commence and terminate I/O activity between external devices and computer system resources. To that end, a system management interrupt handler is included that monitors bus transactions between a bus controller and an external device that is the subject of I/O activity. Upon sensing the completion of a bus transaction, the system management interrupt handler transmits a system management interrupt to the processor. In response thereto, the processor reads a buffer in the bus controller and provides the requisite resources with the I/O information contained therein.

Abstract: According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.

Abstract: A method and apparatus for reducing the disk drive data transfer interrupt service latency penalty is described. The method comprises beginning a data transfer between a disk drive and a host system, issuing an interrupt before the transfer is complete, and then completing the data transfer. This method may be implemented on a computer assembly that includes a processor, an input/output controller, and a scatter/gather list, which is stored in memory, that includes an entry that will cause the input/output controller to generate the interrupt.

Abstract: A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI bus. The multiplexer enables the user to dynamically select which address line is routed to the IDSEL pin on the PCI device. According to the PCI specification, the address line connected to the IDSEL pin determines the Device ID for that PCI device. In turn, the Device ID establishes which of the four available interrupt INT# lines are assigned to that PCI device. Thus, the interrupt INT# line assignments can be dynamically controlled. Where desired, the user can force two PCI devices to share an interrupt line, or the user can force the devices to use separate interrupts.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: A dynamic early indication system for a computer includes a processor subsystem logic that performs a subsystem function, an early indicator, indication logic, and a driver that is executed by the processor in response to an indication to perform processing. The indication logic may be coupled to the subsystem logic and early indicator to provide an indication that informs the processor when processing associated with the subsystem function is needed at a completion time of the subsystem function. The indication may be provided before the completion time of the subsystem function if the early indicator represents early indication. The driver controls the early indicator to improve efficiency of subsystem processing.

Abstract: A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt.