Processor Status Patents (Class 710/267)
  • Patent number: 10740030
    Abstract: An indication is made for each task category of a plurality of task categories, of a first attribute that indicates a data set to be collected, a second attribute that indicates a first predetermined amount of time within which a central processing unit (CPU) stops executing a task of the task category, and a third attribute that indicates a second predetermined amount of time within which the CPU that was executing the task of the task category collects the data set. In response to occurrence of an event, a plurality of CPUs are stopped to collect a plurality of data sets, based on first attributes, second attributes, and third attributes of task categories corresponding to tasks executing on the plurality of CPUs.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Trung N. Nguyen, Louis A. Rasor, Juan J. Ruiz
  • Patent number: 10691562
    Abstract: Aspects of the disclosure relate to management node failover systems and methods. The system includes two management devices and a detection and reversal device. Each of the two management devices has a processor and a non-volatile memory storing computer executable code. The two management devices function respectively as an active node and a passive node. The detection and reversal device monitors status of the active node. When the active node fails, the detection and reversal device sends an activation signal to the passive node. The passive node, in response to receiving the active signal, switches from the passive node to the active node.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 23, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Anurag Bhatia, Samvinesh Christopher, Winston Thangapandian
  • Patent number: 10649935
    Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Derek R. Kumar, Joshua Phillips de Cesare
  • Patent number: 10620969
    Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Avinash N. Ananthakrishnan, Eugene Gorbatov, Russell Fenger, Ashok Raj, Kameswar Subramaniam
  • Patent number: 10579584
    Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 3, 2020
    Assignee: PACT XPP SCHWEIZ AG
    Inventors: Martin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May
  • Patent number: 10334521
    Abstract: An information processing device includes a wireless communication unit, a main system, and a subsystem. The information processing device is enabled to selectively execute a ready mode in which at least the main system in its entirety is activated, and a sleep mode in which at least a portion of the main system is not activated. When the information processing device transitions from the ready mode to the sleep mode, if the main system determines that the main system is connected to the wireless network and that peer-to-peer networking is ineffective, the main system carries out configuring of the subsystem to enable the subsystem to respond to the external device via the wireless communication unit during the sleep mode, and the main system transitions to, as the sleep mode, a first sleep mode in which the subsystem is activated without the main system in its entirety being activated.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: June 25, 2019
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Koji Sasadai
  • Patent number: 10310936
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 10289188
    Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Henrietta Bezbroz
  • Patent number: 10152438
    Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 11, 2018
    Assignee: Apple Inc.
    Inventors: Derek R. Kumar, Joshua Phillips de Cesare
  • Patent number: 10120805
    Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
  • Patent number: 10089263
    Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Thiam Wah Loh, Gautham N. Chinya, Per Hammarlund, Reza Fortas, Hong Wang, Huajin Sun
  • Patent number: 10082852
    Abstract: A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 25, 2018
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 10041998
    Abstract: Disclosed embodiments include a method of using a general-purpose microprocessor to debug a programmable logic controller. In some embodiments, the method includes: at a MPU of the PLC, backing up identification information and file information of an interrupt step of steps comprised in a user's program and substituting the interrupt step with an exceptional interrupt code to set the interrupt step for the debugging; and at the MPU of the PLC, interrupting the driving of the PLC at a step including the exceptional interrupt code in executing the user's program step by step while driving the PLC.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 7, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Kang-Hee Park
  • Patent number: 9904575
    Abstract: A method and apparatus of a device that rate-limits the execution of a timer is described. The device receives a timer that includes an initial execution timer and a timer priority. If the timer priority is low, the device rate-limits the execution of the timer based on a suppression period associated with the timer priority. In order to rate-limit the execution of the timer, the device determines the suppression period based on the timer priority and schedules the timer to execute at the end of the suppression period. The device further schedules the timer to execute at the initial exertion time when the timer priority is high.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 27, 2018
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 9864857
    Abstract: A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive information. The method also includes executing, by the device, a first application on the first virtual machine. The method further includes determining, by the device, whether execution of an instruction associated with a second virtual machine would result in a fault. The method also includes, in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction and allowing the second virtual machine to fail without adversely affecting the first virtual machine.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 9, 2018
    Assignee: AT&T MOBILITY II LC
    Inventors: Gustavo De Los Reyes, Micheal Horton, Sanjay Macwan
  • Patent number: 9841993
    Abstract: A problem with conventional art is that, in an environment wherein a plurality of interrupts having different priorities for processing occur in an overlapping manner from external devices, responding to high-priority interrupts while ensuring execution intervals of periodic tasks has been difficult. A partition execution control device according to the present invention comprises: a first management table which stores, for each partition, initial time slices, remaining time slices, execution priorities, execution states, and an interrupt disable level for suppressing the interrupts from the external devices; and a second management table which stores the interrupt priorities of the external devices and partitions to which the interrupts are to be output.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 12, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Satoshi Oshima
  • Patent number: 9811338
    Abstract: In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Jason W. Brandt, Robert Valentine
  • Patent number: 9747138
    Abstract: An information processing device comprising a processor that selects, from among a plurality of data processing section that subject data blocks to a predetermined process, a data processing section to which a first data block group with first identification information based on the data blocks is allocated, and divides, when a workload placed on the data processing section exceeds a first threshold, the first data block group allocated to the data processing section into a plurality of second data block groups with second identification information based on the data blocks, and selects, from among the plurality of data processing sections, data processing sections to which the plurality of second data block groups are allocated.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Miwa, Hironori Nishino, Makoto Yamaguchi
  • Patent number: 9575836
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9569383
    Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: February 14, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: Matthew L. Domsch, Hendrich M. Hernandez, Robert L. Winter, Shawn J. Dube
  • Patent number: 9537692
    Abstract: The invention relates to an automation device, in which a plurality of spatially distributed functional units communicate with one another by means of a common transmission protocol. The device has a microcontroller (110) which has at least one associated clock generator (120) and a memory unit (150) and which is connected at least to a data source (140), which is designed to output a data byte stream to be transmitted. A first program for conversion of a data byte stream to be transmitted to a sequence of sample values of an adequate frequency-modulated line signal, and a second program for identification of a frequency-modulated line signal and for its sequential conversion to a received data byte stream are stored in the memory unit (150), with these programs being associated with the microcontroller (110). The first and the second program can be run alternately.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: January 3, 2017
    Assignee: ABB PATENT GMBH
    Inventors: Heiko Kresse, Andreas Stelter, Ralf Schaeffer
  • Patent number: 9513923
    Abstract: One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver to store the current PPU context of a calling thread on a PPU context stack and to associate a named PPU context with the calling thread. The second operator is a PPU context pop, which causes the PPU driver to restore the PPU context of a calling function to the PPU context at the top of the PPU context stack. By performing a PPU context push at the beginning of a function and a PPU context pop prior to returning from the function, the function may execute within a single CPU thread, but operate on a two distinct PPU contexts.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 6, 2016
    Assignee: NVIDIA Corporation
    Inventor: Nicholas Patrick Wilt
  • Patent number: 9507659
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9436634
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 6, 2016
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 9384156
    Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: July 5, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Nhon Quach, Stephen Z. Au, Thomas Zou, Tracy Sharpe
  • Patent number: 9367374
    Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 14, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Jonathan L. Kaus, Adam C. Lange-Pearson, Gary R. Ricard, Jaimeson Saley
  • Patent number: 9354890
    Abstract: In one or more embodiments, system(s), method(s), integrated circuit(s), physical layer(s), apparatus(es), System-on-Chip (SoC), various other hardware, computer-readable and/or executable instructions, and/or technique(s) are described that enable a subroutine to release control of a processing entity when the subroutine is incomplete. By so doing, the processing entity may be used by code outside of the subroutine, such as code that needs attention, and/or more-fully utilize its own processing power by being less idle.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 31, 2016
    Assignee: Marvell International Ltd.
    Inventor: Xinhai Kang
  • Patent number: 9329891
    Abstract: In a communication apparatus, a communication processor rebuilds, with switching of communication systems, a communication bearer to perform communication. An application processor outputs, when background communication occurs or a display unit is shifted from an off state to an on state while notification from the communication processor is stopped, a request signal to the communication processor. The application processor starts the background communication based on information of a latest communication bearer output from the communication processor in response to the request signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 3, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hitoshi Oshino, Makoto Shinohara
  • Patent number: 9323528
    Abstract: Described herein are mechanisms for creating, executing, and terminating mini-threads. A processor executes instructions with a primary thread in a first execution mode, and to execute an instruction to create a secondary mini-thread that is associated with a first subset of registers and associates the primary thread with a second subset of the registers during a second execution mode. During the second execution mode, the primary thread operates as a primary mini-thread.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 9235538
    Abstract: Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 12, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Avi Kivity
  • Publication number: 20150149676
    Abstract: A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures.
    Type: Application
    Filed: May 11, 2013
    Publication date: May 28, 2015
    Inventors: Indrajith Kuruppu, Don Damith Nadishan Colambathanthrige
  • Patent number: 9043520
    Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9043521
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Publication number: 20150143089
    Abstract: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU cores continue operating in normal mode. Further, a multi-threaded SMM environment and mutual exclusion objects (mutexes) may allow guarding of key hardware resources and software data structures to enable individual CPU cores among the remaining CPU cores to subsequently also enter SMM in response to a different SMI while the originally selected CPU core is still in SMM.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Timothy Andrew LEWIS, Kevin Dale DAVIS
  • Publication number: 20150134867
    Abstract: An external logic device for a network interface controller enables interrupt coalescing from a network interface controller. The network interface controller has a cause register for storing information about interrupt causes and drives an interrupt line. The external logic device is connectable to the cause register for reading the contents of the cause register, and to the interrupt line of the network interface controller and to an interrupt input of a processor for forwarding interrupts from the interrupt line of the network interface controller to the processor. The external logic device has a timer which is initializable when the interrupt line contains an interrupt, and is constructed to delay the forwarding of interrupts, depending on the current contents of the cause register, until a timeout of the timer is reached.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 14, 2015
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Christian HILDNER
  • Patent number: 9026704
    Abstract: A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 5, 2015
    Assignee: LSI Corporation
    Inventors: Shankar T. More, Vidyadhar C. Pinglikar, Prasad Ramchandra Kadam
  • Publication number: 20150120978
    Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Liang Chen, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien, Yaniv Adiri
  • Publication number: 20150113191
    Abstract: Embodiments include methods, systems and computer program products that include executing a begin transaction instruction to begin a transaction comprising a sequence of instructions, wherein the begin transaction instruction indicates that a resource will be accessed by the first processing device. Embodiments also include determining whether it is safe for the first processing device to access the resource. Based on a determination that it is safe for the first processing device to access the resource, embodiments include processing the sequence of instructions of the transaction. Based on a determination that the sequence of instructions of the transaction has been completed, embodiments include executing an end transaction instruction, wherein the end transaction instruction indicates that the first processing device has completed its access of the resource. Based on a determination that it is not safe for the first processing device to access the resource, embodiments include aborting the transaction.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: James H. Mulder, Peter J. Relson
  • Publication number: 20150113192
    Abstract: A method and a system for processing a data conflict are provided that relate to the field of signal interface technologies of an integrated circuit, where the method includes sending a power management bus (PMBus) command to a slave device by using a PMBus, so as to perform power management; when the PMBus command fails to be sent, determining whether the number of times that the PMBus command fails to be sent is greater than or equal to a preset value, where the preset value is configured in advance during system initialization; starting timing if the number of times that the PMBus command fails to be sent is less than the preset value; and resending the PMBus command when timing duration reaches resending time. The present invention is applicable to a scenario in which multiple master devices (Masters) send the PMBus command by using the PMBus.
    Type: Application
    Filed: December 26, 2014
    Publication date: April 23, 2015
    Inventors: Qian Xie, Xinru Wang, Guoxin Yang
  • Publication number: 20150113193
    Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
    Type: Application
    Filed: January 6, 2015
    Publication date: April 23, 2015
    Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
  • Patent number: 9015397
    Abstract: A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: April 21, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Tal Sharifie, Shay Benisty, Yair Baram
  • Patent number: 9009377
    Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventors: Erik P Machnicki, Deniz Balkan, Manu Gulati
  • Publication number: 20150067218
    Abstract: A series of processing that includes a first control step for controlling an apparatus that executes predetermined processing and a second control step for controlling the apparatus based on a control result of the first control step is executed. An execution history of the first control step or the second control step is stored in a memory. The series of processing is interrupted in a case where a predetermined interruption factor occurs during execution of the series of processing. In a case where the interruption is executed, a start step for resuming the series of processing is set to the first control step or the second control step, based on the execution history stored in the memory.
    Type: Application
    Filed: August 7, 2014
    Publication date: March 5, 2015
    Inventor: Hideyuki Kanamori
  • Patent number: 8959382
    Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 17, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Gabriel Vogel
  • Patent number: 8959270
    Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: February 17, 2015
    Assignee: Apple Inc.
    Inventors: Josh P. de Cesare, Ruchi Wadhawan, Erik P. Machnicki, Mark D. Hayter
  • Publication number: 20150046620
    Abstract: A computing apparatus identifies that a first processor of a host has forwarded information for a device to a second processor that controls the device. After identifying that the first processor has forwarded the information to the second processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus causes future information for the device to be forwarded to the second processor.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventors: Michael S. Tsirkin, Avi Kivity
  • Publication number: 20150046618
    Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.
    Type: Application
    Filed: September 18, 2014
    Publication date: February 12, 2015
    Inventors: Matthew L. Domsch, Hendrich M. Hernandez, Robert L. Winter, Shawn J. Dube
  • Publication number: 20150046619
    Abstract: The present invention aims to provide a host controller apparatus, an information processing apparatus, and an event information output method that are capable of outputting event information to a system memory while achieving power saving. A host controller apparatus according to the present invention includes: an event controller that outputs occurred event information to a system memory; and an interruption controller that outputs an interrupt signal to a CPU executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory. The event controller outputs the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the CPU.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Applicant: Renesas Electronics Corporation
    Inventor: Mitsuru FUJII
  • Patent number: 8943252
    Abstract: Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: January 27, 2015
    Assignee: Microsoft Corporation
    Inventors: Bradley M. Waters, Danyu Zhu
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles