Processor Status Patents (Class 710/267)
  • Patent number: 11188369
    Abstract: Apparatuses, methods, program products, and systems are presented for interrupt virtualization. An apparatus includes an adapter module that detects a switch from a first physical input/output (“I/O”) adapter associated with a logical partition to a second physical I/O adapter associated with the logical partition. The apparatus includes an interrupt module that updates one or more I/O interrupt management structures for the logical partition so that the logical partition receives I/O interrupt information from the second physical I/O adapter and not the first physical I/O adapter without the logical partition being aware of the switch to the second I/O adapter. The apparatus includes an abstraction module that updates physical device information at a hypervisor for the logical partition to reflect the switch to the second physical I/O device.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jesse Arroyo, Prathima Kommineni, Timothy Schimke, Vinod Bussa
  • Patent number: 11144490
    Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: October 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Sandeep Kumar, Suman Kumar
  • Patent number: 11113217
    Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh M. Sankaran
  • Patent number: 11080088
    Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Arumugam Thiyagarajah, Rajesh Sankaran, Dharmendra Thakkar
  • Patent number: 11080087
    Abstract: A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
  • Patent number: 11074101
    Abstract: Embodiments include method, systems and computer program products for switching between interrupt context input/output I/O processing versus thread context I/O processing. The method includes receiving, by a processor of a plurality of processors, an interrupt. A device driver for an I/O adapter determines that the dispatch latency for an associated kernel thread is greater than a first predetermined threshold. An adapter switches to an interrupt context mode. The adapter processes an I/O on the processor associated with the received interrupt to completion.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mathew Accapadi, Chad Collie, Vani D. Ramagiri, Lloyd Phillips, Anil Kalavakolanu, Teresa Hong Pham
  • Patent number: 10949367
    Abstract: A method for handling kernel services for interrupt routines in a multi-core processor in an electronic device. The method comprises receiving a first interrupt on a first core of the multi-core processor, wherein the first interrupt includes at least one kernel service request and at least one non-kernel service request. The method further determines whether a worker queue of the first core in empty and whether a kernel service lock for the at least one kernel service request is acquired by at least one second core of the multi-core processor, in response to determining that the worker queue of the first core is empty. The method further comprises executing the at least one non-kernel service request of the first interrupt on the first core. The pending kernel service request are queued in the worker queue based on whether worker queue is empty or not and availability of kernel lock.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Anup Manohar Kaveri, Nischal Jain, Rohit Kumar Saraf, Samarth Varshney, Shwetang Singh, Vinayak Hanagandi, Srinivasa Rao Kola, Younjo Oh
  • Patent number: 10922402
    Abstract: In a computer system operable at more than one privilege level, an interrupt security module handles interrupts without exposing a secret value of a register to virtual interrupt handling code that executes at a lower privilege level than the interrupt security module. The interrupt security module is configured to intercept interrupts generated while executing code at lower privilege levels. Upon receiving such an interrupt, the interrupt security module overwrites the secret value of the register with an unrelated constant. Subsequently, the interrupt security module generates a virtual interrupt corresponding to the interrupt and forwards the virtual interrupt to the virtual interrupt handling code. Advantageously, although the virtual interrupt handling code is able to determine the value of the register and consequently the unrelated constant, the virtual interrupt handling code is unable to determine the secret value.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: February 16, 2021
    Assignee: VMware, Inc.
    Inventors: Wei Xu, Alok Nemchand Kataria, Rakesh Agarwal, Martim Carbone
  • Patent number: 10922253
    Abstract: Disclosed are various embodiments for software-based interrupt remapping. A memory address for a respective interrupt request of the peripheral device is allocated. The peripheral device is then configured to write to the memory address to raise an interrupt with the processor. Later, it can be determined that the peripheral device has attempted to write to the memory address. In response, an interrupt can be raised for the respective interrupt request with the processor of the computing device on behalf of the peripheral device.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 16, 2021
    Assignee: VMWARE, INC.
    Inventors: Regis Duchesne, Alexander Fainkichen, Cyprien Laplace, Ye Li, Andrei Warkentin
  • Patent number: 10894318
    Abstract: A method for controlling an industrial robot are disclosed, wherein the method is performed by a robot controller system, the robot controller system includes a local part connected to an industrial robot and a remote cloud part connectable to the local part. The local part includes a first real-time partition and a second non-real-time partition, and the method includes the steps of: storing a local cache of a complete file system of the robot controller system in the second non-real-time partition; storing the complete file system in the remote cloud part; and controlling the industrial robot in real time from the first real-time partition.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 19, 2021
    Assignee: ABB Schweiz AG
    Inventor: Roger Kulläng
  • Patent number: 10817182
    Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 27, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 10810048
    Abstract: Systems and methods for dynamic allocation of compilation machines are disclosed. A method includes: initiating and storing a task to be compiled and marking the task in a waiting state to wait for compilation of a compilation machine; fetching a compile command, and analyzing a current compile state of the compilation machine and further determining based on the current compile state whether to set the task to be compiled to continue waiting for compilation or enter a compile stage, wherein if to continue waiting for compilation, then the task to be compiled may be further held in storage; otherwise if to enter the compile stage, then the task may be transmitted to the compilation machine for compilation. Thus, the tasks can be automatically assigned to the compilation machines to achieve efficient use of the compilation machines and reduce the otherwise potential error rate due to human intervention.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 20, 2020
    Assignee: HUIZHOU TCL MOBILE COMMUNICATION CO., LTD
    Inventors: Fan Yang, Qiujuan Xie, Enli Xiang, Julan Chen, Jiaqiong Feng
  • Patent number: 10740030
    Abstract: An indication is made for each task category of a plurality of task categories, of a first attribute that indicates a data set to be collected, a second attribute that indicates a first predetermined amount of time within which a central processing unit (CPU) stops executing a task of the task category, and a third attribute that indicates a second predetermined amount of time within which the CPU that was executing the task of the task category collects the data set. In response to occurrence of an event, a plurality of CPUs are stopped to collect a plurality of data sets, based on first attributes, second attributes, and third attributes of task categories corresponding to tasks executing on the plurality of CPUs.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Trung N. Nguyen, Louis A. Rasor, Juan J. Ruiz
  • Patent number: 10691562
    Abstract: Aspects of the disclosure relate to management node failover systems and methods. The system includes two management devices and a detection and reversal device. Each of the two management devices has a processor and a non-volatile memory storing computer executable code. The two management devices function respectively as an active node and a passive node. The detection and reversal device monitors status of the active node. When the active node fails, the detection and reversal device sends an activation signal to the passive node. The passive node, in response to receiving the active signal, switches from the passive node to the active node.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 23, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Anurag Bhatia, Samvinesh Christopher, Winston Thangapandian
  • Patent number: 10649935
    Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 12, 2020
    Assignee: Apple Inc.
    Inventors: Derek R. Kumar, Joshua Phillips de Cesare
  • Patent number: 10620969
    Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Avinash N. Ananthakrishnan, Eugene Gorbatov, Russell Fenger, Ashok Raj, Kameswar Subramaniam
  • Patent number: 10579584
    Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: March 3, 2020
    Assignee: PACT XPP SCHWEIZ AG
    Inventors: Martin Vorbach, Jürgen Becker, Markus Weinhardt, Volker Baumgarte, Frank May
  • Patent number: 10334521
    Abstract: An information processing device includes a wireless communication unit, a main system, and a subsystem. The information processing device is enabled to selectively execute a ready mode in which at least the main system in its entirety is activated, and a sleep mode in which at least a portion of the main system is not activated. When the information processing device transitions from the ready mode to the sleep mode, if the main system determines that the main system is connected to the wireless network and that peer-to-peer networking is ineffective, the main system carries out configuring of the subsystem to enable the subsystem to respond to the external device via the wireless communication unit during the sleep mode, and the main system transitions to, as the sleep mode, a first sleep mode in which the subsystem is activated without the main system in its entirety being activated.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: June 25, 2019
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Koji Sasadai
  • Patent number: 10310936
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 10289188
    Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Henrietta Bezbroz
  • Patent number: 10152438
    Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 11, 2018
    Assignee: Apple Inc.
    Inventors: Derek R. Kumar, Joshua Phillips de Cesare
  • Patent number: 10120805
    Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
  • Patent number: 10089263
    Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Thiam Wah Loh, Gautham N. Chinya, Per Hammarlund, Reza Fortas, Hong Wang, Huajin Sun
  • Patent number: 10082852
    Abstract: A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: September 25, 2018
    Assignee: SILICON MOTION, INC.
    Inventor: Jiyun-Wei Lin
  • Patent number: 10041998
    Abstract: Disclosed embodiments include a method of using a general-purpose microprocessor to debug a programmable logic controller. In some embodiments, the method includes: at a MPU of the PLC, backing up identification information and file information of an interrupt step of steps comprised in a user's program and substituting the interrupt step with an exceptional interrupt code to set the interrupt step for the debugging; and at the MPU of the PLC, interrupting the driving of the PLC at a step including the exceptional interrupt code in executing the user's program step by step while driving the PLC.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 7, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Kang-Hee Park
  • Patent number: 9904575
    Abstract: A method and apparatus of a device that rate-limits the execution of a timer is described. The device receives a timer that includes an initial execution timer and a timer priority. If the timer priority is low, the device rate-limits the execution of the timer based on a suppression period associated with the timer priority. In order to rate-limit the execution of the timer, the device determines the suppression period based on the timer priority and schedules the timer to execute at the end of the suppression period. The device further schedules the timer to execute at the initial exertion time when the timer priority is high.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 27, 2018
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 9864857
    Abstract: A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive information. The method also includes executing, by the device, a first application on the first virtual machine. The method further includes determining, by the device, whether execution of an instruction associated with a second virtual machine would result in a fault. The method also includes, in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction and allowing the second virtual machine to fail without adversely affecting the first virtual machine.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: January 9, 2018
    Assignee: AT&T MOBILITY II LC
    Inventors: Gustavo De Los Reyes, Micheal Horton, Sanjay Macwan
  • Patent number: 9841993
    Abstract: A problem with conventional art is that, in an environment wherein a plurality of interrupts having different priorities for processing occur in an overlapping manner from external devices, responding to high-priority interrupts while ensuring execution intervals of periodic tasks has been difficult. A partition execution control device according to the present invention comprises: a first management table which stores, for each partition, initial time slices, remaining time slices, execution priorities, execution states, and an interrupt disable level for suppressing the interrupts from the external devices; and a second management table which stores the interrupt priorities of the external devices and partitions to which the interrupts are to be output.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 12, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Satoshi Oshima
  • Patent number: 9811338
    Abstract: In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Jason W. Brandt, Robert Valentine
  • Patent number: 9747138
    Abstract: An information processing device comprising a processor that selects, from among a plurality of data processing section that subject data blocks to a predetermined process, a data processing section to which a first data block group with first identification information based on the data blocks is allocated, and divides, when a workload placed on the data processing section exceeds a first threshold, the first data block group allocated to the data processing section into a plurality of second data block groups with second identification information based on the data blocks, and selects, from among the plurality of data processing sections, data processing sections to which the plurality of second data block groups are allocated.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuta Miwa, Hironori Nishino, Makoto Yamaguchi
  • Patent number: 9575836
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9569383
    Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: February 14, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: Matthew L. Domsch, Hendrich M. Hernandez, Robert L. Winter, Shawn J. Dube
  • Patent number: 9537692
    Abstract: The invention relates to an automation device, in which a plurality of spatially distributed functional units communicate with one another by means of a common transmission protocol. The device has a microcontroller (110) which has at least one associated clock generator (120) and a memory unit (150) and which is connected at least to a data source (140), which is designed to output a data byte stream to be transmitted. A first program for conversion of a data byte stream to be transmitted to a sequence of sample values of an adequate frequency-modulated line signal, and a second program for identification of a frequency-modulated line signal and for its sequential conversion to a received data byte stream are stored in the memory unit (150), with these programs being associated with the microcontroller (110). The first and the second program can be run alternately.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: January 3, 2017
    Assignee: ABB PATENT GMBH
    Inventors: Heiko Kresse, Andreas Stelter, Ralf Schaeffer
  • Patent number: 9513923
    Abstract: One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver to store the current PPU context of a calling thread on a PPU context stack and to associate a named PPU context with the calling thread. The second operator is a PPU context pop, which causes the PPU driver to restore the PPU context of a calling function to the PPU context at the top of the PPU context stack. By performing a PPU context push at the beginning of a function and a PPU context pop prior to returning from the function, the function may execute within a single CPU thread, but operate on a two distinct PPU contexts.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 6, 2016
    Assignee: NVIDIA Corporation
    Inventor: Nicholas Patrick Wilt
  • Patent number: 9507659
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9436634
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 6, 2016
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Patent number: 9384156
    Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: July 5, 2016
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Nhon Quach, Stephen Z. Au, Thomas Zou, Tracy Sharpe
  • Patent number: 9367374
    Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: June 14, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Jonathan L. Kaus, Adam C. Lange-Pearson, Gary R. Ricard, Jaimeson Saley
  • Patent number: 9354890
    Abstract: In one or more embodiments, system(s), method(s), integrated circuit(s), physical layer(s), apparatus(es), System-on-Chip (SoC), various other hardware, computer-readable and/or executable instructions, and/or technique(s) are described that enable a subroutine to release control of a processing entity when the subroutine is incomplete. By so doing, the processing entity may be used by code outside of the subroutine, such as code that needs attention, and/or more-fully utilize its own processing power by being less idle.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: May 31, 2016
    Assignee: Marvell International Ltd.
    Inventor: Xinhai Kang
  • Patent number: 9329891
    Abstract: In a communication apparatus, a communication processor rebuilds, with switching of communication systems, a communication bearer to perform communication. An application processor outputs, when background communication occurs or a display unit is shifted from an off state to an on state while notification from the communication processor is stopped, a request signal to the communication processor. The application processor starts the background communication based on information of a latest communication bearer output from the communication processor in response to the request signal.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 3, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hitoshi Oshino, Makoto Shinohara
  • Patent number: 9323528
    Abstract: Described herein are mechanisms for creating, executing, and terminating mini-threads. A processor executes instructions with a primary thread in a first execution mode, and to execute an instruction to create a secondary mini-thread that is associated with a first subset of registers and associates the primary thread with a second subset of the registers during a second execution mode. During the second execution mode, the primary thread operates as a primary mini-thread.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 9235538
    Abstract: Systems and methods for injecting interrupts in a virtualized computer system. An example method may comprise providing a data structure associating message destination addresses and virtual processor identifiers for a plurality of interrupt destination modes, receiving an interrupt message including a message destination address, looking up the message destination address in the data structure, and forwarding the interrupt message to a virtual processor associated by the data structure with the message destination address.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 12, 2016
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Avi Kivity
  • Publication number: 20150149676
    Abstract: A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures.
    Type: Application
    Filed: May 11, 2013
    Publication date: May 28, 2015
    Inventors: Indrajith Kuruppu, Don Damith Nadishan Colambathanthrige
  • Patent number: 9043521
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Patent number: 9043520
    Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150143089
    Abstract: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU cores continue operating in normal mode. Further, a multi-threaded SMM environment and mutual exclusion objects (mutexes) may allow guarding of key hardware resources and software data structures to enable individual CPU cores among the remaining CPU cores to subsequently also enter SMM in response to a different SMI while the originally selected CPU core is still in SMM.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Timothy Andrew LEWIS, Kevin Dale DAVIS
  • Publication number: 20150134867
    Abstract: An external logic device for a network interface controller enables interrupt coalescing from a network interface controller. The network interface controller has a cause register for storing information about interrupt causes and drives an interrupt line. The external logic device is connectable to the cause register for reading the contents of the cause register, and to the interrupt line of the network interface controller and to an interrupt input of a processor for forwarding interrupts from the interrupt line of the network interface controller to the processor. The external logic device has a timer which is initializable when the interrupt line contains an interrupt, and is constructed to delay the forwarding of interrupts, depending on the current contents of the cause register, until a timeout of the timer is reached.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 14, 2015
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Christian HILDNER
  • Patent number: 9026704
    Abstract: A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 5, 2015
    Assignee: LSI Corporation
    Inventors: Shankar T. More, Vidyadhar C. Pinglikar, Prasad Ramchandra Kadam
  • Publication number: 20150120978
    Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Liang Chen, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien, Yaniv Adiri
  • Publication number: 20150113191
    Abstract: Embodiments include methods, systems and computer program products that include executing a begin transaction instruction to begin a transaction comprising a sequence of instructions, wherein the begin transaction instruction indicates that a resource will be accessed by the first processing device. Embodiments also include determining whether it is safe for the first processing device to access the resource. Based on a determination that it is safe for the first processing device to access the resource, embodiments include processing the sequence of instructions of the transaction. Based on a determination that the sequence of instructions of the transaction has been completed, embodiments include executing an end transaction instruction, wherein the end transaction instruction indicates that the first processing device has completed its access of the resource. Based on a determination that it is not safe for the first processing device to access the resource, embodiments include aborting the transaction.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: James H. Mulder, Peter J. Relson