Abstract: Aspects relate to limits management for a processor power distribution network. In an aspect, an electronic device has a processor with a processing core that is coupled to a power rail. The power rail is external to the processor. A current sensor is associated with the output of the power rail and configured to produce current sensor readings. A state-space unit is coupled to the current sensor. The state-space unit has a predictive model to apply the current sensor readings to the predictive model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits a current draw of the processing core in response to the current limit.

Abstract: A virtual machine is dispatched and based on the dispatch, a determination is made as to whether a select area of memory expected to be accessible to the virtual machine and used in communication between the virtual machine and an operating system is accessible to the virtual machine. Based on determining that the select area of memory is inaccessible to the virtual machine, virtual machine execution is exited with a select interception code.

Abstract: Individual clock adjustments between electronic devices are typically based around a round-trip time (RTT) measurement of the reference message between initiating and the receiving devices. With increasing expectations of clock synchronization accuracy, as well as widespread use of wireless data networks, the presently disclosed technology provides a dedicated clock synchronization network that yields a fixed delay between hops and within associated devices of a dedicated clock synchronization network. By accounting for the known delays between hops and within associated devices of the dedicated clock synchronization network, better clock synchronization accuracy can be achieved than prior art techniques that estimate latency based on an RTT measurement.

Abstract: A virtualized computing environment is protected from a malicious hypervisor by restricting the hypervisor's access to one or more portions of an event (interrupt or exception) handling pathway of a guest virtual machine, wherein the guest virtual machine includes both a secure layer to manage security for the guest and one or more non-secure layers to handle event processing. The hypervisor is restricted from providing normal exception information to the guest virtual machine (referred to simply as a “guest” herein), and instead is only permitted to provide an event signal to the secure layer of the guest. In response to the event signal, the secure layer of the guest accesses a specified region of memory for the event information, reviews the information, and provides the information to another, non-secure, layer of the guest for processing only if the event information complies with specified security protocols.

Abstract: A data processing system and a method are provided for recognizing a scanned biometric characteristic in the data processing system. The data processing system includes a biometric sensor, a rich execution environment (REE), and a secure element (SE). In one embodiment, during an enrollment operation, a random challenge is applied to scanned data to produce a biometric template that is stored. During subsequent validation operations, the SE determines if user data includes evidence of the random challenge before providing access to a secure application. Evidence of the random challenge indicates the user data was provided by the biometric sensor. In another embodiment, the sensor data is split between the REE and the SE and partially processed in the SE. The described embodiments prevent a replay attack from being conducted in communications between the REE and the SE.

Abstract: Disclosed is an electronic device comprising: a connection circuit configured to provide an electrical connection of an external power supply device; a processor electrically connected to the connection circuit; a memory operatively connected to the processor; and a reset circuit electrically connected to the connection circuit and operatively connected to the processor. The processor is configured to” transmit, to the reset circuit, an interrupt signal during a first time at least partially based on the identification of the connecting to the external power supply device through the connection circuit, and the reset circuit may be configured to: determine whether the interrupt signal is received within a second time after the connecting to the external power supply device through the connection circuit, and transmit, to the processor, a reset signal for a hardware reset of the processor based on the interrupt signal not being received within the second time.

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Abstract: A data processing system and a method are provided for recognizing a scanned biometric characteristic in the data processing system. The data processing system includes a biometric sensor, a rich execution environment (REE), and a secure element (SE). In one embodiment, during an enrollment operation, a random challenge is applied to scanned data to produce a biometric template that is stored. During subsequent validation operations, the SE determines if user data includes evidence of the random challenge before providing access to a secure application. Evidence of the random challenge indicates the user data was provided by the biometric sensor. In another embodiment, the sensor data is split between the REE and the SE and partially processed in the SE. The described embodiments prevent a replay attack from being conducted in communications between the REE and the SE.

Abstract: The present invention finds and defines a problem which possibly exists in an interrupt remapping mechanism under a virtual symmetric multiprocessing environment, i.e., a problem of Interruptability Holder Preemption (IHP). This problem causes the interrupt remapping mechanism to fail and reduces I/O performance of virtual machines. In order to solve the IHP problem, the present invention provides a proactive VCPU comprehensive scheduling method based on interruptability holder information. This method is based on Kernel-Based Virtual Machines (KVMs) which are widely used at present and paravirtualization network models thereof. By globally controlling and analyzing a running state of an interruptability holder and simultaneously considering global scheduling fairness of a system, a VCPU comprehensive scheduling method is established, which can effectively eliminate the IHP problem and obviously improve the I/O performance of the virtual machines.

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Abstract: Apparatuses, methods, program products, and systems are presented for interrupt virtualization. An apparatus includes an adapter module that detects a switch from a first physical input/output (“I/O”) adapter associated with a logical partition to a second physical I/O adapter associated with the logical partition. The apparatus includes an interrupt module that updates one or more I/O interrupt management structures for the logical partition so that the logical partition receives I/O interrupt information from the second physical I/O adapter and not the first physical I/O adapter without the logical partition being aware of the switch to the second I/O adapter. The apparatus includes an abstraction module that updates physical device information at a hypervisor for the logical partition to reflect the switch to the second physical I/O device.

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Abstract: A processor includes a processor core, a processor cache to store reporting data structures including a queue structure, and an interrupt posting circuit coupled to the processor core and the processing cache. The interrupt posting circuit receives an interrupt request directed to a virtual processor (VP) of a virtual machine (VM) executed by the processor core. The VM is managed by a virtual machine monitor (VMM) executed by the processor core. The interrupt posting circuit determines the VP is in an inactive state and records the interrupt request in a first posted data structure allocated by the VMM for the VP in main memory coupled to the processor. The interrupt posting circuit updates location information stored in the reporting data structures based on recording the interrupt request in the first posted data structure to generate updated location information that identifies a location of the interrupt request.

Abstract: A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.

Abstract: Embodiments include method, systems and computer program products for switching between interrupt context input/output I/O processing versus thread context I/O processing. The method includes receiving, by a processor of a plurality of processors, an interrupt. A device driver for an I/O adapter determines that the dispatch latency for an associated kernel thread is greater than a first predetermined threshold. An adapter switches to an interrupt context mode. The adapter processes an I/O on the processor associated with the received interrupt to completion.

Abstract: A method for handling kernel services for interrupt routines in a multi-core processor in an electronic device. The method comprises receiving a first interrupt on a first core of the multi-core processor, wherein the first interrupt includes at least one kernel service request and at least one non-kernel service request. The method further determines whether a worker queue of the first core in empty and whether a kernel service lock for the at least one kernel service request is acquired by at least one second core of the multi-core processor, in response to determining that the worker queue of the first core is empty. The method further comprises executing the at least one non-kernel service request of the first interrupt on the first core. The pending kernel service request are queued in the worker queue based on whether worker queue is empty or not and availability of kernel lock.

Abstract: In a computer system operable at more than one privilege level, an interrupt security module handles interrupts without exposing a secret value of a register to virtual interrupt handling code that executes at a lower privilege level than the interrupt security module. The interrupt security module is configured to intercept interrupts generated while executing code at lower privilege levels. Upon receiving such an interrupt, the interrupt security module overwrites the secret value of the register with an unrelated constant. Subsequently, the interrupt security module generates a virtual interrupt corresponding to the interrupt and forwards the virtual interrupt to the virtual interrupt handling code. Advantageously, although the virtual interrupt handling code is able to determine the value of the register and consequently the unrelated constant, the virtual interrupt handling code is unable to determine the secret value.

Abstract: Disclosed are various embodiments for software-based interrupt remapping. A memory address for a respective interrupt request of the peripheral device is allocated. The peripheral device is then configured to write to the memory address to raise an interrupt with the processor. Later, it can be determined that the peripheral device has attempted to write to the memory address. In response, an interrupt can be raised for the respective interrupt request with the processor of the computing device on behalf of the peripheral device.

Abstract: A method for controlling an industrial robot are disclosed, wherein the method is performed by a robot controller system, the robot controller system includes a local part connected to an industrial robot and a remote cloud part connectable to the local part. The local part includes a first real-time partition and a second non-real-time partition, and the method includes the steps of: storing a local cache of a complete file system of the robot controller system in the second non-real-time partition; storing the complete file system in the remote cloud part; and controlling the industrial robot in real time from the first real-time partition.

Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. Responsive to receiving the interrupt, the host device access the completion queue to access entries placed by the memory device therein. The host device may take a certain amount of time to service the interrupt resulting in host latency. Given knowledge of the host latency, the memory device time the sending of the interrupt so that, given the host latency, the memory device may post the entry to the completion queue in a timely manner.

Abstract: Systems and methods for dynamic allocation of compilation machines are disclosed. A method includes: initiating and storing a task to be compiled and marking the task in a waiting state to wait for compilation of a compilation machine; fetching a compile command, and analyzing a current compile state of the compilation machine and further determining based on the current compile state whether to set the task to be compiled to continue waiting for compilation or enter a compile stage, wherein if to continue waiting for compilation, then the task to be compiled may be further held in storage; otherwise if to enter the compile stage, then the task may be transmitted to the compilation machine for compilation. Thus, the tasks can be automatically assigned to the compilation machines to achieve efficient use of the compilation machines and reduce the otherwise potential error rate due to human intervention.

Abstract: An indication is made for each task category of a plurality of task categories, of a first attribute that indicates a data set to be collected, a second attribute that indicates a first predetermined amount of time within which a central processing unit (CPU) stops executing a task of the task category, and a third attribute that indicates a second predetermined amount of time within which the CPU that was executing the task of the task category collects the data set. In response to occurrence of an event, a plurality of CPUs are stopped to collect a plurality of data sets, based on first attributes, second attributes, and third attributes of task categories corresponding to tasks executing on the plurality of CPUs.

Abstract: Aspects of the disclosure relate to management node failover systems and methods. The system includes two management devices and a detection and reversal device. Each of the two management devices has a processor and a non-volatile memory storing computer executable code. The two management devices function respectively as an active node and a passive node. The detection and reversal device monitors status of the active node. When the active node fails, the detection and reversal device sends an activation signal to the passive node. The passive node, in response to receiving the active signal, switches from the passive node to the active node.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

Abstract: An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Abstract: An information processing device includes a wireless communication unit, a main system, and a subsystem. The information processing device is enabled to selectively execute a ready mode in which at least the main system in its entirety is activated, and a sleep mode in which at least a portion of the main system is not activated. When the information processing device transitions from the ready mode to the sleep mode, if the main system determines that the main system is connected to the wireless network and that peer-to-peer networking is ineffective, the main system carries out configuring of the subsystem to enable the subsystem to respond to the external device via the wireless communication unit during the sleep mode, and the main system transitions to, as the sleep mode, a first sleep mode in which the subsystem is activated without the main system in its entirety being activated.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.

Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

Abstract: A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.

Abstract: Disclosed embodiments include a method of using a general-purpose microprocessor to debug a programmable logic controller. In some embodiments, the method includes: at a MPU of the PLC, backing up identification information and file information of an interrupt step of steps comprised in a user's program and substituting the interrupt step with an exceptional interrupt code to set the interrupt step for the debugging; and at the MPU of the PLC, interrupting the driving of the PLC at a step including the exceptional interrupt code in executing the user's program step by step while driving the PLC.

Abstract: A method and apparatus of a device that rate-limits the execution of a timer is described. The device receives a timer that includes an initial execution timer and a timer priority. If the timer priority is low, the device rate-limits the execution of the timer based on a suppression period associated with the timer priority. In order to rate-limit the execution of the timer, the device determines the suppression period based on the timer priority and schedules the timer to execute at the end of the suppression period. The device further schedules the timer to execute at the initial exertion time when the timer priority is high.

Abstract: A particular method includes receiving authentication information at a device. The method also includes determining, by the device, whether a user is authenticated based on the authentication information. The method further includes executing, by the device, a first virtual machine in response to determining that the user is authenticated. The first virtual machine has access to sensitive information. The method also includes executing, by the device, a first application on the first virtual machine. The method further includes determining, by the device, whether execution of an instruction associated with a second virtual machine would result in a fault. The method also includes, in response to determining that execution of the instruction would result in the fault, preventing execution of the instruction and allowing the second virtual machine to fail without adversely affecting the first virtual machine.

Abstract: A problem with conventional art is that, in an environment wherein a plurality of interrupts having different priorities for processing occur in an overlapping manner from external devices, responding to high-priority interrupts while ensuring execution intervals of periodic tasks has been difficult. A partition execution control device according to the present invention comprises: a first management table which stores, for each partition, initial time slices, remaining time slices, execution priorities, execution states, and an interrupt disable level for suppressing the interrupts from the external devices; and a second management table which stores the interrupt priorities of the external devices and partitions to which the interrupts are to be output.

Abstract: In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.

Abstract: An information processing device comprising a processor that selects, from among a plurality of data processing section that subject data blocks to a predetermined process, a data processing section to which a first data block group with first identification information based on the data blocks is allocated, and divides, when a workload placed on the data processing section exceeds a first threshold, the first data block group allocated to the data processing section into a plurality of second data block groups with second identification information based on the data blocks, and selects, from among the plurality of data processing sections, data processing sections to which the plurality of second data block groups are allocated.

Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.

Abstract: The invention relates to an automation device, in which a plurality of spatially distributed functional units communicate with one another by means of a common transmission protocol. The device has a microcontroller (110) which has at least one associated clock generator (120) and a memory unit (150) and which is connected at least to a data source (140), which is designed to output a data byte stream to be transmitted. A first program for conversion of a data byte stream to be transmitted to a sequence of sample values of an adequate frequency-modulated line signal, and a second program for identification of a frequency-modulated line signal and for its sequential conversion to a received data byte stream are stored in the memory unit (150), with these programs being associated with the microcontroller (110). The first and the second program can be run alternately.

Abstract: One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver to store the current PPU context of a calling thread on a PPU context stack and to associate a named PPU context with the calling thread. The second operator is a PPU context pop, which causes the PPU driver to restore the PPU context of a calling function to the PPU context at the top of the PPU context stack. By performing a PPU context push at the beginning of a function and a PPU context pop prior to returning from the function, the function may execute within a single CPU thread, but operate on a two distinct PPU contexts.

Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.

Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract: In one or more embodiments, system(s), method(s), integrated circuit(s), physical layer(s), apparatus(es), System-on-Chip (SoC), various other hardware, computer-readable and/or executable instructions, and/or technique(s) are described that enable a subroutine to release control of a processing entity when the subroutine is incomplete. By so doing, the processing entity may be used by code outside of the subroutine, such as code that needs attention, and/or more-fully utilize its own processing power by being less idle.

Abstract: In a communication apparatus, a communication processor rebuilds, with switching of communication systems, a communication bearer to perform communication. An application processor outputs, when background communication occurs or a display unit is shifted from an off state to an on state while notification from the communication processor is stopped, a request signal to the communication processor. The application processor starts the background communication based on information of a latest communication bearer output from the communication processor in response to the request signal.