Abstract: A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis for coordination. A key aspect of the present innovation includes the novel techniques for coordinating processes including transmission of electromagnetism and transmission of electromagnetic radiation in a process environment by effecting periodic interruptions, based upon the abovementioned coherent temporal and resource framework, while maintaining the required operational and safety procedures.

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.

Abstract: Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System Management Interrupt (SMI#) is generated, only a single targeted CPU core enters System Management Mode (SMM) in response to the SMI while the remaining CPU cores continue operating in normal mode. Further, a multi-threaded SMM environment and mutual exclusion objects (mutexes) may allow guarding of key hardware resources and software data structures to enable individual CPU cores among the remaining CPU cores to subsequently also enter SMM in response to a different SMI while the originally selected CPU core is still in SMM.

Abstract: An external logic device for a network interface controller enables interrupt coalescing from a network interface controller. The network interface controller has a cause register for storing information about interrupt causes and drives an interrupt line. The external logic device is connectable to the cause register for reading the contents of the cause register, and to the interrupt line of the network interface controller and to an interrupt input of a processor for forwarding interrupts from the interrupt line of the network interface controller to the processor. The external logic device has a timer which is initializable when the interrupt line contains an interrupt, and is constructed to delay the forwarding of interrupts, depending on the current contents of the cause register, until a timeout of the timer is reached.

Abstract: A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander.

Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: Embodiments include methods, systems and computer program products that include executing a begin transaction instruction to begin a transaction comprising a sequence of instructions, wherein the begin transaction instruction indicates that a resource will be accessed by the first processing device. Embodiments also include determining whether it is safe for the first processing device to access the resource. Based on a determination that it is safe for the first processing device to access the resource, embodiments include processing the sequence of instructions of the transaction. Based on a determination that the sequence of instructions of the transaction has been completed, embodiments include executing an end transaction instruction, wherein the end transaction instruction indicates that the first processing device has completed its access of the resource. Based on a determination that it is not safe for the first processing device to access the resource, embodiments include aborting the transaction.

Abstract: A method and a system for processing a data conflict are provided that relate to the field of signal interface technologies of an integrated circuit, where the method includes sending a power management bus (PMBus) command to a slave device by using a PMBus, so as to perform power management; when the PMBus command fails to be sent, determining whether the number of times that the PMBus command fails to be sent is greater than or equal to a preset value, where the preset value is configured in advance during system initialization; starting timing if the number of times that the PMBus command fails to be sent is less than the preset value; and resending the PMBus command when timing duration reaches resending time. The present invention is applicable to a scenario in which multiple master devices (Masters) send the PMBus command by using the PMBus.

Abstract: A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.

Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.

Abstract: A series of processing that includes a first control step for controlling an apparatus that executes predetermined processing and a second control step for controlling the apparatus based on a control result of the first control step is executed. An execution history of the first control step or the second control step is stored in a memory. The series of processing is interrupted in a case where a predetermined interruption factor occurs during execution of the series of processing. In a case where the interruption is executed, a start step for resuming the series of processing is set to the first control step or the second control step, based on the execution history stored in the memory.

Abstract: In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Abstract: A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The method further includes using the peripheral to request a clock signal. The method also includes selectively control communication of the clock signal to the peripheral in response to the request.

Abstract: The present invention aims to provide a host controller apparatus, an information processing apparatus, and an event information output method that are capable of outputting event information to a system memory while achieving power saving. A host controller apparatus according to the present invention includes: an event controller that outputs occurred event information to a system memory; and an interruption controller that outputs an interrupt signal to a CPU executing an event recorded in the system memory, the interrupt signal requesting execution of the event output from the event controller to the system memory. The event controller outputs the occurred event information to the system memory in synchronization with a timing at which the interruption controller outputs the interrupt signal to the CPU.

Abstract: A computing apparatus identifies that a first processor of a host has forwarded information for a device to a second processor that controls the device. After identifying that the first processor has forwarded the information to the second processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus causes future information for the device to be forwarded to the second processor.

Abstract: An information handling system includes a plurality of processors that each includes a cache memory, and a receive side scaling (RSS) indirection table with a plurality of pointers that each points to one of the processors. A network data packet received by the information handling system determines a pointer to a first processor. In response to determining the pointer, information associated with the network data packet is transferred to the cache memory of the first processor. The information handling system also includes a process scheduler that moves a process associated with the network data packet from a second processor to the first processor, and an RSS module that directs the process scheduler to move the process and associates the first pointer with the processor in response to directing the process scheduler.

Abstract: Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: PCI devices write an MSI message in a memory and polling routines, which are executed by CPU cores respectively, poll the memory. The polling routines poll a cause of interrupt during an interval between tasks, during an interval between threads, and during idle and cause a CPU core with the lowest load to perform interrupt processing. An IO task performs inter-task communication with another IO task by using a command queue.

Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.

Abstract: Systems and methods for enhancing the handling of interrupts in a virtual computing environment are disclosed. A CPU is configured such that the CPU, when in a virtual machine (VM) mode, directs an interrupt to a VM. When in the VM context, a guest in the VM is run with a hypervisor interrupt descriptor table (hypervisor IDT) to determine how the interrupt should be handled. The hypervisor IDT directs an interrupt that is to be handled by the VM to an interrupt handler in a guest IDT without causing a transition to the hypervisor. If an interrupt is to be handled by the hypervisor, the hypervisor IDT causes a transition to the hypervisor.

Abstract: Embodiments of a method and system are disclosed. One embodiment of a method for signaling an interrupt in an I2C system that includes a master I2C device and at least one slave I2C device that are connected by an SDA line and an SCL line is disclosed. The method involves, at the slave I2C device, pulling the SDA line low to signal an interrupt and at the slave I2C device, releasing the SDA line in response to either the SCL line having been pulled low or the expiration of a predetermined time period, whichever occurs first. In an embodiment, the predetermined time period is 1 ms.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: Program execution with improved power efficiency including a computer program that for performing a method that includes determining a current power state of a processor. Low power state instructions of an application are executed on the processor in response to determining that the current power state of the processor is a low power state. Executing the low power state instructions includes collecting hardware state data, storing the hardware state data, and performing a task. High power state instructions of the application are executed on the processor in response to determining that the current power state of the processor is a high power state. Executing the high power state instructions includes performing the task using the stored hardware state data as an input.

Abstract: A sample is generated based on an event. Further, an interrupt handler captures information for an interrupted thread on a current processor. In addition, an affinity of the interrupted thread is set such that the interrupted thread runs only on the current processor without being able to migrate to a different processor. A sampler thread that runs on the current processor retrieves a call stack associated with the interrupted thread after the affinity of the interrupted thread has been set to the current processor. The affinity of the interrupted thread is restored after the call stack has been retrieved.

Abstract: A method of identifying a cause of an interrupt related to an interrupt indication received from an interrupt indicating circuit in a processor, includes the steps of having the interrupt indicating circuit provided with a plurality of lowest-layer registers having a plurality of bits, each of the plurality of bits corresponding to the cause of the interrupt, and one or more upper-layer registers for aggregating the plurality of lowest-layer registers; forming a hierarchical structure with the one or more upper-layer registers and the plurality of lowest-layer register; and identifying the cause of the interrupt by having the processor read the upper-layer registers and the lowest-layer registers in order following the hierarchical structure.

Abstract: Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.

Abstract: Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.

Abstract: Disclosed is a technique for an automated testing harness that transparently preserves testing state across system sessions. The testing harness can be configured to execute a script of testing instructions, one or more of which can trigger a change in a system session. Prior to performing the session change, the testing harness can save test state and suspend the test. Upon resuming the test, the test harness can overwrite the initial values with the saved state values. To enable the automated testing, the testing harness can include a launch daemon and one or more launch agents. Upon a session change, an active launch agent can notify a launch daemon of its active status. This can cause the launch daemon to resume the test and restore the test state to the saved values.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.

Abstract: In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.

Abstract: A protocol for executing the instructions of a non-authorized transaction on the same processor in a multiprocessor environment is provided. A first instruction of a non-authorized transaction including a sequence of instructions is executed. A determination of whether the unauthorized transaction is aborted after each executed instruction. In response to an abort, the non-authorized transaction is rolled back and restarted at the first instruction of the non-authorized transaction. In response to an absence of an abort, the next instruction is executed until all sequenced instructions of the non-authorized transaction are completed on a same processing device.

Abstract: Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.

Abstract: A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection to a network between the network and a designated CPU core, such that for all data packets received from the network an interrupt is created in the designated CPU core for received data packet processing. Each data packet received from the network is associated with an application connection established in a CPU core selected based on processor load and an interrupt thread is created on the CPU core associated with the application connection for processing the data packet. Each data packet being sent to the network is associated with an application connected established either in the CPU core in which the application is executing or an alternative CPU core selected based on processor load.

Abstract: Power throttling may be used to conserve power and reduce heat in a parallel computing environment. Compute nodes in the parallel computing environment may be organized into groups based on, for example, whether they execute tasks of the same job or receive power from the same converter. Once one of compute nodes in the group detects that a parameter (i.e., temperature, current, power consumption, etc.) has exceeded a first threshold, power throttling on all the nodes in the group may be activated. However, before deactivating power throttling, a plurality of parameters associated with the group of compute nodes may be monitored to ensure they are all below a second threshold. If so, the power throttling for all of the compute nodes is deactivated.

Abstract: An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit.

Abstract: In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.

Abstract: A method of operating a system on chip (SoC) includes calculating a first residence time indicating an amount of time that at least one task resides in an execution queue in the SoC, wherein the at least one task is assigned to at least one core of a multi-core processor in the SoC, calculating a total unit residence time indicating an amount of time that all tasks other than the at least one task reside in the execution queue, calculating a second residence time for the at least one core by adding the first residence time of the at least one task and the total unit residence time, and adjusting at least one of an operating frequency and a voltage of the at least one core based on the second residence time.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

Abstract: A disclosed information processing apparatus includes: a first processing unit; and a second processing unit that is in either of an operational state and a suspended state. The first processing unit and the second processing unit are coupled by a first signal line through which a first signal that represents a state of the second processing unit passes and by a second signal line through which a second signal that causes an interrupt to the second processing unit passes. The second processing unit outputs the first signal according to a state of the second processing unit. The first processing unit determines, based on the first signal, whether the first processing unit causes the second processing unit to resume. When the first processing unit causes the second processing unit to resume, the first processing unit outputs the second signal, and the second processing unit resumes, upon receiving the second signal.

Abstract: A real-time sampling device for being coupled to a processing unit includes a first register, a second register, a third register, a trigger output element and a timer for outputting an interrupt signal. The first register externally receives and processes a first input signal to produce processed data. The second register retrieves the processed data from the first register upon receiving the interrupt signal, and the processing unit, upon receiving the interrupt signal, retrieves the processed data from the second register and performs calculation thereon to produce a processed data calculation value and temporarily store the processed data calculation value in the third register. The trigger output element outputs the processed data calculation value in the third register in real time upon receiving the interrupt signal. The real-time sampling device an be applied to digital control systems in order to perform real-time sampling on controlled subjects.

Abstract: An apparatus and a method for allocating interrupts in a multi-core system are provided. According to an embodiment, an interrupt control register unit records the interrupt processing capacity of each core of a multi-core system by receiving an interrupt, and checking the interrupt control register unit when receiving the interrupt and allocating the interrupt to a core which has been checked to be in an interrupt processing enabled state in the checking step. When the core is allocating the interrupt, the core transmits, to the interrupt control register unit, a signal representing the interrupt control register corresponding to the core which is changed to an interrupt processing disabled state, and can process the interrupt.

Abstract: The present invention relates to a reset method and a network device. The method includes: receiving, by an SPI Flash, a reset instruction sent by a processor; and performing reset processing corresponding to the reset instruction according to the reset instruction, where the reset instruction includes interrupting a current operation, recording interruption state information when the current operation is interrupted, and setting a current state to a state of responding to a read instruction of the processor; after finishing the reset operation, sending, by the processor, a read instruction to the SPI Flash, and receiving interruption state information sent by the SPI Flash according to the read instruction; and then determining, according to the interruption state information, whether the interrupted operation in the SPI Flash needs to be continued, and if yes, sending an instruction of continuing the interrupted operation to the SPI Flash.

Abstract: A virtual multi-processor system includes a plurality of logic processors. Moreover, the virtual multi-processor system includes a logic processor controller configured to allocate a time slice to each of the logic processors to control the logic processors so that the logic processors sequentially run in a time-sharing manner. When a request for interrupt processing occurs, an external interrupt controller performs control so that a logic processor that has a time slice within which the interrupt processing is possible and that runs next executes the interrupt processing.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.