Abstract: A power supply circuit for a switching mode power supply, having: a charging capacitor coupled to an auxiliary winding; a power supply diode coupled to a power supply capacitor, wherein the charging capacitor has a connecting terminal coupled to the power supply diode, and the charging capacitor and the power supply diode are serially coupled between the auxiliary winding of the switching mode power supply and the power supply capacitor; and a power supply switch coupled between the connecting terminal and a primary ground of the switching mode power supply.

Abstract: A system and method for shortening the system management mode when a fault occurs in hardware component in a computer system is disclosed. The computer system has hardware components that may have faults. Notification of an error in one of the hardware components is received through RAS silicon on a processing unit. The error is detected from the hardware component by a system management interrupt handler executed by a bootstrap processor core. The error data is logged into a system error log via a system control interrupt handler executed by the processing unit. The system management mode is avoided during the logging of the error data. This prevents other processor cores being suspended from the system management mode.

Abstract: Example method includes: allocating, by a main processor of a wireless access point (WAP) comprising at least the main processor and a plurality of co-processors wherein the main processor and the plurality of co-processors both have access to a random-access memory (RAM) co-located within the WAP, a dedicated non-overlapping segment of the RAM to each of the plurality of the co-processors; receiving, by the main processor of the WAP, a notification from one of the plurality of co-processors indicating that an exception previously defined by the one of the plurality of co-processors has occurred; determining, by the main processor of the WAP, the dedicated non-overlapping segment of the RAM allocated to the one of the plurality of co-processors; and saving, by the main processor of the WAP, the dedicated non-overlapping segment of the RAM allocated to the one of the plurality of co-processors to a fast access memory.

Abstract: A RAID data storage device direct communication system includes a first RAID data storage device that includes a first RAID data storage device controller having a first RAID data storage device function providing a second RAID data storage device submission queue in a first RAID data storage device memory subsystem, and a second RAID data storage device that includes a second RAID data storage device controller having a second RAID data storage device function providing a second RAID data storage device completion queue in a second RAID data storage device memory subsystem. The second RAID data storage device generates a command, transmits the command directly to first RAID data storage device and in the second RAID data storage device submission queue, and receives a completion message that is associated with the command directly from the first RAID data storage device and in the second RAID data storage device completion queue.

Abstract: Methods and apparatuses for aggregated IBIs are provided. The apparatus includes a host controller configured to communicate with at least one slave via a serial communication bus, trigger and receive a series of responses from the at least one slave via the serial communication bus, determine one response of the series of responses indicating an in-band interrupt (IBI) request, and respond to the IBI request based on a position of the one response among the series of responses. The method includes communicating with at least one slave via a serial communication bus, triggering and receiving a series of responses from the at least one slave via the serial communication bus, determining one response of the series of responses indicating an in-band interrupt (IBI) request, and responding to the IBI request based on a position of the one response among the series of responses.

Abstract: A computer apparatus (100) includes an OS execution unit (120), an OS-dependent interrupt processing unit (110), and an OS-independent interrupt processing unit (130). When an OS-independent interrupt (201) due to a state of a device (200) occurs, the OS-independent interrupt processing unit (130) determines whether or not to initiate a task (145). When the task (145) is to be initiated, the OS-independent interrupt processing unit (130) turns on the flag (141) and causes the OS execution unit (120) to generate an OS-dependent interrupt (202). When the OS-dependent interrupt (202) is generated, the OS-dependent interrupt processing unit (110) determines whether or not the flag (141) is on, and when the flag (141) is on, initiates the task (145) and turns off the flag (141).

Abstract: A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

Abstract: An external M.2 solid-state drive dock with local and network interfaces is disclosed. The dock includes an enclosure with apertures through which M.2 solid-state drives can be received. A circuit board is mounted within the enclosure that includes M.2 socket connectors for receiving the M.2 solid-state drives. The circuit board also includes a storage controller coupled to the M.2. socket connectors. A local interface controller is coupled to the storage controller for providing a local interface, such as a USB-C interface, to the M.2 solid-state drives to host computers. A network controller is also coupled to the storage controller for providing network interfaces, such as wired and/or wireless network interfaces, for accessing the M.2. solid-state drives. The storage controller can receive storage requests from the local interface controller and the network interface controller and provide the storage requests to the M.2 solid-state drives.

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. The method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Accordingly, a TLB miss rate is reduced and program execution is accelerated.

Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

Abstract: A method includes for each processed interrupt: identifying an interrupt associated with a first interrupt number; determining that the interrupt is designated as a special interrupt, the special interrupt being an interrupt to be translated to a different interrupt number only if the hardware processor is in user mode; determining a current execution mode for the hardware processor; for each interrupt in operating system mode, delivering the interrupt as the first interrupt number; and for each interrupt in user mode: translating the first interrupt number to a second interrupt number; and delivering the interrupt as the second interrupt number, wherein the current execution mode is determined to be an operating system mode for at least one of the interrupts, and the current execution mode is determined to be a user mode for at least an additional one of the interrupts.

Abstract: Based on a command to interrupt operation of a selected one or more of a plurality of data storage drives coupled to two or more storage controllers, two or more signals are sent from the two or more storage controllers via two or more data busses associated with and coupled to the respective two or more controllers. The selected data storage drive receives the two or more signals via the two or more data busses. Based on determining that the two or more signals agree, the operation of the selected drive is interrupted.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: A processing system includes an execution unit, communicatively coupled to an architecturally-protected memory, the execution unit comprising a logic circuit to execute a virtual machine monitor (VMM) that supports a virtual machine (VM) comprising a guest operating system (OS) and to implement an architecturally-protected execution environment, wherein the logic circuit is to responsive to executing a blocking instruction by the guest OS directed at a first page stored in the architecturally-protected memory during a first time period identified by a value stored in a first counter, copy the value from the first counter to a second counter, responsive to executing a first tracking instruction issued by the VMM, increment the value stored in the first counter, and set a flag to indicate successful execution of the second tracking instruction.

Abstract: A violation of a firmware access rule is detected, and an entry is generated at a log file stored at a baseboard management controller, the entry identifying the violation. In an embodiment, detecting the violation is in response to receiving a system management interrupt at an information handling system.

Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

Abstract: A processor core interrupt control circuit issues a request signal for requesting cancellation of a coprocessor instruction being executed at a coprocessor. A program control circuit issues interrupt processing after issuance of the cancellation request. A coprocessor computation control circuit retains the execution state of the coprocessor instruction. Upon receiving the processing cancellation request signal, a coprocessor interrupt control circuit performs cancellation or holding of the coprocessor instruction on the basis of execution state information retained by the coprocessor computation control circuit. The coprocessor interrupt control circuit evicts the execution state of the coprocessor instruction in the case of holding, and restores the execution state of the coprocessor instruction that had been evicted after completion of the interrupt processing.

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract: A wireless communication device architecture is provided. The wireless communication device can include a WLAN chipset, a cellular chipset, and an application processor. The application processor can include a first portion and a second portion. The first portion can include at least one root complex powered via a dedicated power domain, which can be independent of at least one second power domain that can power the second portion. The WLAN chipset can coupled to a first port of the at least one root complex via a first interface. The cellular chipset can be coupled to a second port of the at least one root complex via a second interface. The at least one root complex can use power received via the dedicated power domain to bridge the WLAN chipset and the cellular chipset while the second portion of the application processor is sleeping.

Abstract: The present disclosure includes systems and methods relating to packed command management for non-volatile storage devices. In some implementations, a device includes: a host controller configured to transfer data between a host memory and a storage device; and a non-transitory medium encoding host software configured to prepare a packed command, which represents more than one command, by loading pointers to memory blocks associated with the packed command into a host memory; wherein the host controller is configured to assert an interrupt to the host software, for at least one command of the packed command, after data transfer for the at least one command is completed, but before data transfer for all of the commands of the packed command is completed.

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract: Certain embodiments of the present invention are directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.

Abstract: Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Abstract: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Abstract: An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.

Abstract: A method for executing a system management interrupt (SMI) is provided. When a power on self test (POST) is executed, a first identifier is generated and stored into a system management mode block of a memory. During a process for starting an operating system (OS), the first identifier is read from the system management mode block as a second identifier, and the second identifier is stored into an OS block of the memory. When the OS wants to use a system management interrupt, the first identifier and the second identifier are respectively read from the system management mode block and the OS block. Afterwards, it is determined whether the first identifier and the second identifier are the same. If the first identifier and the second identifier are the same, the SMI is executed.

Abstract: In an embodiment, a request is received from a virtual machine that specifies a virtual ISN and a hardware resource. A physical ISN is selected that is assigned to the hardware resource. The physical ISN is assigned to the virtual ISN as an assigned pair. The request and the physical ISN are sent to the hardware resource. A physical interrupt is received from the hardware resource that specifies the physical ISN. In response to the receipt of the physical interrupt that specifies the physical ISN, the virtual machine and the virtual ISN that is assigned to the first physical ISN are determined from the physical interrupt and the assigned pair from among a plurality of virtual machines. In response to determining the virtual machine and first virtual ISN that is assigned to the physical ISN, a virtual interrupt that comprises that virtual ISN is sent to the virtual machine.

Abstract: A method and system for permitting a guest to program a message-signaled interrupt-based device is disclosed. A hypervisor of a host detects a request by a guest to map an address range of memory of the guest to a message signaled-interrupt capability table associated with a device. The hypervisor maps the message signaled-interrupt capability table from a message signaled-interrupt capability register of a programmable interrupt controller associated with the host to the address range of memory of the guest. The hypervisor detects an attempt by the guest to program the device with the message-signaled interrupt configuration located in the address range of memory of the guest. The hypervisor programs the device with the message-signaled interrupt configuration specified by the guest in the address range of memory of the guest.

Abstract: Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

Abstract: A method and system for transmitting an aggregated interrupt packet are described herein. The method includes sending metadata from a client device to a host device. The method also includes detecting at least two sets of data from the client device. Additionally, the method includes detecting an identifier for the client device. Furthermore, the method includes generating an aggregated interrupt packet in the client device that comprises the identifier and the at least two sets of data for the client device. The method also includes sending the aggregated interrupt packet from the client device to the host device.

Abstract: A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.

Abstract: Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.

Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison.

Abstract: The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt.

Abstract: A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

Abstract: An interrupt reducing device driver module reduces the rate at which interrupts from a peripheral burden a processor. The interrupt reducing device driver determines when data is associated with the interrupt. When data is present, such as when indicated by an interrupt status register, further interrupts are masked and a buffer associated with the peripheral is read-out. This read-out continues while data is present in the buffer. Once no further data is present, the data interrupts are unmasked. Reduction in the rate of interrupts prevents resource starvation and improves overall system response. Additionally, the processor and associated components are able to enter and remain in low power modes, improving battery life.

Abstract: A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.

Abstract: A multiprocessor system includes a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal and an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units, wherein, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state.

Abstract: An information processing apparatus includes an execution determination unit and a control unit. The execution determination unit determines whether a series of processes including multiple processes is executable at an execution time of the series of processes. The control unit selectively provides at least one recovery device for substituting for the series of processes when it is determined that the series of processes is not executable.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract: A source identification facility is provided that enables identification of the one or more types of adapters requesting an interrupt in order to facilitate processing of the interrupt. The adapter types are accessible to the operating system and are used to tailor processing by the operating system of the interrupt.

Abstract: Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.

Abstract: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

Abstract: A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing.

Abstract: Aspects of a method and system for detecting interrupts from detachable electronic accessories or peripherals are provided. In this regard, a hardware audio CODEC may be operable to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and filter one or more output signals generated from the comparison. When an accessory or peripheral is coupled to the accessory or peripheral port, interrupts from the accessory or peripheral may be detected based on results of the comparison and/or the filtering. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages for a plurality of consecutive clock cycles.

Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a low power mobile device, General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.