Abstract: One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An I/O adapter event notification may be routed and presented to a host or to a guest that the host is executing. To present the notification to the correct host or to the correct guest, various data structures in host and/or guest memory are used.

Abstract: Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified.

Abstract: The latency of virtual interrupt delivery in virtual machines is reduced by normalizing and exposing the virtual interrupt routing information of each VM to a privileged domain such as the VMkernel in an organized manner to enable virtual interrupt delivery that minimizes the number of VCPU hops. A computer implemented method of processing the virtual I/O request comprises receiving the virtual I/O request, responsive to completing a physical I/O corresponding to the virtual I/O request, referring to a virtual CPU set including information on a destination virtual CPU designated by the guest operating system for handling a virtual interrupt corresponding to the virtual I/O request, and generating the virtual interrupt corresponding to the virtual I/O request to the destination virtual CPU determined by referring to the virtual CPU set.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt.

Abstract: A method includes recording a user-level interrupt as undeliverable in a mailbox at least partially based on an interrupt domain identifier and an interrupt recipient identifier included in a user-level interrupt message associated with the user-level interrupt. The recording is at least partially based on an indication that the user-level interrupt is undeliverable to a recipient application thread executing on a processor core of a plurality of processor cores in a multi-core system.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: An anti-virus system for enforcing a virus monitoring and scanning process, the anti-virus and firewall system comprises a master CPU card, a plurality of slave CPU cards and a programmable logic. The master CPU card is used for controlling the virus monitoring and scanning process and dividing the virus monitoring and scanning process into a plurality of sub-processes. The plurality of slave CPU cards are controlled by the master CPU card in a software level and a hardware level, each of the plurality of slave CPU cards receives and processes one of the plurality of sub-processes then sends back to the master CPU card. The programmable logic controlled by the master CPU card for monitoring and controlling said plurality of slave CPU cards at a hardware level.

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract: The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit.

Abstract: A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from a plurality of user-level interrupt delivery configurations. The one or more recipients correspond to one or more application threads executing on one or more processor cores of a plurality of processor cores in a multi-core system. A method includes generating an indicator of a user-level interrupt being undeliverable to one or more intended recipients of a user-level interrupt message according to a failed delivery notification mode configuration. The user-level interrupt may be issued by an application thread executing on a first processor core of a plurality of processor cores in a multi-core system.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

Abstract: The method, apparatus and system of an I/O forwarding technique for multi-interrupt capable I/O devices are disclosed. In one embodiment, a method of transferring an I/O request in a cache-coherent non-uniform memory access (ccNUMA) computer system including multiple cells (e.g., each cell may include multiple processors) that are connected via a system interconnect, includes receiving an I/O request from one of the multiple processors associated with one of the multiple cells in the ccNUMA computer system, associating a processor, corresponding to a multi-interrupt capable I/O interface that is servicing the I/O request, located in the one of the multiple cells as a lead processor, and executing an I/O initiation path and a completion path associated with the received I/O request on the lead processor upon associating the lead processor corresponding to the multi-interrupt capable I/O interface.

Abstract: A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.

Abstract: In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality of guests executable on the system. The interrupt request state identifies which interrupts have been requested at the corresponding interrupt controller in the corresponding guest of the plurality of guests. A guest interrupt manager is coupled to receive an interrupt message targeted at a first destination in a first guest of the plurality of guests, and the guest interrupt manager is configured to update the interrupt request state in the data structure that corresponds to the first destination and the first guest.

Abstract: An interrupt detection apparatus includes a detection address region storing unit configured to store an address region, as a detection address region, to be detected in accordance with a first interrupt message having address information, an issuance interrupt information storing unit configured to store address information of a second interrupt message as issuance interrupt information, an interrupt message detection unit configured to determine that the first interrupt message corresponds to the detection address region, and an interrupt issuing unit configured to issue the second interrupt message having the issuance interrupt information when it is determined that the first interrupt message corresponds to the detection address region.

Abstract: A method for executing a system management interrupt (SMI) is provided. When a power on self test (POST) is executed, a first identifier is generated and stored into a system management mode block of a memory. During a process for starting an operating system (OS), the first identifier is read from the system management mode block as a second identifier, and the second identifier is stored into an OS block of the memory. When the OS wants to use a system management interrupt, the first identifier and the second identifier are respectively read from the system management mode block and the OS block. Afterwards, it is determined whether the first identifier and the second identifier are the same. If the first identifier and the second identifier are the same, the SMI is executed.

Abstract: Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Abstract: In a multiprocessor system including a plurality of processors, the processors execute, at a time of migration a task operating in own processor to another processor, a transmitting task for transmitting the migration target task to a destination processor, and when an interrupt request to be received and executed by an interrupt handler accompanying the migration target task is generated during transmission of the migration target task, the transmitting task receives the interrupt request instead of the interrupt handler and starts the interrupt handler.

Abstract: A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software responds to an interrupt received by the external interrupt interface hardware 26 to write data characterising that interrupt into list registers 18 of the virtual interface hardware 28. A guest operating system for the virtual machine of the virtual data processing apparatus being emulated may then read data from the virtual interface hardware 28 characterising the interrupt to be processed by that virtual machine. The virtual machine and the guest operating system interact with the virtual interface hardware 28 as if it were external interface hardware. The hypervisor software is responsible for maintaining the data within the virtual interface hardware 28 to properly reflect queued interrupts as received by the external interface 26.

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract: Techniques are described of using votes of third-party components to select a master processor from a plurality of redundant processors. A master processor and a standby processor maintain communications with one another. If communication between the master processor and the standby processor fails, the processors may poll a set of registered voters to determine which of the processors is to be the master processor. In this way, the processors may determine which of the processors is to be master without the use of a shared indicator to specify which of the processors is to be the master processor.

Abstract: The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.

Abstract: System, method and program product for managing a plurality of configurations of a first virtual machine. A command is received to set the configuration of the first virtual machine for processing a next incoming interaction and subsequent incoming interactions of at least one protocol from one or more other virtual machines to a configuration exhibited by the first virtual machine which first subsequently prepares to receive the next incoming interaction. The configuration exhibited by the first virtual machine which first prepared to receive the next incoming interaction is determined. The first virtual machine configuration which first prepared to receive the next incoming interaction processes the next incoming interaction.

Abstract: Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt.

Abstract: In an embodiment, a method is provided. The method of this embodiment provides determining a flow context associated with a receive packet; and if the flow context complies with a dynamic interrupt moderation policy having one or more rules, generating an interrupt to process the receive packet substantially independently of an interrupt generated in accordance with an interrupt coalescing scheme (“coalesced interrupt”). Other embodiments are disclosed and/or claimed.

Abstract: A method, apparatus, and computer usable program code for logical partitioning and virtualization in heterogeneous computer architecture. In one illustrative embodiment, a portion of a first set of processors of a first type is allocated to a partition in a heterogeneous logically partitioned system and a portion of a second set of processors of a second type is allocated to the partition.

Abstract: A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1n which outputs an interrupt request when an interrupt source is generated; and an interrupt control part 30 which, upon receipt of the interrupt request, assigns an operation by an interrupt vector to the interrupt operation dedicated core 20.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.

Abstract: Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.

Abstract: Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

Abstract: In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a mobile Internet device (MID) General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.

Abstract: A terminal apparatus generates a hash value from a sequence number based on a predetermined hash algorithm, and creates identification information from an IP address and/or a MAC address and the generated hash value based on a predetermined creation algorithm. Moreover, at the time of processing for shutdown or reboot, the terminal apparatus stores the current recording device information into a hard disk, and when booted next time, determines whether or not the current recording device information and the recording device information stored in the hard disk match with each other. Further, when booted, the terminal apparatus requests a response from another terminal apparatus in the network segment, and when there is not a response from another terminal apparatus, creates management information of terminal apparatuses including itself having been booted in the network segment.

Abstract: Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted. An associated system and machine readable medium are also disclosed.

Abstract: A method for managing interruption of an out of box experience for an information handling system (IHS) whereby the method includes writing a flag to storage device, wherein the storage device is coupled to a processor within the IHS and executing an interruption handling sequence at the processor within the IHS, wherein the processor is operable to read the flag in the storage device as an input to the interruption handling sequence.

Abstract: Certain embodiments of the present invention arc directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.

Abstract: In a data relay device, it is judged whether a destination address of data received from an adapter matches with an address specified for an interruption process. Only data that is judged appropriate is sent to a controller.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Abstract: An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

Abstract: Architectures and techniques that allow legacy pin functionality to be replaced with a “virtual wire” that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Abstract: An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group.

Abstract: A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interrupt controller interface. Interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller. From the plurality of interrupt requests and the second selected interrupt request, a first single interrupt request is selected and transmitted to the processing unit along with a first priority signal, and a first index signal. The processing unit initiates an appropriate interrupt service routine on the basis of said first index signal.

Abstract: In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.

Abstract: A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history.

Abstract: A method and apparatus are provided for reducing latency associated with processing events of a hardware interrupt. Send and receive events share the same hardware interrupt. A receive handler and a separate send handler are provided to simultaneously process completion of a send event and a receive event. In addition, separate queues are provided to communicate receipt of an event to the respective interrupt handler.