Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up the data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: User programs composed of modules for use in automation systems may be created in a cyclic programming process. When solutions are created for complex automation tasks, there is a danger that during the execution of program sequences, individual operands can assume unexpected values in an unforeseen manner, causing error responses in the automation system. The method and programming tool allow data breakpoints to be set up within program logic that in particular has been graphically programmed, in the event of an occurrence of specific conditions. These data breakpoints are set up using a marker in an operand table, which contains selected operands coupled with the type and/or scope of the respective access operation, and using the unique definition of a specific access operation, (achieved by the marker), as a condition for the occurrence of the desired program interruption.

Abstract: A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing special cluster manager devices that can convert “N” serial messages received from a local APIC to “M” parallel messages, wherein M is less than N. The special cluster manager device then transfers the “M” parallel messages to a receiving cluster manager device. The receiving cluster manager device converts the “M” parallel messages into the original “N” serial messages, and sends the “N” serial messages to the appropriate local APIC within the receiving cluster.

Abstract: A method for allowing appliance-to-appliance communication transactions wherein an appliance communications manager that stands apart from source and destination appliances receives a connection request from a source appliance. A phonebook having a plurality of phonebook entries, and stored in the appliance communications manager, is then accessed. Each of the phonebook entries includes a destination appliance identifier and associated destination appliance communication information. A user of the source appliance is presented with a list having a plurality of the phonebook entries. The appliance communications manager receives the identity of a destination appliance selected from said list and, via the appliance communications manager, a communication link is established with the selected destination appliance. When a communication message is received from the source appliance, the communication message is sent to the selected destination appliance.

Abstract: An interrupt controller may receive a plurality of interrupts from a variety of sources. An interrupt source register may be utilized to determine the interrupt source. A prioritizer may then determine the priority of each interrupt based on the source of the interrupt. The prioritizer then controls which interrupts are forwarded to a vector generator. The vector generator calculates a interrupt service routine vector of the highest priority interrupt for the core processor. As a result, the core processor receives only the highest priority interrupt vector. When the core processor has finished processing the highest priority interrupt, in some embodiments, the next highest priority interrupt vector is then forwarded for handling.

Abstract: An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

Abstract: An object-oriented interrupt processing system in a computer system creates a system database including a device namespace containing an entry for each device in the computer system and an interrupt namespace containing an entry for each interrupt source, arranged as an Interrupt Source Tree. Each entry in the Interrupt Source Tree is cross-referenced to a corresponding entry in the namespace and contains a reference to an interrupt handler for the corresponding interrupt source. When an interrupt occurs, a single interrupt dispatcher is invoked, to access the Interrupt Source Tree and cause execution of the corresponding interrupt handler.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Abstract: The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Abstract: To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.

Abstract: In accordance with methods and systems consistent with the present invention, an improved deadlock-free routing system is provided to a family of network topologies where both the configuration of the networks and the routings are designed to optimize performance. In this system, each network utilizes static routing tables that perform deadlock-free routing in an optimized manner to reduce the amount of communication overhead when routing traffic. Specifically, the routings in accordance with methods and systems consistent with the present invention require no more than two hops for networks up to a size of 16 nodes. As a result, the deadlock-free routing provided in accordance with methods and systems consistent with the present invention incurs less communications overhead than some conventional systems while still avoiding deadlock.

Abstract: A node controller (12) includes a processor interface unit (24) that receives an interrupt signal (50). The processor interface unit (24) includes a register (52) with a forward enable bit (54). In response to the forward enable bit (54) being set, the processor interface unit (24) generates a forward interrupt signal (56) for transfer to an input/output interface unit (26) of the node controller (12). The input/output interface unit (26) generates an interrupt request for transfer to a remote node controller. The input/output interface unit (26) includes an interrupt destination register (58) that includes an identity of a particular remote node controller and associated processor interface unit to which the interrupt request is to be transferred. The remote node controller having a processor attached thereto to handle the interrupt request.

Abstract: The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a bi-directional data bus for conveying plural bits of data or command between a master controller and one or more client controllers; direction signal controlling the direction in which data or command bits are conveyed on the data bus as between the master controller and a connected one of the one or more client controllers; a pair of ready signals including a transmit ready signal asserted by a source of data or command bits placed on the data bus and including a receive ready signal asserted by a destination for the data or command bits placed on the data bus; and a clock signal for indicating the presence of valid data or command bits on the data bus on a leading or trailing edge thereof. Preferably, a command/data signal is also provided to indicate the type of information placed on the data bus by the source.

Abstract: A novel method and apparatus for managing communication transactions between electronic appliances is presented. The invention includes a source input/output (I/O) communications function which establishes a first communication link between the apparatus and a source appliance, and a destination I/O communications function which establishes a second communication link between said apparatus and a destination appliance. The apparatus stores and executes a communications program in program memory which manages communications transactions between the source I/O communications function and destination communications function.

Abstract: A data output apparatus includes: a storage device in which a first storage area is formed in advance; a first receiving device for receiving a parameter set for setting a condition of the output process, and storing the received parameter set into the first storage area; a forming device for forming a second storage area in the storage device, and linking the formed second storage area with the received parameter set; a second receiving device for receiving a data set, and storing the received data set into the second storage area; a processing device for identifying the parameter set linked with the second area in which the received data set is stored, setting the condition of the output process according to the identified parameter set, and processing the received data set according to the output process whose condition is set by the identified parameter set; and an output device for outputting the processed data set.

Abstract: A write register access circuit 201 comprises data input terminals 1e01˜1e32, 32 pieces of first-stage flip-flops 1a01˜1a32, 16 pieces of second-stage flip-flops 1b01˜1b16 connected to the first-stage flip-flops 1a01˜1a16, an OR gate 1g, a flip-flop 1h, a NAND gate 11, 16 pieces of data selector circuits 1c01˜1c16, 32 pieces of gate circuits 1d01˜1d32, and 32 pieces of data output terminals 1f01˜1f32, and the write register access circuit 201 is connected to a CPU circuit 215 through an interruption request circuit Z. Therefore, when the write register access circuit 201 is included in an LSI, the write register access circuit 201 enables parallel processing between the CPU and the LSI without necessity of matching the instruction word length of the CPU and the bus width of the LSI, providing an internal bus width changing switch, and dealing with the problem at the software end of the CPU. Further, data transfer rate is increased.

Abstract: A system, method and article of manufacture are provided for minimizing the amount of changes that need to be made to exception handling logic when new exceptions are added. Exceptions are organized into hierarchies in a polymorphic exception handler. A root of one of the hierarchies in which an exception occurs is caught. The exception is instructed to rethrow itself. The rethrown exception is caught and identified. A type of the rethrown exception is determined and a message is outputted indicating the type of the rethrown exception.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: An apparatus and a method are provided to distribute interrupts from a system bus to Intel® Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.

Abstract: A distributed computing platform using the idle computational processing power of a plurality of provider computers is disclosed. At least one networked server collects tasks from client computers, schedules and distributes the tasks to networked provider computers, and collects and returns results to client computers. A client API forms tasks and collects results. A compute engine operates on the provider computers to communicate with the server and execute tasks using idle computational power.

Abstract: The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

Abstract: A processing system having a virtual subsystem architecture employs a reentrant system management mode mechanism and device handlers along with remappable hardware resources to simulate physical subsystems, all transparent to application programs executing on the processing system.

Abstract: A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.

Abstract: A computer system includes an address and data path interconnecting an on-chip CPU with a module and an external communication port, event request packets being generated by the CPU and the module and memory access packets being generated by the CPU, each packet having a destination address and being distributed in parallel format on-chip with a reduction to a more serial format for off-chip communication.

Abstract: The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Abstract: A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

Abstract: A computer system that includes a microprocessor, and at least one other device on a single integrated circuit chip that can be connected to an external computer device. The integrated circuit chip includes: an on-chip CPU having a plurality of registers, a communication bus for providing a parallel communication path between the CPU and a first memory local to the CPU, and an external communication port connected to the communication bus. The port [having] has an internal connection to the communication bus with an internal parallel signal format and an external connection to the external computer device with an external format less parallel than the internal parallel signal format.

Abstract: An initialization of local buses 14a to 14n, a definition of topology and a management of isochronous resources are performed for every local bus. Each of portals 12a to 12n includes an asynchronous packet discriminator 215 which discriminates an asynchronous packet sent by a terminal device and transfers it. The portals 12a to 12n discriminate asynchronous packets sent by terminal devices in order to acquire isochronous resources and secure isochronous resources on different buses. The portals 12a to 12n transfer isochronous packets to different local buses by associating a received isochronous packet with a plug on the bridge bus side and a plug on the local bus side with an isochronous channel on the bus. Thus, the utilization efficiency of bus resource in a serial bus network is improved and a packet sent from a terminal device can be transferred to a different bus.

Abstract: One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register.

Abstract: A robot controller and its control method use a generic personal computer and a PC operating system.

Abstract: A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction commands among and host devices. The system employs an interrupt controller to manage interrupt commands issued by devices. The system further employs a concurrent bridge to support communication between the controllers and at least one host device. With this system, congestion due to control and data traffic is minimized and a more efficient operation of central processor units is achieved.

Abstract: An interrupt messaging scheme to manage interrupts within a multiprocessing computer system without a dedicated interrupt bus. An interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the multiprocessing system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. A suitable routing algorithm may be employed to route various interrupt packets within the system. Simultaneous transmission of interrupt messages from two or more processing nodes and I/O bridges may be possible without any need for bus arbitration. Interrupt packets carry routing and destination information to identify source and destination processing nodes for interrupt delivery. A lowest priority interrupt packet from an I/O bridge is converted into a coherent form by the host processing node coupled to the I/O bridge.

Abstract: A processor for controlling execution of instructions stored in a main storage and interruption processing, comprises: interruption processing control device operable to accept an interruption request, analyze an accepted interruption to obtain a cause of the interruption, and generate information indicating a storage position in the main storage of a procedure for processing the cause of the interruption; specific address holding device operable to hold first address information obtained from the information generated by the interruption processing control device; and instruction execution control device operable to decide whether or not the first address information held by the specific address holding device is to be used as information indicating a storage position of an instruction to be executed and control instruction execution according to a decision result.

Abstract: A method and apparatus for detecting an interrupt request in a video graphics or other system are accomplished by reading or polling a shared interrupt request flag stored in one of multiple potentially interrupting devices and determining whether a pending interrupt request exists based on a status of the shared interrupt request flag. In the event that a pending interrupt request exists, a notification of the pending interrupt request is provided to an interrupt service routine. In the event that a pending interrupt request does not exist the circuitry that is reading or polling the shared interrupt request flag delays for a polling interval and then repeats reading or polling the shared interrupt request flag and determining whether a pending interrupt request exists.

Abstract: A programmable interrupt controller (510) for a single interrupt architecture processor (518) includes a plurality of interrupt sources (502) each operable to generate an interrupt. A dynamically alterable interrupt mask (508) selectively blocks interrupt signals for the interrupt sources (502). Interrupts permitted by the dynamically alterable interrupt mask (508) are processed by an interrupt handler (500) for the single interrupt architecture processor (518) in order of priority. In addition, processing for a lower priority interrupt is interrupted in order to process a later received higher priority interrupt permitted by the dynamically alterable interrupt mask (508).

Abstract: An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Abstract: A method and apparatus for reliable interrupt reception over a buffered bus utilizes a mailbox register to receive interrupt request information sent after a data write transaction. The data is sent from an initiating peripheral device over the buffered bus to arrive with an arbitrary delay at the host memory. After completing the sending phase for the data the initiating peripheral device sends a mailbox register data block containing an interrupt request to a mailbox register associated with the host processor. Because the mailbox register data block will necessarily arrive after the receipt of the actual data in the host memory because it is following the actual data through the same buffered bus, the interrupt will be properly sequenced with the receipt of data.

Abstract: A method and apparatus for providing remote, distributed processing of a task by employing a wide area network (e.g., the Internet). A resource provider initiates the process by sending an application to a resource allocator requesting to be added to the resource allocator's list of providers. The resource allocator accepts or rejects a particular resource provider based on the application. If accepted, the resource provider waits for a task from the resource allocator. Upon receiving a task, the resource provider evaluates the currently available local resources. The resource provider determines whether or not it is currently able to handle the task in view of the available local resources. If the resource provider is able to handle the task, it accepts the task. The resource provider processes the task and returns the results to either the resource allocator or the original resource requester.

Abstract: Each node of multinode computer system includes an interrupt controller, a pair of send and receive queues, and a state machine for communicating interrupts between nodes. The communication among the interrupt controller, the state machine, and the queues is coordinated by a queue manager. For sending an interrupt, the interrupt controller accepts an interrupt placed on a bus within the node and intended for another node and stores it in the send queue. The controller then notifies the interrupt source that the interrupt has been accepted before it is transmitted to other node. The interrupt has a first form suitable for transmission on the bus. A state machine within the node takes the interrupt from the send queue and puts the interrupt into a second form suitable for transmission across a network connecting the multiple nodes.

Abstract: One embodiment of the present invention provides an apparatus within a computer system that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a central processing unit that maintains status information for peripheral devices in a status register.

Abstract: An apparatus and method of dynamic resource mapping for isolating interrupt sources is implemented. Each interrupt source is provided with a unique identifier. The identifier is mapped to an interrupt number which is sent to an operating system when the interrupt source corresponding to the identifier generates an interrupt. Each device is associated with a data structure that includes a data value which is operable for accessing an interrupt register. The data value may be a pointer that points to a pointer to the interrupt register for the device generating the interrupt. When an interrupt is generated, the mapping may be used to access the pointers which thereby provide direct access to the interrupt register, whereby the contents of the interrupt register are processed by an interrupt service routine.

Abstract: An interrupt messaging scheme for a multiprocessing computer system where a dedicated bus to carry interrupt messages within the multiprocessing system is eliminated. Instead, an interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. Various interrupt requests are transferred through a predetermined set of discrete interrupt message packets. Interrupt message initiators—an I/O interrupt controller or a local interrupt controller (in case of an inter-processor interrupt)—may be configured to generate appropriate interrupt message packets upon receiving an interrupt request. A suitable routing algorithm may be employed to route various interrupt messages within the system.

Abstract: In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.

Abstract: One embodiment of the present invention provides a method that maintains status information for peripheral devices in a status register, which is located within a central processing unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor performs an internal read of the status register to determine which peripheral device requires processing. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices.

Abstract: A communication system including at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.

Abstract: A distributed computer system includes a host CPU, a network/host bridge, a network/I/O bridge and one or more I/O devices. The host CPU can generate a locked host transaction, which is wrapped in a packet and transmitted over a network to the remote I/O device for replay. The remote I/O devices can generate interrupts. The interrupt is wrapped in a packet and transmitted to the host computer for replay as an interrupt. The host CPU then executes the appropriate interrupt service routine to process the interrupt routine. The remote location of the I/O device with respect to the host CPU is transparent to the CPU and I/O devices. The bridges perform wrapping and unwrapping of host and I/O transactions for transmission across a network.

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods.

Abstract: During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-"OR" bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.