Abstract: An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

Abstract: Disclosed herein are systems and method for live migration of a guest OS, the method comprising: interrupting execution of the guest OS in the hypervisor on a source computing device, transferring a state of the guest OS from the hypervisor on the source computing device to a hypervisor on a target computing device, and resuming execution of the guest OS in the hypervisor on the target computing device without waiting for completion of pending I/O requests on the source, wherein the pending I/O requests are generated by the guest OS in the hypervisor on the source and have not been completed before the interruption of execution of the guest OS, and wherein after resuming execution of the guest OS, the guest OS in the hypervisor on the target computing device is allowed to generate new I/O requests without waiting for completion of pending I/O requests on the source computing device.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: A computing device is provided, including memory storing an instruction storage location. The computing device may further include a processor system including a plurality of processor threads. The processor system may suspend execution of one or more respective processor threads of the plurality of processor threads. The processor system may store one or more respective processor thread contexts of the one or more processor threads in the memory. The processor system may enter a system management mode (SMM). The processor system may determine that the instruction storage location includes a code update instruction. The processor system may perform a code update based on the code update instruction. The processor system may exit the SMM. The processor system may retrieve the one or more processor thread contexts from the memory and resume execution of the one or more processor threads without rebooting the computing device.

Abstract: Method and systems for executing a non-maskable interrupt are provided. In one aspect, a method for executing a non-maskable interrupt includes: obtaining an interrupt request in a non-secure mode, and interrupting an operation of an operating system (OS); saving, in a secure mode, a status of the OS when the operation of the OS is interrupted; executing, in the non-secure mode, a procedure defined for the interrupt request; resume, in the secure mode, the status of the OS; and after resuming the status of the OS, continue executing the operation of the OS in the non-secure mode.

Abstract: A plurality of processing entities are maintained. A plurality of task control block (TCB) groups are generated, wherein each of the plurality of TCB groups are restricted to one or more different processing entities of the plurality of processing entities. A TCB is assigned to one of the plurality of TCB groups, at TCB creation time.

Abstract: Embodiments described herein provide a method for an error logging mechanism operated with controller area network (CAN) buses within an Ethernet network. A first interrupt request indicative of a first error condition that occurs at the first CAN bus is received at an Ethernet bridge and from a first CAN controller connected to a first CAN bus. In response to the first interrupt request, the first interrupt request is serviced by retrieving, from a first error register at the first CAN controller, information relating to the first error condition. The information relating to the first error condition is encapsulated in a first frame in compliance with a layer 2 transport protocol for time-sensitive applications. The encapsulated first frame is then sent, via an Ethernet switch, to an error logging device installed at a location remote to the first CAN bus.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: An information processing apparatus includes a processor. The processor assigns priority levels to respective logics arranged in a chain graph. Each logic is activated by an input event to generate an output event. The processor allocates tokens to the logics based on the priority levels. The processor estimates, for each of the logics, a total number of generated output events to obtain an expected amount of tokens corresponding to the total number. The processor compares, for each of the logics, the expected amount of tokens to an amount of the allocated tokens to determine whether each of the logics has a surplus or a shortage in the allocated tokens. The processor adjusts a frequency of activating each of logics having the shortage. The processor calculates a total amount of the surplus. The processor reallocates the total amount of the surplus to the logics having the shortage.

Abstract: A task switching assisting method includes storing, by an information processing apparatus, task information regarding a task executed by a user. An element related to execution of the task is stored in correlation with the task information, an operation related to the task is determined, a work status with respect to the correlated element related to the execution of the task is determined based on the determined operation related to the task, the task is switched by saving or restoring the work status, based on the task information and the work status with respect to the correlated element related to the execution of the task, task execution resource information for executing the task and task saving resource information at a time of saving the task are analyzed on a task basis, and the task information is generated based on a result of the analysis, by the information processing apparatus.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: A processor comprises a register to store a first reference to a context data structure specifying a virtual machine context, the context data structure comprising a second reference to a target array and an execution unit comprising a logic circuit to execute a virtual machine (VM) based on the virtual machine context, wherein the VM comprises a guest operating system (OS) associated with a page table comprising a first memory address mapping between a guest virtual address (GVA) space and a guest physical address (GPA) space, receive a request by the guest OS to switch from the first memory address mapping to a second memory address mapping, the request comprising an index value and a first root value, retrieve an entry, identified by the index value, from the target array, the entry comprising a second root value, and responsive to determining that the first root value matches the second root value, cause a switch from the first memory address mapping to the second memory address mapping.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.

Abstract: Threads that are generated during specific processing are managed, with an operation core of threads that are generated during activation processing being fixed to a specific core, and an operation core of threads for specific processing that are generated after the activation processing is complete not being set. Also, the setting of the operation core of threads for specific processing that were generated before the timing at which the activation processing is completed is restored to an original setting.

Abstract: Methods and devices for managing devices not directly accessible to device management server are provided. A device for communicating a Location Update Alert message to a Device Management (DM) Server via a DM Gateway includes a memory for storing code of a DM client and a plurality of DM MOs, each of the plurality of DM MOs including one or more nodes, a processor for executing the code of the DM client stored in the memory, a communications unit for receiving and sending messages for the DM client, and the DM client for communicating a Location Update Alert message to the DM Server via the DM Gateway upon detecting a change in an address of the device, based on a LocationUpdate node of at least one of the plurality of DM MOs.

Abstract: A mobile X-ray apparatus includes: an X-ray radiation device configured to emit X-rays; a controller configured to control the X-ray radiation device; a power supply configured to supply operating power to the X-ray radiation device and the controller from a lithium ion battery and control overcurrent that occurs during emission of the X-rays by the X-ray radiation device; and a charger configured to charge the power supply.

Abstract: A processor comprises a register to store a first pointer to a context data structure specifying a virtual machine context, the context data structure comprising a first field to store a second pointer to a plurality of realm switch control structures (RSCSs), and an execution unit comprising a logic circuit to execute a virtual machine (VM) according to the virtual machine context, wherein the VM comprises a guest operating system (OS) comprising a plurality of kernel components, and wherein each RSCS of the plurality of RSCSs specifies a respective component context associated with a respective kernel component of the plurality of kernel components, and execute a first kernel component of the plurality of kernel components using a first component context specified by a first RSCS of the plurality of RSCSs.

Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

Abstract: A Logical Dispatchable Unit Engine identifies a unit of work to be executed. The Logical Dispatchable Unit Engine determines whether the unit of work is to be dispatched to a general processor or a specialty engine based on characteristics associated with the unit of work, instructions associated with the unit of work and/or restrictions associated with the unit of work. The Logical Dispatchable Unit Engine communicates with an Operating System kernel to dispatch the unit of work for execution, responsive to determining whether the unit of work is to be dispatched to a general processor or a specialty engine.

Abstract: Systems and methods for delivering certain types of interrupts to virtual machines executing privileged virtual machine functions. An example method may comprise: receiving, by a hypervisor being executed by a processing device of a host computer system, a request to send an interrupt to a virtual central processing unit (vCPU) of a virtual machine; responsive to detecting that the vCPU is executing a virtual machine (VM) function, monitoring the vCPU for completion of the VM function; and responsive to detecting that execution of the VM function is complete, delivering the interrupt to the vCPU.

Abstract: A method includes running multiple processing tasks on multiple physical processing cores that support general-purpose registers and special-purpose registers. Respective usage levels, with which the processing tasks use the special-purpose registers, are estimated. The physical processing cores are assigned to the processing tasks based on the estimated usage levels of the special-purpose registers.

Abstract: A method for modeling a hydrocarbon reservoir. A representation of a simulation model is generated in a non-transitory, computer readable medium. The simulation model is used to generate computational tasks. The tasks are allocated among a plurality of computational nodes. Each processing node of the plurality of computational nodes includes core processors and a shared memory accessible by the core processors. The reservoir simulation is executed on the plurality of computational nodes. During the reservoir simulation, if a first processing node in the plurality of computational nodes finishes executing its allocated tasks, a migration request is sent from the first processing node to another processing node in the plurality of computational nodes. The migration request is configured to request migration of a movable task from the other processing node to the first processing node. The movable task is migrated from the other processing node to the first processing node.

Abstract: The present invention provides a method and an apparatus for training a Vector coefficient of a vectored digital subscriber line, where the method includes: after a handshake phase is executed for a joining line, calculating, by using a pilot estimation method, an initial precoding coefficient and an initial cancellation coefficient that represent interference from the joining line to a normal working line; and after a channel discovery phase is executed for the joining line, compensating the initial precoding coefficient and the initial cancellation coefficient by using a compensation factor, to obtain a precoding coefficient and a cancellation coefficient that represent the interference from the joining line to the normal working line, wherein the compensation factor is obtained according to a signal power change or a signal phase change of the joining line. The present invention improves efficiency of Vector coefficient training.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: Methods for managing inter-CPU interrupts between sending and receiving CPUs are disclosed. As a part of a method, a target CPU identifier and an interrupt number is written in an interrupt send register of an interrupt sending CPU, the interrupt number is written into one of a plurality of locations of an interrupt receive register corresponding to the target CPU, an identifier of the location of the highest priority interrupt of a plurality of interrupts received by the interrupt receive register is written in an interrupt pick register, the interrupt pick register is read to determine the highest priority interrupt and a matrix associated with the target CPU is read to determine the sender of the highest priority interrupt. The highest priority interrupt is processed.

Abstract: A method includes for each processed interrupt: determining whether the interrupt is a user mode interrupt; upon determining that the interrupt is a user mode interrupt, determining a stack location to insert an entry corresponding to the user mode interrupt, the stack location being calculated by adjusting a current stack pointer by a red zone offset; and inserting the entry corresponding to the user mode interrupt into the stack at the stack location.

Abstract: An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.

Abstract: A method of optimizing system parameters in a crude unit to reduce corrosion and corrosion byproduct deposition in the crude unit is disclosed and claimed. The method includes measuring or predicting properties associated with the system parameters and using an automated controller to analyze the properties to cause adjustments in the chemical program to optimize the system parameters. Adjusting the system parameters effectively controls corrosion in the crude unit by reducing the corrosiveness of a fluid in the process stream and/or by protecting the system from a potentially corrosive substance. System parameter sensing probes are arranged at one or more locations in the process stream to allow accurate monitoring of the system parameters in the crude unit.

Abstract: A system including an interrupt generation module and a processing detection module. The interrupt generation module is configured to generate an interrupt when a first indicator is set to a first state, where the first indicator transitions to a second state when the interrupt is generated. The processing detection module is configured to detect when the interrupt is sent, set a second indicator to a third state to indicate when the interrupt is sent, and set the second indicator to a fourth state when the interrupt is processed.

Abstract: Systems and methods are described for managing applications in a computer system. An operating system kernel such as Linux can be started and executed at different addresses other than the address typically used for such kernels. An operating system kernel can accommodate end of memory and size of memory that do not comply with normal system specifications. Mechanisms are described that change methods for exception vector handling using a software fix. Dual and/or multi-core systems can run applications in both SMP and ASMP modes without needing any hardware changes. Separate instances or similar copies of an OS such as Linux can be executed on multiple cores in ASMP mode. In SMP mode, Linux or another OS can run as a single instance of the OS.

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: A microcomputer includes a central processing unit (CPU) and a data transfer controller (DTC). The data transfer controller (DTC) reads out data transfer information including transfer mode information from a storage device (RAM) or the like. The data transfer controller (DTC) analyzes the transfer mode information to change at least one of a transfer source address, a transfer destination address, the number of transfer operations, and data transfer information that is used next.

Abstract: A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.

Abstract: In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

Abstract: An electronic computing device comprises first and second nonvolatile memories. The second nonvolatile memory serves as a main memory of the device. A processor clears the second nonvolatile memory in response to shutdown command according to a setting reflecting a first user operation. A processor clears the second nonvolatile memory and loads the kernel from the first nonvolatile memory to the second nonvolatile memory in response to a boot command according to a condition of a second user operation detected by the processor regardless of the setting reflecting the first user operation.

Abstract: The disclosure is applied to a field of communication technologies and relates to a method for controlling multiple CAN interfaces through a single SPI bus.

Abstract: According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

Abstract: In some embodiments, a method includes executing an atomic transaction in a system having a transactional memory. The method includes receiving a signal interrupt during executing of the atomic transaction. The method includes storing a state of the signal interrupt to enable subsequent execution of the signal interrupt. The method includes returning to executing the atomic transaction until the atomic transaction is at least one of completed and aborted. The method includes after executing the atomic transaction is at least one of completed and aborted, determining whether the signal interrupt is received during executing of the atomic transaction. The method includes after determining that the signal interrupt is received during executing of the atomic transaction, retrieving the state of the signal interrupt. The method includes executing an interrupt handler for processing the signal interrupt and returning from executing of the atomic transaction.

Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.

Abstract: Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.

Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.

Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.

Abstract: Systems and methods for enhancing the handling of interrupts in a virtual computing environment are disclosed. A CPU is configured such that the CPU, when in a virtual machine (VM) mode, directs an interrupt to a VM. When in the VM context, a guest in the VM is run with a hypervisor interrupt descriptor table (hypervisor IDT) to determine how the interrupt should be handled. The hypervisor IDT directs an interrupt that is to be handled by the VM to an interrupt handler in a guest IDT without causing a transition to the hypervisor. If an interrupt is to be handled by the hypervisor, the hypervisor IDT causes a transition to the hypervisor.

Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.

Abstract: Data replication in a distributed node system including one or more nodes. A consensus protocol for failure recovery is implemented. Data items and information relating to consensus protocol roles of participant nodes are stored in at least some of the plurality of nodes. Logical logs stored in at least some of the plurality of nodes are created. The logical logs contain additional consensus protocol information including container metadata and replicated data.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.