Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Abstract: Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signal interrupts in different manners. For example, some clients signal interrupts in a level-based manner, and some clients signal interrupts in a pulse-based manner. In an embodiment, all interrupts received by the interrupt handler are formed into an event message according to a uniform format regardless of the manner in which the interrupt is signaled. The event message includes all information necessary for a host processor interrupt service routine (ISR) to service the interrupts without reading hardware registers. Event messages are stored in an event buffer for access and handling by the host. The event buffer is managed by the interrupt handler.

Abstract: Provided are techniques for retrieving lock attention data. A group of attention connection paths configured to transmit lock attention interrupts and lock attention data between the host and the control unit are identified. A lock attention interrupt is received from the control unit. In response to receiving the lock attention interrupt, a connection path from the group of attention connection paths is selected and lock attention data is retrieved from the control unit using the selected connection path.

Abstract: The invention virtualizes a computer that includes a host computer system, which comprises a processor, memory, and physical system devices. A conventional operating system (referred to below as the “host operating system” or “HOS”) is installed on the hardware. A computer program product that is executable within the host computer system comprises computer-executable code for implementing an interface software layer, preferably a virtual machine monitor, between the host system and a virtual machine; for reading in and storing state information of the processor associated with the HOS; and for logically decoupling the HOS from the processor with respect to pre-determined functions of the interface software layer and the virtual machine by setting the processor state information to settings associated with the interface software layer.

Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: A high availability system includes a first server computer for a first virtual computer and a first hypervisor and a second server computer for a second virtual computer and a second hypervisor. The first virtual computer executes a processing and the second virtual computer executes the processing behind from the first virtual computer. Information associated with an event is transmitted. The event provides an input to the first virtual computer. In the second hypervisor, a control unit performs, control based on the information to match the execution state of the second virtual computer and that of the first virtual computer, and control associated with the information, when the event associated with the information is predetermined one of an I/O completion interrupt from the first virtual storage and an interrupt handler call corresponding to the interrupt, after the interrupt from the second virtual storage corresponding to the interrupt is caught.

Abstract: System and method for direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. A first task with a first memory context and with the staff function as a component executes the start function to perform a context switch from the first memory context into a second memory context. The target function is a component of a second task with the second memory context. The target function is executed in the second memory context, and the context switch is reversed to return to the first memory context after executing the target function.

Abstract: To aim to provide an information processing device capable of improving a processing capability and securely handling programs and data to be protected. According to a system LSI 100 including a plurality of CPUs, when a CPU-1 102 switches to a protection mode, the CPU-1 102 and a CPU-2 103 are reset. While the CPU-1 102 operates in the protection mode, only the CPU-1 102 executes a protection program and the CPU-2 103 is stopped by continuing outputting a reset signal to the CPU-2 103.

Abstract: Methods for adding a communication connection to a vectored group of communication connections and corresponding apparatuses are disclosed.

Abstract: A method for relocating system management interface code in an information handling system which includes extracting a relocation table from the system management interface code, inserting a relocation identifier in each entry of the system management interface code having an address, searching the system management code for the relocation identifier during execution of the information handling system, and inserting an address based upon a relocation address for each entry in the system management interface code having a relocation identifier.

Abstract: A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units.

Abstract: A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with at least one other processing core of the computer system in response to determining that the at least one processing core is halted. An associated system and machine readable medium are also disclosed.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A system includes a plurality of partitions having respective operating systems, and a resource shared by the partitions. The resource has plural segments, where a first one of the segments is accessed to invoke a first interrupt. An operating system of a first one of the plurality of partitions invokes, in response to the first interrupt, a routine to cause generation of a second interrupt to a second one of the plurality of partitions.

Abstract: A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond to the interrupts. The exception vector considers the type of interrupt and the priority level of the interrupt when selecting the exception vector. Shadow set mapping logic is coupled to the vector generator. The mapping logic contains a number of fields that correspond to the different exception vectors that may be generated. The fields are programmable by kernel mode instructions, and contain data mapping each field to one of a number of shadow register sets. When an interrupt occurs, the vector generator generates a corresponding exception vector. In addition, the shadow set mapping logic looks at the field corresponding to the exception vector, and retrieves the data stored therein.

Abstract: Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and claimed.

Abstract: An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed by OS1, a second area storing a reset handler containing instructions for returning to OS2 and for branching to OS2, and a switching unit that switches connection/disconnection of the first area with outside; a table storing unit storing information showing the reset handler's position; a CPU having a program counter and executing an instruction at a position indicated by positional information in the program counter; and a management unit that, when instructed to switch from OS1 to OS2 while the apparatus is operating with OS1, instructs the switching unit to disconnect the first area and the CPU to reset. When instructed to reset itself, the CPU initializes its state and sets the reset handler positional information into the program counter.

Abstract: In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by copying contents of the address field and data field of an entry in the MRT into the address field and data field of the MSI. Other embodiments are described and claimed.

Abstract: A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

Abstract: Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: A method, a computer program product and a computer system for controlling the execution of an interruption routine for interrupting an active application. The computer system may include a first detector unit operable to detect if any application of multiple other applications is requesting interruption of the active application. Furthermore, the computer system may include a second detector unit operable to detect input data generated in response to a user interacting with the computer system. The computer system may also include a processing unit operable to execute a first sub-routine of the interruption routine when the input data has not been detected and a second sub-routine of the interruption routine when the input data has been detected. The execution of any interruption routine may be controlled in dependence of whether it is detected that input data has been generated in response to a user interacting with the computer system.

Abstract: An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.

Abstract: A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT) environment. In some embodiments, the custom interrupt service routine does not in any way interfere with the operation of the interrupt handling in a non-VT environment.

Abstract: A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.

Abstract: A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt controller to an interrupt collector, asserting an interrupt signal to the microprocessor from the interrupt collector, and shifting the cause value field into a cause array. The interrupt command include an identifier field, a cause register ID field, and a cause value field, and content of the cause value field is based on a content of the interrupt cause register. The interrupt signal is asserted based on receipt of the identifier field and cause register ID field by the interrupt collector, and the shifting of the cause value field into a cause array within the interrupt collector occurs while the microprocessor services the receipt of the identifier field and cause register ID field from the interrupt collector.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that generates an interrupt vector signal for indicating a storing destination of an interrupt processing program corresponding any of the plurality of interrupt causes; a section that outputs the interrupt signal and the interrupt vector signal to an interrupt process executing circuit; and a section that controls the interrupt signal and an output value of the interrupt vector signal in sync with an interrupt acceptance signal input from the interrupt process executing circuit, the interrupt acceptance signal representing a condition in which an interrupt process is acceptable.

Abstract: A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with its relevant cause information and transmitted by a slave device during a typical response to any operation that a master device may have issued, such as a read or a write. In addition, a link level protocol may be configured in the bus interface of the master device to continually poll specified addresses, or to issue a unique command targeted at interrupts. The master device may be unaware of the unique requests, as the bus may remain idle as seen by the master device. The response to the unique requests may be similar to the interrupt message information transmitted as part of a response to a standard request that may be made by the master device.

Abstract: A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by a peripheral device before an operating system is loaded in the computer system. The virtual wire unit outputs an interrupt control packet to the CPU in response to the control signal wherein the interrupt vector contents carried by the interrupt control packet are ignored by the CPU. After the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal.

Abstract: An interrupt hooking method for a computing apparatus, which includes a processing device and an interrupt controller, includes the steps of: enabling the processing device to convert a hardware interrupt request (IRQ) number of a system control interrupt (SCI) into a predefined interrupt vector according to an operating mode of the interrupt controller; and enabling the processing device to modify a pointer in an interrupt descriptor table that corresponds to the predefined interrupt vector for directing to a corresponding interrupt handler of the application program. A computing apparatus, which includes the processing device that performs the interrupt hooking method, is also disclosed.

Abstract: The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration system is provided to process at least one request associated with an interrupt resource, wherein the request includes at least two dimensions related to an interrupt and an interrupt service component. An arbiter processes the request and returns a subset of interrupt resource ranges in view of available system resources. This multi-dimensional mapping of resources enables coordination across resource pools, processors, buses, and/or other components while mitigating possible run-time problems attributed to one-dimensional systems that may find that suitable resources are unavailable.

Abstract: A method for determining blocking signals is used to judge whether to block a return signal transmitted to a CPU or not when a system management interrupt (SMI) signal is transmitted to the CPU, wherein the return signal is a signal transmitted by a system chip in response to a triggering command transmitted to the system chip by the CPU. The blocking method includes detecting whether the CPU has transmitted the triggering command to the system chip, and detecting whether the system management interrupt signal is transmitted to the CPU. When the CPU has transmitted the triggering command to the system chip, and subsequently the system management interrupt signal has been transmitted to the CPU, it is judged that the system management interrupt signal is used to extract the values in registers of a computer system. Thereby the return signal transmitted to the CPU is blocked.

Abstract: Methods and apparatus to perform event handling operations are described. In one embodiment, after an event (such as an architectural event occurs), the corresponding occurrence response (e.g., a yield event) may cause generation of an interrupt. Other embodiments are also described.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources.

Abstract: An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to different classes of interrupts. A read queue has inputs coupled to the plurality of interrupt holding registers and to the interrupt vector register. Detection logic is coupled between an arbiter, fed by the write and read queues, and a processor for: (a) indicating when an interrupt has passed from the write arbiter to the processor; (b) detecting the interrupt class of such passed interrupt; (c) enabling the one of the bit positions corresponding to the detected interrupt class in the interrupt vector register to store a state indicating the servicing requirement for such detected class of interrupt; and (d) wherein the data stored in the interrupt vector register is passed to the processor through the read queue and the arbiter selector.

Abstract: A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an operating system to the firmware. The identified exception vector is saved to form a saved exception vector. The identified exception vector is then replaced with a substitute vector; and the saved exception vector is restored when control is returned to the operating system to form a restored exception vector. At that point, the restored exception vector is again used to perform error and debugging processes.

Abstract: The present invention system and method enables dynamic reconfiguration of an electronic device with appropriate interrupts in a convenient and efficient manner. A plurality of internal peripherals, an interconnecting component and the external coupling ports are programmably configurable to perform a variety of functions with different interrupts. In response to interrupt request names that are utilized in multiple configurations, an interrupt dispatcher component directs operations to an appropriate interrupt handler for a particular configuration based upon both the configuration image and the interrupt service request indicator. The electronic device can be automatically reconfigured based upon the existence of a predetermined condition by activating different configuration images and associated interrupts are automatically included. Pending interrupt state indicators are resolved (e.g., deleted) during the reconfiguration.

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: An interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.

Abstract: A system, methodology and/or computer architecture that facilitates processing device interrupts (including level-triggered interrupts) in a user-mode process is provided. The kernel interrupt handler can cause a dedicated thread in the process to wake and invoke the driver interrupt service routine. This thread can then return control to the kernel interrupt handler. In addition to processing interrupts in an isolated mode, the context switching technique could be used in any isolated environment to process interrupts via dedicated execution context methods.

Abstract: A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor decodes an interrupt and determines which support processor generated the interrupt. The main processor then determines whether a kernel or an application should process the interrupt. Interrupts such as page faults, segment faults, and alignment errors are handled by the kernel, while “informational” signals, such as stop and signal requests, halt requests, mailbox requests, and DMC tag complete requests are handled by the application. In addition, multiple identical events are maintained, and event data may be included in the interrupt using the invention described herein.

Abstract: The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical processors running virtual machines.

Abstract: An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated idle-acknowledge signals. The clock gating circuit produces a second clock signal based on the first clock signal when fewer than all designated idle-acknowledge signals are received. The clock gating circuit produces no second clock signal when all designated idle-acknowledge signals are received. The bus interface unit receives bus access requests and receives the first and second clock signals. When a bus access request is made, the bus interface unit de-asserts its idle-acknowledge signal and passes the bus access request. The memory interfaces operate on the second clock. One interface receives the bus access request from the bus interface unit, withdraws its idle-acknowledge signal, processes the bus access request, and re-asserts its idle-acknowledge signal upon completion.

Abstract: An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system and interrupt resources of a second type which are not managed by the operating system. Regarding an interrupt generated by an interrupt resource of the first type, the interrupt control apparatus in the present invention launches a common interrupt entry function which is subject to a scheduling process common to the interrupt resources of the first type, based on the address information of the interrupt vector register. At the same time, with regard to an interrupt generated by an interrupt resource of the second type, the interrupt control apparatus in the present invention launches an extended interrupt entry function which is not subject to the aforementioned scheduling process, based on the address information held in the interrupt vector register.

Abstract: In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.

Abstract: A shared-IRQ user-defined interrupt signal handling method and system is proposed, which is designed for use with a computer platform to allow a group of peripheral devices connected to an interrupt-configurable peripheral interface to share system interrupt lines IRQ with another group of peripheral devices connected to an interrupt nonconfigurable peripheral interface; which is characterized by the provision of an interrupt configuration table for defining a virtual device for the interrupt-configurable peripheral interface as well as each specific system interrupt line that is shared by the two groups of peripheral devices. This feature allows system interrupt lines IRQ to be shared by the two different groups of peripheral devices, and also allows the implementation to be easier to carried out than prior art without involving complex and difficult BIOS coding.

Abstract: A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is executed or a ‘to’ address for the branch to case and counts of selected performance monitoring events. A timestamp may be associated with each event. In one embodiment, the pre and post handler is used with trap on branch to log trace records prior to and immediate after taking a branch. In another embodiment, a pre handler is enabled to log trace records that occur prior to executing interrupt service routines. A post handler is enabled to log trace records that occur after the interrupt service routines is executed and prior to returning to normal execution. Resulting low-level performance trace data may be collected by the user at a later time for more structured performance analysis.