Abstract: A method is provided for controlling interrupts in a secure execution mode-capable processor. The method includes detecting an interrupt and performing a predetermined routine in response to detecting the interrupt. The method further includes performing a second routine prior to performing the predetermined routine in response to detecting the interrupt depending upon whether the processor is operating in a secure execution mode.

Abstract: A computer-implemented method for handling pending interrupt vectors of a pending interrupt list is disclosed. The method includes batch-reading the set of pending interrupt vectors into a working list of working interrupt vectors. The method also includes performing interrupt handling of the working interrupt vectors using an interrupt handling arrangement until the working list is empty. The interrupt handling process permits a first incoming interrupt vector that is received by the pending interrupt list after the batch reading to temporarily interrupt the performing interrupt handling of the working interrupt vectors and to be handled on a priority basis by the interrupt handling arrangement if a priority level of the first incoming interrupt vector is higher than a priority level of a first working interrupt vector being currently handled by the interrupt handling arrangement.

Abstract: A system, methodology and/or computer architecture that facilitates processing device interrupts (including level-triggered interrupts) in a user-mode process is provided. The kernel interrupt handler can cause a dedicated thread in the process to wake and invoke the driver interrupt service routine. This thread can then return control to the kernel interrupt handler. In addition to processing interrupts in an isolated mode, the context switching technique could be used in any isolated environment to process interrupts via dedicated execution context methods.

Abstract: A system including an event monitor monitoring at least one transmission link. Each event monitor receives transmission link addresses from an address sequencer and transmits related event data to a centralized storage register. The address sequencer also transmits the addresses to the storage register. The event monitor compares new event data for each address with old event data stored by the event monitor. If a difference is detected, the event monitor sends a strobe signal to the storage register, which stores the event data reflecting the difference and the related address data. The strobe signal is also sent to a signaling device, which sends an interrupt signal to cause a microprocessor to read the event and address data from the storage register. Optionally, the signaling device does not send an interrupt signal until a threshold number of strobe signals have been received.

Abstract: An apparatus and method for handling an interrupt are disclosed. In one embodiment, a processor may receive an interrupt request corresponding to a particular interrupt. The particular interrupt may be one of a group of interrupts. Responsive to receiving the interrupt request, the processor may substitute a vector corresponding to the group of interrupts with a vector corresponding to the particular interrupt. Responsive to the substitution, the processor may then jump to a service routine corresponding to the particular interrupt. Execution of the service routine may resolve the condition which initially caused the interrupt request.

Abstract: The present inventions provide a controlling device for reducing external interrupts for a processor and the method thereof in a real time system. The controlling device decides whether it should trigger a real interrupt to the processor or combining as many interrupts as possible in one interrupt. The controlling device comprises a buffer, an interrupt controller, and an interrupt recording table. The interrupt controller receives interrupts, then saving information of interrupts to the buffer and reading out limitations of the interrupts, the limitations including interrupt deadlines and processing time of each interrupt. The interrupt recording table stores the limitations of each interrupt. The interrupt controller comprises a timer for counting timing references of the interrupt signals. After receiving an interrupt, the interrupt controller compares the limitations and selectively sends an interrupt signal, a real hardware interrupt, to the processor.

Abstract: Multiple levels of interrupts to be utilized in a computer system, which allows, for example, an interrupt with an interrupt level associated with an application to be distinct from an interrupt with an interrupt level associated with a kernel. The kernel level interrupt may be handled quickly via its own handler, while the application level interrupt may be handled more slowly. This may be accomplished by first determining if a first-level handler is installed for the interrupt source. If so, then it may be called. Otherwise, the interrupt source may be masked and a second-level handler may be called. Once this second-level handler has completed its tasks, the interrupt source may then be unmasked. Implementations with three or more levels of interrupt are also possible.

Abstract: A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.

Abstract: An interrupt controller includes circuitry to process at least one end of interrupt (EOI) vector, the circuitry being capable of substantially simultaneously comparing the at least one EOI vector with a plurality of interrupts.

Abstract: A method, system, and article of manufacture to efficiently support interrupts of a computer system. A message-based interrupt from a device of the computer system is intercepted. A fake line-based interrupt for the device corresponding to the message-based interrupt is determined, wherein an operating system (OS) of the computer system is not message-based interrupt capable. The fake line-based interrupt is issued to the OS. A query from the OS regarding the fake line-based interrupt is serviced, the query to determine if the fake line-based interrupt was from the device. An interrupt vector associated with the message-based interrupt is provided to the OS.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: An interface source system providing at least two paths to load an instruction decode register of a coprocessor is disclosed. The interface source system includes an instruction port register, an instruction memory, an instruction decode register, and an interrupt vector table (IVT) stored in the instruction memory. The IVT stores an external instruction vector containing either a predetermined value indicating that the instruction decode register is to be loaded with contents from the instruction port register or an address of an instruction in the instruction memory. A first one of the at least two paths is used to load the instruction from the instruction memory containing the IVT if the external instruction vector contained the address of the instruction in the instruction memory. A second one of the at least two paths is used to load the instruction from the instruction port register if the external instruction vector contained the predetermined value.

Abstract: A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

Abstract: System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node. When a save place node is encountered in a first frame, the traversing jumps to a destination node pointed to by the save place node in a second frame, and continues the traversing there. When a restore place node is encountered when traversing the nodes in the second frame, the traversing returns to the node after the save place node in the first frame and continues the processing in the first frame. The method may be implemented on a system that comprises a processor, a memory, an internal bus, and an external bus controller. The external bus controller and the external bus data may support one or more versions of the Universal Serial Bus standard.

Abstract: A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.

Abstract: A microcomputer has a ROM with pre-stored programs, a RAM storing a revision program for executing an interruption-processing, and a program counter in which an address is successively renewed during an execution of the ROM-stored programs. A first register stores a comparison address corresponding to an optional address of the ROM-stored programs, at which an interruption-processing should be executed to virtually revise the ROM-stored programs. A second register stores a vector address data corresponding to a head address of the revision program. An address comparator compares the comparison address data with a renewed address of the program counter. A controller/calculator makes an access to the head address of the revision program, corresponding to the vector address data of the second register, when there is a coincidence between the comparison address data and the renewed address of the program counter, resulting in an execution of the interruption-processing in accordance with the revision program.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level. The interrupt handling system also permits software based interrupts wherein, for example, one processor may interrupt another processor.

Abstract: A virtual machine monitor (VMM) is included in a computer system that has a protected host operating system (HOS). A virtual machine running at least one application via a virtual operating system is connected to the VMM. Both the HOS and the VMM have separate operating contexts and disjoint address spaces, but are both co-resident at system level. A driver that is downloadable into the HOS at system level forms a total context switch between the VMM and HOS contexts. A user-level emulator accepts commands from the VMM via the system-level driver and processes these commands as remote procedure calls. The emulator is able to issue host operating system calls and thereby access the physical system devices via the host operating system. The host operating system itself thus handles execution of certain VMM instructions, such as accessing physical devices.

Abstract: A pre-stored vector interrupt handling system for rapidly processing interrupt requests from input/output (I/O) devices in processor-based systems includes selection logic and an interrupt vector store to quickly deliver a branch instruction from the interrupt vector store directly to the execution unit of a processor. The interrupt vector store is either pre-loaded with a table of the processor's branch instructions during system initialization or implemented in ROM. During normal operation, when an interrupt is received, a master interrupt signal is issued to the processor, which asserts an instruction cycle mode signal to external chip select logic. The chip select logic deselects the program store and selects the interrupt vector store. An interrupt vector from the vector store is loaded onto the data bus and then directly into the execution unit of the processor.

Abstract: A unified interrupt handling system and method is provided for an embeddable processor having multiple interrupt types. An instruction is inserted into the first vector address that disables the second interrupt mode. At the second vector address, an other instruction is inserted that branches to a common interrupt dispatcher. The common interrupt dispatcher is provided with an interrupt routine that processes the interrupt, and then re-enables the second interrupt modes. Interrupt requests are then processed by the common interrupt dispatcher without interruption.

Abstract: Starting and establishing a dialog between an interruption handler and an operating system for handling of hardware interruptions by the operating system is disclosed. A recommendation for handling such an interruption, and information regarding the interruption, are stored by the interruption handler in a storage accessible by the operating system. The interruption handler calls the operating system at a predetermined interruption handling point thereof, for the operating system to handle the interruption. The handler then determines whether the operating system handled the interruption according to the recommendation.

Abstract: A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Abstract: Mechanisms and techniques operate in a computerized device to execute critical code without interference from interruptions. Critical code is registered for invocation of a critical execution manager in the event of an interruption to the critical code. The critical code is then executed until an interruption to the critical code occurs. After handling the interruption, a critical execution manager is invoked and the critical execution manager detects if an interference signal indicates a reset value. If the interference signal indicates the reset value, the critical execution manager performs a reset operation on the critical code to reset a current state of the critical code to allow execution of the critical code while avoiding interference from handling the interruption and returns to execution of the critical code using the current state of the critical code.

Abstract: A method for interrupt priority encoding and vectoring begins with reading pending interrupt bits from an interrupt status register. An entry in a table is located using the pending interrupt bits. The table has a plurality of vector entries for at least one high priority interrupt bit, and a single entry for at least one low priority interrupt bit. A vector address is fetched from the table and a branch is performed to the vector address. An alternate embodiment has high and low priority interrupt vector tables, where the high low priority interrupt vector table is used if no high priority interrupt is present.

Abstract: An interrupt signal generating device comprises interrupt detection units (20) each adapted to output a detection signal (DET-1 to DET-n) in response to a respective input signal (IN-1 to IN-n) representing an interrupt event; and an interrupt handler unit (15). The interrupt handler has a plurality of input terminals for receiving the detection signals (DET-1 to DET-n) and a plurality of output terminals for outputting corresponding interrupt signals to a CPU, and signal distribution means (16) connecting said input terminals to said output terminals and establishing a predetermined but changeable assignment between the input and output terminals, wherein each of said input terminals is assigned to one of said outputs terminals such that an interrupt signal (INT-1 to INT-n) is output from this output terminal in response to a detection signal (DET-1 to DET-n) applied to the respective input terminal.

Abstract: An integrated circuit implementing a storage-shelf router used alone, or in combination with other storage-shelf routers, and in combination with path controller cards, to interconnect the disks within a storage shelf or disk array to a high-bandwidth communications medium, such as an FC arbitrated loop, through which data is exchanged between the individual disk drives of the storage shelf and a disk-array controller. A set of interconnected storage-shelf routers within a storage shelf can be accessed through a single port of an FC arbitrated loop or other high-bandwidth communications medium. Because, in one implementation, eight storage-shelf routers can be interconnected within a storage shelf to provide highly available interconnection of sixty-four disk drives within the storage shelf to an FC arbitrated loop via a single FC-arbitrated-loop port, a single FC arbitrated loop including a disk-array controller, may interconnect 8,000 individual disk drives to the disk-array controller within a disk array.

Abstract: An interrupt vector is issued by an interrupt controller in response to an interrupt request. A processor executes an interrupt service routine in response to receiving the interrupt vector. Upon the completion of the interrupt service routine, the processor issues an end of interrupt vector to the interrupt controller. The interrupt controller substantially simultaneously compares the end of interrupt vector with a plurality of stored interrupt vectors.

Abstract: Methods and apparatus for a cooperative processing of a task in a multi-threaded computing system are disclosed. In one aspect of the invention, a first thread is arranged to receive a task and only partially process the task. During its processing, the first thread stores processing information that is relevant to future processing in a packet that is associated with the task. Upon completing its processing, the first thread designates a second thread as the owner of the packet. After the second thread obtains ownership of the packet it then further processes the task based at least in part upon the processing information stored in the packet by the first thread. With the described arrangement no synchronization primitives are required for the threads to cooperate in processing the task.

Abstract: A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A method and apparatus for increasing the routing bandwidth of interrupts between cluster manager devices in a clustered multiprocessor system is disclosed. This is accomplished by providing special cluster manager devices that can convert “N” serial messages received from a local APIC to “M” parallel messages, wherein M is less than N. The special cluster manager device then transfers the “M” parallel messages to a receiving cluster manager device. The receiving cluster manager device converts the “M” parallel messages into the original “N” serial messages, and sends the “N” serial messages to the appropriate local APIC within the receiving cluster.

Abstract: An interrupt controller, ASIC, and electronic equipment are provided that make it possible to branch directly to interrupt processing routines at a plurality of locations. When an interrupt controller receives one of IR0 to IR31, it generates an IRQ for a CPU; traps an address AD from the CPU; and after determining that a read instruction for an interrupt vector has been executed, it generates a vector table address VTA corresponding to the interrupt factor with respect to a memory in which the interrupt vector table is stored. The CPU and the memory are connected to a higher-performance ASB, the interrupt controller is connected to a lower-performance APB. A selector selects one of the AD and the VTA, based on a signal from the interrupt controller. A first mode in which the VTA is generated and a second mode in which the interrupt vector is read are switchable.

Abstract: A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions and managing the allocation of file data in the non-volatile memory, an interface control circuit (2) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory (7) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Abstract: An interrupt controller may receive a plurality of interrupts from a variety of sources. An interrupt source register may be utilized to determine the interrupt source. A prioritizer may then determine the priority of each interrupt based on the source of the interrupt. The prioritizer then controls which interrupts are forwarded to a vector generator. The vector generator calculates a interrupt service routine vector of the highest priority interrupt for the core processor. As a result, the core processor receives only the highest priority interrupt vector. When the core processor has finished processing the highest priority interrupt, in some embodiments, the next highest priority interrupt vector is then forwarded for handling.

Abstract: Systems and methods for enabling computer system devices and components are disclosed. A method for use in a computer system having a processor includes receiving an input from a device coupled to the system and generating an interrupt signal in response to the input. The method further includes placing the system in a management mode in response to the interrupt and processing an interrupt routine associated with the interrupt. The method further includes processing the interrupt routine located in an upper level of the system's available memory and providing information to a driver associated with the system.

Abstract: A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives transactions from a master device, communicates with a master device as another master device or as a slave device, and queues transactions received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency. The node controller also implements an interrupt arbitration scheme designed to choose among multiple eligible interrupt distribution units without using dedicated sideband signals on the bus.

Abstract: A method of handling an interrupt request in a computer system by programmably setting an override address associated with a specific interrupt service routine, and servicing an interrupt request based on the override address, which is different from a power-on default address associated with the same interrupt service routine. The method may determine whether the interrupt service routine is critical and, if so, set the override address to a physical location in the on-chip memory of the processing unit, instead of in the off-chip memory (RAM). Override address registers are accessed via the special purpose registers of the processing unit. A validation bit may be turned on in response to the setting of the override address, with both the default address and the override address being provided as separate inputs to a multiplexing device controlled by the validation bit. The override address is forwarded from the multiplexing device to an instruction fetch unit whenever the validation bit has been set.

Abstract: An article representing a processor providing event handling functionality is described. According to one embodiment of the invention, the article includes a machine readable medium storing data representing a processor including an instruction set unit and an event handling unit, as well as a first plurality of event handlers that includes a first event handler. The instruction set unit is to support a first and second instruction sets. Problems that arise during the processing of instructions from the first and second unit are to cause the article to execute the appropriate one of the first plurality of event handlers. At least some of the first set of events are mapped to different ones of the first plurality of event handlers. All of the second set of events are mapped to the first event handler.

Abstract: An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.

Abstract: To downsize the circuit scale of a CPU in a microcomputer capable of executing multiple interrupt, an interrupt controller includes an interrupt mask level register. The CPU temporarily transfers or stacks processing data into a RAM. The processing data include a PSR (i.e., system register) value and a PC (i.e., program counter) value of the interrupt processing presently running in CPU. At the same time, the CPU sends a stack signal “STK” to the interrupt controller. In response to the stack signal “STK”, the interrupt controller temporarily transfers the interrupt mask level stored in the register into the RAM. When the CPU restarts the suspended interrupt processing, the CPU reads the PSR value and the PC value from the RAM while the CPU produces a return signal “RTN.” In response to the return signal “RTN”, the interrupt mask level is returned from the RAM to the register.

Abstract: A computer system includes a processor for executing a program and an interruption handler from a memory. The processor includes an instruction pointer indicating a memory location of a current executing instruction. The processor executes a trampoline check instruction in the program which tests a condition and if the condition is true, causes an interruption and supplies an address displacement. The interruption handler responds to the interruption and restarts execution of the program at a restart point indicating a memory location of a special handler in the program. The restart point is a sum of the address displacement and a value of the instruction pointer at the time of the interruption. If the condition is false, normal control flow of the program is continued.

Abstract: A system, method and article of manufacture are provided for minimizing the amount of changes that need to be made to exception handling logic when new exceptions are added. Exceptions are organized into hierarchies in a polymorphic exception handler. A root of one of the hierarchies in which an exception occurs is caught. The exception is instructed to rethrow itself. The rethrown exception is caught and identified. A type of the rethrown exception is determined and a message is outputted indicating the type of the rethrown exception.

Abstract: A data processing system (10) has a multifield register (62) which has two fields, a selection field (90) and an information field (91). The selection field (90) identifies the source of the information loaded in the information field (91). In one embodiment, the multifield register (62) is an interrupt flag register (62) and the selection field (90) identifies which of the two registers portions (59,60) of the interrupt pending register (58) is loaded into the multifield register (62). The low register portion (59) can identify up to thirty-one sources of interrupt requests and the high register portion (60) can identify up to thirty-two sources of interrupt requests even though the information field (91) is only thirty-one bits. This is achievable because the selection field (90) may serves a dual function, namely as a flag bit and as bit-32 of the interrupt pending register (58).

Abstract: A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H′400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

Abstract: Run time modification of interrupt service routines in an embedded operating system installs a soft vectored interrupt service routine into the operating system kernel at the time of the kernel generation. The soft vectored interrupt service routine refers interrupt service calls to installable interrupt service routines that may be loaded subsequently on a real-time basis. In this way, flexible interrupt service routine response may be obtained for a wide variety of hardware combinations, unanticipated at the time of the generation of the operating system kernel.

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.