Abstract: A control system for use in a bus system having at least two transmission lines, having a first control device which has a first termination path and a first terminating resistor connected to the first termination path, a second control device which has a second termination path and a second terminating resistor connected to the second termination path, a first connector which is adapted to connect the first control device to the transmission lines and therefore to integrate the first control device in the bus system, a second connector which is adapted to connect the second control device to the transmission lines and therefore to integrate the second control device in the bus system, wherein the first connector and the second connector are different to one another.

Abstract: A configuration management device provided with: a configuration storage means for storing a bridge that includes a virtual bridge and the configuration information of input/output devices; a bus recognition means for reading the configuration information of input/output devices connected to the bridge from the input/output devices and storing the read information in the configuration storage means; a virtual resource definition storage means for defining a virtual connection between the input/output devices connected to a connection means that is not the bridge and the virtual bridge; and a device access transfer means for receiving a configuration information read request for input/output devices connected to the virtual bridge that is transmitted by the bus recognition means, reading the configuration information from the input/output devices the virtual connection of which is defined, and transmitting the read configuration information to the bus recognition means.

Abstract: A method for mapping LUNs (logical unit numbers) in storage memory, performed by a storage system, is provided. The method includes determining a set of LUNs in the storage memory and generating a mapping from a logical address space to all of the LUNs in the set, based on the determining, so that each logical address in the logical address space maps to one LUN in the set. The method includes accessing one or more of the LUNs in accordance with the mapping.

Abstract: Techniques and systems for performing a network activity within a network. The technique includes assigning one or a plurality of network devices subnets with network devices for performing network activities. Network devices within the assigned network device subnets can be assigned to act as a primary network device and a backup network device. The primary network device can perform the network activity. The backup network devices can monitor the primary network device and continue performing the network activities if the primary network device fails or is rogue.

Abstract: A computer program product may include storage media embodying program instructions executable by a baseboard management controller (BMC) within a compute node to: receive a request to install a central processing unit (CPU) in the compute node; identify a current hardware configuration of the compute node; identify a plurality of available locations within the compute node that are compatible with installation of the CPU; calculate, for each of the identified plurality of available locations, a predicted performance score for the CPU on the basis that the CPU were to be installed in the available location, wherein the predicted performance scores are calculated in response to receiving the request; select a location from among the plurality of available locations that is associated with the greatest performance score for the CPU; and generate user output indicating the selected location where the CPU should be installed.

Abstract: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

Abstract: A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics and includes a primary master central processing unit.

Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Abstract: An operation method of a data storage system including storage devices includes transmitting a packet to a host including information indicating whether the storage devices are capable of resource sharing; transmitting ID information of the storage devices capable of resource to the host; transmitting by a requesting device among the capable storage devices a resource sharing request message to the remaining storage devices capable of resource sharing; and performing the resource sharing on at least one of the remaining storage devices.

Abstract: Systems and methods for synchronizing a redundant array of independent disks (RAID) controller with a management controller. The system includes the management controller, a RAID having the RAID controller connected to the management controller; and a serial bus connected to the management controller and the RAID controller. The RAID controller is configured to, when the RAID is powered up, assert the serial bus with a ready signal, and the management controller is configured to, upon checking the ready signal from the serial bus, construct a communication with the RAID controller for communicating with the RAID.

Abstract: A power control apparatus includes a processor configured to collect first information related to operation of a performing unit configured to perform data processing and information related to operation of a bus configured to transfer data; determine an operating frequency and an operating voltage for the performing unit, based on the collected information; estimate based on the collected information, a period elapsing until the performing unit suspends operation and a period elapsing until the bus suspends operation; derive a discriminant that obtains a difference of total power consumption and power consumption pre-switching; and execute a switching of an operating frequency and an operating voltage of the performing unit, based on a value of the discriminant.

Abstract: A method of authenticating shared peripheral component interconnect express devices of a switched fabric includes associating at least one requester identifier with a physical function of a device on the switched fabric and instantiating a virtual function of the device based on the physical function. The virtual function includes the associated at least one requester identifier. The method further includes accepting memory-mapped input/output traffic through the virtual function only from a requester having a corresponding requester identifier matching an associated requester identifier of the virtual function. The method may also include allowing a write operation of the virtual function or the physical function only to an address residing within an allowable address range associated with the device.

Abstract: A processor having a streaming unit is disclosed. In one embodiment, a processor includes a streaming unit configured to load one or more input data streams from a memory coupled to the processor. The streaming unit includes an internal network having a plurality of queues configured to store streams of data. The streaming unit further includes a plurality of operations circuits configured to perform operations on the streams of data. The streaming unit is software programmable to operatively couple two or more of the plurality of operations circuits together via one or more of the plurality of queues. The operations circuits may perform operations on multiple streams of data, resulting in corresponding output streams of data.

Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.

Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.

Abstract: A vehicle computing system includes a vehicle computing module mounted on a main system board. The module includes a computing module circuit board with computing components mounted thereon including a central processing unit and a main memory. An edge connector connects the computing module circuit board to an edge connector socket on the main system board. A plurality of computing function interfaces are connected to the edge connector, and include a configuration interface connected to the central processing unit and, via the edge connector, to a controller on the main system board. The controller configures the central processing unit for operation in the vehicle computing system by enabling specification of the computing function interfaces during a vehicle computing module configuration. The computing function interfaces are configured during the vehicle computing module configuration to process data received by the vehicle computing module via the computing function interfaces.

Abstract: A method, device, and system for packet transmission on the PCIE bus according to the embodiments of the present invention, a SCSI protocol packet is encapsulated to obtain an encapsulated SCSI protocol packet, and the encapsulated SCSI protocol packet is carried in a PCIE data packet, and then the PCIE data packet carrying the encapsulated SCSI protocol packet is transmitted to the receiver device through the PCIE bus. Thereby, transmission of SCSI protocol packets is implemented on the PCIE bus, and any devices interconnected through the PCIE bus can operate each other through SCSI protocol packets with a high data transmission bandwidth and high processing speed, without requiring a specific physical device or adapter to perform protocol conversion.

Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.

Abstract: Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data trans

Abstract: Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data trans

Abstract: The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table.

Abstract: A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A communication network for a low-voltage switchboard comprising three types of communication bus. The first communication bus is designed to provide a first communication channel with at least one electronic protection device. A second communication bus is designed to provide a second communication channel with said electronic protection device. At least one third communication bus (13) is designed to provide a third communication channel between said at least one protection and control unit and one or more additional electronic modules (6A, 6B, 6C, 6E, 6F). The second communication bus is associated with a second, higher user access level than the first user access level associated with said first communication bus.

Abstract: A storage network includes at least one storage processor. At least one switch is coupled to the at least one storage processor. At least one nontransparent bridge is coupled to the at least one switch. The at least one nontransparent bridge includes at least one addressable endpoint. At least one storage device is coupled to the nontransparent bridge. At least one baseboard management controller is coupled to the at least one addressable endpoint.

Abstract: A high-current Multi-Port USB hub has a microcontroller that selectively switches the hub between low current synchronizing state and high current charging state. During charging state in excess of two Amps of current can be provided to each device connected to the hub. Each USB port circuit includes a power FET to selectively provide current to the USB port according to the state of the hub. Current sensors on each of the USB ports detects an amount of current being drawn by a device connected to the USB port. Each USB port is provided with indicators to indicate the charged state of the device connected to that port. The charge state of the device is also provided to the microcontroller which provides a summary status indication of the set of devices connected to the USB hub.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EEPROMs is written to registers in the physical layer device to configure the physical layer device.

Abstract: Embodiments of the invention includes a plurality of connectors configured to connect a plurality of data storage host bus adaptors to a plurality of data storage device subassemblies such that at least one lane of low voltage differential signal pairs from each of the plurality of host bus adaptors is connected to each of the data storage device subassemblies. The invention improves the electrical interconnections in a data storage array such as a JBOD enclosure or data storage server. The invention minimizes the number of connectors by reducing the number of printed circuit boards, and eliminates the need to add signal repeaters to maintain signal quality. The invention also increases the cooling efficiency of the enclosure by increasing air flow by reducing the number of printed circuit boards in the data storage array.

Abstract: In one embodiment, a multi-protocol communication circuit is provided. The communication circuit includes a plurality of protocol bridge circuits, each configured to convert data between a first format and a respective second format corresponding to a respective communication protocol. A switch network provides routable connections between the protocol bridge circuits and one or more interface circuits. Each interface circuit is configured to convert data between the first format and a raw data format. Due to the common first format, an interface circuit may be configured for select ones of different communication protocols by routing data in the first format between the interface circuit and a protocol bridge circuit corresponding to the select one of the different communication protocols.

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

Abstract: A computer system includes a central processing unit (CPU), a north bridge, a south bridge, a bridge and a slot. The north bridge is electrically connected to the CPU. The bridge is electrically connected to the north bridge and the south bridge, and the connector is connected to the bridge. The bridge generates a first data and a second data according to the data packages transmitted from the north bridge and adjusts the output bandwidth of the first data and the second data according to a channel control signal. The south bridge receives or transfers the first data via the bridge so as to communicate with the north bridge. The slot is electrically connected to the bridge and receives or transfers the second data via the bridge so as to communicate with the north bridge.

Abstract: A switch apparatus capable of being coupled to a computer and a plurality of devices, the switch apparatus includes: a first bridge coupled to the computer; a second-bridge group coupled to the devices; and a controller for controlling the connection relationship between the first bridge and the second-bridge group, wherein the controller assigns physical identifiers having different bus identifiers to the plurality of devices, assigns logical identifiers to the devices in accordance with an identifier assigned to the first bridge in response to an instruction for reading connection states of the devices received from the computer when the computer is coupled to the first bridge, and converts a physical identifier and a logical identifier of a packet transmitted between the first bridge and the second-bridge group in accordance with the correspondence relationships between the physical identifiers and the logical identifiers.

Abstract: A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topology in such a way that the first bus output is connected at least indirectly to the second bus input and the second bus output is connected at least indirectly to the first bus input via the bus. The bus in the circuit arrangement can be separated to obtain a line topology and can be configured as bus-terminating at one of the bus inputs or bus outputs. A system for the functional testing of bus participants on a bus in a simulation environment is provided.

Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.

Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.

Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

Abstract: A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output.

Abstract: The inventive concept relates to a user system including a solid state disk. The user system may include a main memory for storing data processed by a central processing unit; and a solid state disk for storing the selected data among data stored in the main memory. The main memory and the solid state disk form a single memory hierarchy. Thus, the user system of the inventive concept can rapidly process data.

Abstract: A fabric interconnect system may provide a data path between nodes and/or processing elements within an interconnection fabric. Identifiers may be assigned to particular components associated with the interconnection fabric. These identifiers may uniquely identify the particular components, and may indicate a path between a root node and a particular component. In some embodiments, the identifiers include turn counts and turn values that specify a turn-based bath from the root node to a particular component. One or more identifier acceptance rules may be used in order to determine whether a given component should accept and store a particular identifier that the component receives. For example, a lower priority identifier may be discarded in favor of a higher priority identifier.

Abstract: An information system includes a configuration controller board having a capability to set, to each I/O bus bridge device in the alternative I/O board, the logical bus number set in corresponding I/O bus bridge device in the failed I/O board 20, and to set to the I/O bus bridge device in the system board 10 connected with the alternative I/O board, the same downstream side logical bus number as that of the I/O bus bridge device in the system board connected with the failed I/O board.

Abstract: In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Abstract: One or more techniques and/or systems are disclosed for enabling communication between a SAS communication port of a SAS communication component and multiple storage devices. In a first example, a first SAS to SATA bridge chip and a second SAS to SATA bridge chip may be configured to route data from a SAS communication component to multiple storage devices. In a second example, a SAS to SATA bridge chip and a port multiplier may be configured to route data from a SAS communication component to multiple storage devices. In a third example, a four port SAS to SATA bridge comprising two SAS ports and two SATA ports may be configured to route data from a SAS communication component to multiple storage devices. Supporting two or more storage devices with a single SAS communication port allows storage enclosures to increase storage capacity, while decreasing cost per slot.

Abstract: In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

Abstract: A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.

Abstract: In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.